From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE6D8C43219 for ; Mon, 17 Oct 2022 17:20:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230180AbiJQRU5 (ORCPT ); Mon, 17 Oct 2022 13:20:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230154AbiJQRU4 (ORCPT ); Mon, 17 Oct 2022 13:20:56 -0400 Received: from mail-qv1-xf2c.google.com (mail-qv1-xf2c.google.com [IPv6:2607:f8b0:4864:20::f2c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4F0371711 for ; Mon, 17 Oct 2022 10:20:53 -0700 (PDT) Received: by mail-qv1-xf2c.google.com with SMTP id f14so7825063qvo.3 for ; Mon, 17 Oct 2022 10:20:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=d8KFvXWXk+yHpFJT0KTXsfMVjC6a7dZVFBnEd/ZjfUI=; b=wf/PwgJ+34F7/B0pCzFjaKHZmmo9BpTXsHL/cr3KMWfaitH5BdFvQnDtuQJn8txoHT J0m4i7BCubMwdI8Sb8A8D/kWG4s5Gr66h1DeBNFd8NU3UCHm0N21AMI/nczPyaaPmizi v2Ger7sY7Bks0BYMqmBl0gWu+UYdbcKA2xB9e6ze+eNLcElnazUc7foBOURKeeIZPHO7 4AYmUj1SmNorM8nI1dG9t7z1ZSQnpfcge2nZYjS4UZc0mds6hIUy3+49uQzG7TXIRsFS 5ZTp/KB18Qe1dy6g62cTgPwbGMwFD7dc1xyQFagDirmlVJdOpEPiRie2a6vsl6mpxp5q k7NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=d8KFvXWXk+yHpFJT0KTXsfMVjC6a7dZVFBnEd/ZjfUI=; b=1iGJCTMTg9EpLEJIBAJwwL1wtBjlVnNVFOATKR+Xw17s+nePDjeq8mhhwMBprl+kSM PcOjPzrTQ+zr7UZikbQWVK+Pd5jzgq+NegdjQ1MefyUMvLNb/ApEXPWDB/zOQ2f/G4oU 80xq5HbeXThiDTZQwXT7n2s6/ZNezIW+1a8UbDwr7Dfmc9DvP/MPGu3HeRDyEs4DWnb3 t1G3XxAV2yDt229QwbQyd2PP3dUr2OY0H2H+HB1ltclwzmzXrhOuDRJE3FTDp1DDPDFZ ldChNtHa+TYRjlrLRDboBNQrsaRTFq+eK6sAqZUkeoiaMEqQHbCWel7pRpF5UXsr/pvi qUOg== X-Gm-Message-State: ACrzQf1Qn28p84nFqsDTgSI9I9Rkyoep1fSRaRyf0CqKa22dbPCcnHkg DaLTEJSxpGPKL2QGZ1vYd86IBA== X-Google-Smtp-Source: AMsMyM6/3ZjXIrE4Qn/bdGiyrsjypB6R/Ooht83aXja1DRa3oM95NXtfLHU3Qi+LnuCL5VdxoSK15Q== X-Received: by 2002:a0c:9a4c:0:b0:4b1:d3ef:85cc with SMTP id q12-20020a0c9a4c000000b004b1d3ef85ccmr9242276qvd.105.1666027252384; Mon, 17 Oct 2022 10:20:52 -0700 (PDT) Received: from [10.101.5.247] ([148.59.24.28]) by smtp.gmail.com with ESMTPSA id bv8-20020a05622a0a0800b0038b684a1642sm246319qtb.32.2022.10.17.10.20.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Oct 2022 10:20:51 -0700 (PDT) Message-ID: Date: Mon, 17 Oct 2022 13:20:49 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.2 Subject: Re: [PATCH 10/15] dt-bindings: phy: qcom,qmp-pcie: add sc8280xp bindings Content-Language: en-US To: Johan Hovold , Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221017145328.22090-1-johan+linaro@kernel.org> <20221017145328.22090-11-johan+linaro@kernel.org> From: Krzysztof Kozlowski In-Reply-To: <20221017145328.22090-11-johan+linaro@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 17/10/2022 10:53, Johan Hovold wrote: > Add bindings for the PCIe QMP PHYs found on SC8280XP. > > The PCIe2 and PCIe3 controllers and PHYs on SC8280XP can be used in > 4-lane mode or as separate controllers and PHYs in 2-lane mode (e.g. as > PCIe2A and PCIe2B). > > The configuration for a specific system can be read from a TCSR register. > > Signed-off-by: Johan Hovold > --- > .../bindings/phy/qcom,qmp-pcie-phy.yaml | 163 ++++++++++++++++++ > 1 file changed, 163 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml > new file mode 100644 > index 000000000000..82da95eaa9d6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml Filename based on compatible, so for example: qcom,sc8280xp-qmp-pcie-phy.yaml > @@ -0,0 +1,163 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm QMP PHY controller (PCIe) > + > +maintainers: > + - Vinod Koul > + > +description: > + QMP PHY controller supports physical layer functionality for a number of > + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. > + > +properties: > + compatible: > + enum: > + - qcom,sc8280xp-qmp-gen3x1-pcie-phy > + - qcom,sc8280xp-qmp-gen3x2-pcie-phy > + - qcom,sc8280xp-qmp-gen3x4-pcie-phy > + > + reg: > + minItems: 1 > + maxItems: 2 > + > + clocks: > + maxItems: 6 > + > + clock-names: > + items: > + - const: aux > + - const: cfg_ahb > + - const: ref > + - const: rchng > + - const: pipe > + - const: pipediv2 > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > + reset-names: > + items: > + - const: phy > + > + vdda-phy-supply: true > + > + vdda-pll-supply: true > + > + qcom,4ln-config-sel: > + description: 4-lane configuration as TCSR syscon phandle, register offset > + and bit number > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + maxItems: 3 You have only one phandle, so you need to describe the items and limit their number, like here: https://elixir.bootlin.com/linux/v5.18-rc1/source/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml#L42 This allows you to skip most of property description. > + > + "#clock-cells": > + const: 0 > + > + clock-output-names: > + maxItems: 1 > + > + "#phy-cells": > + const: 0 Best regards, Krzysztof