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[72.83.177.149]) by smtp.gmail.com with ESMTPSA id hh6-20020a05622a618600b00343057845f7sm983408qtb.20.2022.10.17.19.01.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Oct 2022 19:01:38 -0700 (PDT) Message-ID: Date: Mon, 17 Oct 2022 22:01:30 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Subject: Re: [PATCH] arm64: dts: mt8195: Add Ethernet controller Content-Language: en-US To: Biao Huang , Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, macpaul.lin@mediatek.com References: <20221017095834.7675-1-biao.huang@mediatek.com> From: Krzysztof Kozlowski In-Reply-To: <20221017095834.7675-1-biao.huang@mediatek.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 17/10/2022 05:58, Biao Huang wrote: > Add Ethernet controller node for mt8195. > > Signed-off-by: Biao Huang > --- > arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 88 ++++++++++++++++++++ > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 87 +++++++++++++++++++ > 2 files changed, 175 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts > index 4fbd99eb496a..02e04f82a4ae 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts > +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts > @@ -258,6 +258,72 @@ &mt6359_vsram_others_ldo_reg { > }; > > &pio { > + eth_default: eth_default { No underscores in node names. Please also be sure your patch does not bring new warnings with `dtbs_check` (lack of suffix above could mean it brings...) > + txd_pins { No underscores > + pinmux = , > + , > + , > + ; > + drive-strength = ; > + }; > + cc_pins { Ditto... and so on. > + pinmux = , > + , > + , > + ; > + drive-strength = ; > + }; > + rxd_pins { > + pinmux = , > + , > + , > + ; > + }; > + mdio_pins { > + pinmux = , > + ; > + input-enable; > + }; > + power_pins { > + pinmux = , > + ; > + output-high; > + }; > + }; > + > + eth_sleep: eth_sleep { > + txd_pins { > + pinmux = , > + , > + , > + ; > + }; > + cc_pins { > + pinmux = , > + , > + , > + ; > + }; > + rxd_pins { > + pinmux = , > + , > + , > + ; > + }; > + mdio_pins { > + pinmux = , > + ; > + input-disable; > + bias-disable; > + }; > + power_pins { > + pinmux = , > + ; > + input-disable; > + bias-disable; > + }; > + }; > + > gpio_keys_pins: gpio-keys-pins { > pins { > pinmux = ; > @@ -434,6 +500,28 @@ &xhci0 { > status = "okay"; > }; > > +ð { > + phy-mode ="rgmii-rxid"; > + phy-handle = <ð_phy0>; > + snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; > + snps,reset-delays-us = <0 10000 10000>; > + mediatek,tx-delay-ps = <2030>; > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <ð_default>; > + pinctrl-1 = <ð_sleep>; > + status = "okay"; > + > + mdio { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + eth_phy0: eth_phy0@1 { ethernet-phy@1 > + compatible = "ethernet-phy-id001c.c916"; > + reg = <0x1>; > + }; > + }; > +}; > + > &xhci1 { > vusb33-supply = <&mt6359_vusb_ldo_reg>; > status = "okay"; > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index 905d1a90b406..aa1fcc3b9cb6 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -1042,6 +1042,93 @@ spis1: spi@1101e000 { > status = "disabled"; > }; > > + stmmac_axi_setup: stmmac-axi-config { > + snps,wr_osr_lmt = <0x7>; > + snps,rd_osr_lmt = <0x7>; > + snps,blen = <0 0 0 0 16 8 4>; > + }; > + > + mtl_rx_setup: rx-queues-config { > + snps,rx-queues-to-use = <4>; > + snps,rx-sched-sp; > + queue0 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x0>; > + }; > + queue1 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x0>; > + }; > + queue2 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x0>; > + }; > + queue3 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x0>; > + }; > + }; > + > + mtl_tx_setup: tx-queues-config { > + snps,tx-queues-to-use = <4>; > + snps,tx-sched-wrr; > + queue0 { > + snps,weight = <0x10>; > + snps,dcb-algorithm; > + snps,priority = <0x0>; > + }; > + queue1 { > + snps,weight = <0x11>; > + snps,dcb-algorithm; > + snps,priority = <0x1>; > + }; > + queue2 { > + snps,weight = <0x12>; > + snps,dcb-algorithm; > + snps,priority = <0x2>; > + }; > + queue3 { > + snps,weight = <0x13>; > + snps,dcb-algorithm; > + snps,priority = <0x3>; > + }; > + }; > + > + eth: ethernet@11021000 { > + compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; > + reg = <0 0x11021000 0 0x4000>; > + interrupts = ; > + interrupt-names = "macirq"; > + mac-address = [00 55 7b b5 7d f7]; How is this property of a SoC? Are you saying now that all MT8195 SoCs have the same MAC address? Best regards, Krzysztof