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Sun, 15 Aug 2021 23:27:50 -0700 Envelope-to: git@xilinx.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, bgolaszewski@baylibre.com, iwamatsu@nigauri.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, zou_wei@huawei.com, arnd@arndb.de, robh@kernel.org Received: from [172.30.17.109] (port=39402) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mFW69-0008W8-D5; Sun, 15 Aug 2021 23:27:49 -0700 Subject: Re: [PATCH V2 2/3] dt-bindings: gpio: zynqmp: Add binding documentation for modepin To: Rob Herring , Piyush Mehta CC: , , , , , , , , , , , , , , References: <20210805174219.3000667-1-piyush.mehta@xilinx.com> <20210805174219.3000667-3-piyush.mehta@xilinx.com> From: Michal Simek Message-ID: Date: Mon, 16 Aug 2021 08:27:45 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: aacb8674-7152-4885-6c8a-08d9607eff58 X-MS-TrafficTypeDiagnostic: DM5PR02MB2347: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2021 06:28:01.4957 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aacb8674-7152-4885-6c8a-08d9607eff58 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0016.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR02MB2347 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 8/13/21 9:01 PM, Rob Herring wrote: > On Thu, Aug 05, 2021 at 11:12:18PM +0530, Piyush Mehta wrote: >> This patch adds DT binding document for zynqmp modepin GPIO controller. >> Modepin GPIO controller has four GPIO pins which can be configurable >> as input or output. >> >> Modepin driver is a bridge between the peripheral driver and GPIO pins. >> It has set and get APIs for accessing GPIO pins, based on the device-tree >> entry of reset-gpio property in the peripheral driver, every pin can be >> configured as input/output and trigger GPIO pin. >> >> For more information please refer zynqMp TRM link: >> Link: https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf >> Chapter 2: Signals, Interfaces, and Pins >> Table 2-2: Clock, Reset, and Configuration Pins - PS_MODE >> >> Signed-off-by: Piyush Mehta >> --- >> Changes in v2: >> - Addressed review comments: Update commit message >> >> https://lore.kernel.org/linux-arm-kernel/20210615080553.2021061-2-piyush.mehta@xilinx.com/T/#mbd1fbda813e33b19397b350bde75747c92a0d7e1 >> https://lore.kernel.org/linux-arm-kernel/20210615080553.2021061-2-piyush.mehta@xilinx.com/T/#me82b1444ab3776162cdb0077dfc9256365c7e736 >> --- >> .../bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 41 ++++++++++++++++++++++ >> 1 file changed, 41 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml >> >> diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml >> new file mode 100644 >> index 0000000..39d78f8 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml >> @@ -0,0 +1,41 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: "http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#" >> +$schema: "http://devicetree.org/meta-schemas/core.yaml#" >> + >> +title: ZynqMP Mode Pin GPIO controller >> + >> +description: >> + PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin >> + GPIO controller with configurable from numbers of pins (from 0 to 3 per >> + PS_MODE). Every pin can be configured as input/output. >> + >> +maintainers: >> + - Piyush Mehta >> + >> +properties: >> + compatible: >> + const: xlnx,zynqmp-gpio-modepin >> + >> + gpio-controller: true >> + >> + "#gpio-cells": >> + const: 2 >> + >> +required: >> + - compatible >> + - gpio-controller >> + - "#gpio-cells" >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + modepin_gpio: gpio { >> + compatible = "xlnx,zynqmp-gpio-modepin"; >> + gpio-controller; >> + #gpio-cells = <2>; > > No way to interact with this h/w? > > As it is part of the firmware interface, it must be a child node in the > firmware node schema. Actually it is there. Only example is not showing this properly. https://github.com/Xilinx/u-boot-xlnx/blob/master/arch/arm/dts/zynqmp.dtsi#L250 Piyush: Can you please do it as we have done with pinctrl. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml?h=v5.14-rc6#n301 like this zynqmp_firmware: zynqmp-firmware { modepin_gpio: gpio { compatible = "xlnx,zynqmp-gpio-modepin"; gpio-controller; #gpio-cells = <2>; }; }; That dt labels can be also removed because they are not needed in example. Thanks, Michal