Re: [PATCH 2/2] interconnect: qcom: Add SDX65 interconnect provider driver

[Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]

On 12/04/2022 07:07, Rohit Agarwal wrote:
> Add driver for the Qualcomm interconnect buses found in SDX65 based
> platforms.

Thank you for your patch. There is something to discuss/improve.

> +
> +static struct qcom_icc_bcm *system_noc_bcms[] = {

It can be array of const pointers, if you rebase on this:
"interconnect: qcom: constify icc_node pointers"
(I just sent it but I am not sure if it made it to the lists)

> +	&bcm_ce0,
> +	&bcm_pn0,
> +	&bcm_pn1,
> +	&bcm_pn2,
> +	&bcm_pn3,
> +	&bcm_pn4,
> +	&bcm_sn0,
> +	&bcm_sn1,
> +	&bcm_sn2,
> +	&bcm_sn3,
> +	&bcm_sn5,
> +	&bcm_sn6,
> +	&bcm_sn7,
> +	&bcm_sn8,
> +	&bcm_sn9,
> +	&bcm_sn10,
> +};
> +
> +static struct qcom_icc_node *system_noc_nodes[] = {

The same.


> +	[MASTER_AUDIO] = &qhm_audio,
> +	[MASTER_BLSP_1] = &qhm_blsp1,
> +	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
> +	[MASTER_QPIC] = &qhm_qpic,
> +	[MASTER_SNOC_CFG] = &qhm_snoc_cfg,
> +	[MASTER_SPMI_FETCHER] = &qhm_spmi_fetcher1,
> +	[MASTER_ANOC_SNOC] = &qnm_aggre_noc,
> +	[MASTER_IPA] = &qnm_ipa,
> +	[MASTER_MEM_NOC_SNOC] = &qnm_memnoc,
> +	[MASTER_MEM_NOC_PCIE_SNOC] = &qnm_memnoc_pcie,
> +	[MASTER_CRYPTO] = &qxm_crypto,
> +	[MASTER_IPA_PCIE] = &xm_ipa2pcie_slv,
> +	[MASTER_PCIE_0] = &xm_pcie,
> +	[MASTER_QDSS_ETR] = &xm_qdss_etr,
> +	[MASTER_SDCC_1] = &xm_sdc1,
> +	[MASTER_USB3] = &xm_usb3,
> +	[SLAVE_AOSS] = &qhs_aoss,
> +	[SLAVE_APPSS] = &qhs_apss,
> +	[SLAVE_AUDIO] = &qhs_audio,
> +	[SLAVE_BLSP_1] = &qhs_blsp1,
> +	[SLAVE_CLK_CTL] = &qhs_clk_ctl,
> +	[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
> +	[SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
> +	[SLAVE_ECC_CFG] = &qhs_ecc_cfg,
> +	[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
> +	[SLAVE_IPA_CFG] = &qhs_ipa,
> +	[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
> +	[SLAVE_PCIE_PARF] = &qhs_pcie_parf,
> +	[SLAVE_PDM] = &qhs_pdm,
> +	[SLAVE_PRNG] = &qhs_prng,
> +	[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
> +	[SLAVE_QPIC] = &qhs_qpic,
> +	[SLAVE_SDCC_1] = &qhs_sdc1,
> +	[SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
> +	[SLAVE_SPMI_FETCHER] = &qhs_spmi_fetcher,
> +	[SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex,
> +	[SLAVE_TCSR] = &qhs_tcsr,
> +	[SLAVE_TLMM] = &qhs_tlmm,
> +	[SLAVE_USB3] = &qhs_usb3,
> +	[SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy,
> +	[SLAVE_ANOC_SNOC] = &qns_aggre_noc,
> +	[SLAVE_SNOC_MEM_NOC_GC] = &qns_snoc_memnoc,
> +	[SLAVE_IMEM] = &qxs_imem,
> +	[SLAVE_SERVICE_SNOC] = &srvc_snoc,
> +	[SLAVE_PCIE_0] = &xs_pcie,
> +	[SLAVE_QDSS_STM] = &xs_qdss_stm,
> +	[SLAVE_TCU] = &xs_sys_tcu_cfg,
> +};
> +
> +static struct qcom_icc_desc sdx65_system_noc = {

All these structures can be const.

Best regards,
Krzysztof