From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5687C2E7394; Mon, 1 Jun 2026 11:30:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780313431; cv=none; b=GoZCMRz9/Y61TUkQ/Q8bE21g2PLCKOM3aM2lzBDNFv5iRJirZZLtoH+/0h0jVS2qdDr4ytiMiw6itJ9ij3UzBC/y7IJeQ4BI2JFxAM0p0f+8w5mIay0U1sSpLQK/NRpZfFC/4Wdi+NFaIgmhzLLODGpYshLNLvcNoLdMFEpAjvA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780313431; c=relaxed/simple; bh=8Ucj4fp6cxZ4+DnmoRcnCdkdviUW0b3KUei+/dNPcYY=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=tdEbz57LHbO/QtZBE10qqANESup7yPCmcfh2LzcD6VRE3043iAnmvyV+AfN15/wIeWMXQPEiBle1zrOpgJseO85ANyPsRfjgP/9OyA1R2JHcLLe/h6YDxYiRSxSKAT3XBPFIdEOT9IjO1y+IGJ/8o16fPDbzwHvo0lj9QGdsRgY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DOV+Z1rd; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DOV+Z1rd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id ACF131F00893; Mon, 1 Jun 2026 11:30:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780313430; bh=jQJ/act9W7vDrGgLtIYr+ZfV8kr/t5gDKLTOLvDLfL4=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=DOV+Z1rdoMGaXgBjVmLd0BoV6ZtE+a3pGAoXoMIDB5en0CspvBpbc/Tc8QxwPZtUu 7ECXAM+vrMspIxI7tiRR7ZDh1NlLlk4M8hBAVNzqTd4vvFZV94KCacDik5iArqrPG3 fYaVJNK7yYZHPyo7nXGX55voioIzpinnKdwFdzNdoohN5p3aygb4x58oSeVpQbHjni pPSzzhgZsO6A9On4UTNmC8t4kwQy3DlgPVekmgkpu6yN+yn7BEnBHJzOf78+x9EfvF c7620oVpL1Ywvk8W+3udXGfTzdVDA/m/WfRhZoPJdnHE4XE9aHxl59i7lf9a7Bf/jB xlzKpatnMkQ3A== Message-ID: Date: Mon, 1 Jun 2026 13:30:22 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] dt-bindings: pinctrl: qcom,pmic-gpio: Add level-shifter function To: Fenglin Wu Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , David Collins , Subbaraman Narayanamurthy , Kamal Wadhwa , Maulik Shah , kernel@oss.qualcomm.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org References: <20260528-pinctrl-level-shifter-v2-0-3a6a025392bf@oss.qualcomm.com> <20260528-pinctrl-level-shifter-v2-2-3a6a025392bf@oss.qualcomm.com> <20260530-thankful-maroon-boar-be86f8@quoll> <158920bf-3b52-4772-9305-18afcd5807e3@oss.qualcomm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 01/06/2026 07:00, Fenglin Wu wrote: > > On 5/30/2026 6:29 PM, Krzysztof Kozlowski wrote: >> On Thu, May 28, 2026 at 06:05:36PM -0700, Fenglin Wu wrote: >>> Add the "level-shifter" function and add the required DT properties to >>> allow RPMh firmware to control the level-shifter. Introduce a custom >>> pinconf parameter "qcom,1p2v-1p8v-ls-en" for enabling or disabling the >>> level-shifter function. >> I don't get how PMIC, which is not a child of RPMh at all or not >> talking with RPMh RSC, needs to configure its pin via RPMh. It feels it >> is misrepresented. > > The control for enabling or disabling the bi-directional level shifter > has been centralized in AOP, similar to how regulator resources are > managed. This allows it to be used on a serial bus shared by multiple > clients from different subsystems. Each subsystem can vote for its > enable state through RPMh commands, and AOP determines the final status > to turn the BIDIR_LVL_SHIFTER PMIC modules on or off. Additionally, each > bi-directional level shifter shares its physical pins with a pair of > PMIC GPIO modules and is mutually exclusive with other PMIC GPIO > functions, which means those PMIC GPIO functions must be disabled. So two completely independent hardware devices - PMIC and RPMh - configure the same hardware - level shifter and pin function? > > For these reasons, adding bi-directional level shifter software support > to the pinctrl-spmi-gpio driver is considered the best approach. Let me > know if you have a better suggestion. > >>> Additionally, add the "groups" property with the allowed group names >>> that can be used to control the level-shifter function on pmh0101. >>> >>> Signed-off-by: Fenglin Wu >>> --- >>> .../bindings/pinctrl/qcom,pmic-gpio.yaml | 66 +++++++++++++++++++++- >>> include/dt-bindings/pinctrl/qcom,pmic-gpio.h | 1 + >>> 2 files changed, 64 insertions(+), 3 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml >>> index b8109e6c2a10..19dc61ddff2d 100644 >>> --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml >>> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml >>> @@ -119,6 +119,21 @@ properties: >>> The first cell will be used to define gpio number and the >>> second denotes the flags for this gpio >>> >>> + qcom,rpmh: >>> + description: >>> + Phandle to the RPMh controller device. Required for PMICs when the >>> + bidirectional level shifters is used (e.g., pmh0101), to enable >>> + communication with RPMh firmware for level shifter control. >>> + $ref: /schemas/types.yaml#/definitions/phandle >>> + >>> + qcom,pmic-id: >>> + description: >>> + The ID of the PMIC which supports bidirectional level shifter function. >>> + It is used as the RPMh resource name suffix to request control of the >>> + level shifter to the RPMh firmware. >>> + $ref: /schemas/types.yaml#/definitions/string >>> + pattern: "^[A-N]_E[0-3]+$" >> You do not get instance IDs (it's explcitly documented in docs). > > Okay. This is primarily for creating the resource names used to obtain > the rpmh addresses from the cmd-db for the level-shifter. > > I can change it to a different name if you still agree to add the > support in the pinctrl driver. ID or name, same thing. Still not allowed. > >>> + >>> additionalProperties: false >>> >>> required: >>> @@ -330,6 +345,22 @@ allOf: >>> contains: >>> enum: >>> - qcom,pmh0101-gpio >>> + then: >>> + properties: >>> + gpio-line-names: >>> + minItems: 18 >>> + maxItems: 18 >>> + gpio-reserved-ranges: >>> + minItems: 1 >>> + maxItems: 9 >>> + qcom,rpmh: true >>> + qcom,pmic-id: true >>> + >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + enum: >>> - qcom,pmih0108-gpio >>> then: >>> properties: >>> @@ -523,6 +554,19 @@ $defs: >>> items: >>> pattern: '^gpio([0-9]+)$' >>> >>> + groups: >>> + $ref: /schemas/types.yaml#/definitions/string-array >>> + description: >>> + List of GPIO groups to apply properties to. Only valid for >>> + function "level-shifter" on pmh0101. Valid groups are >>> + gpio11, gpio12; gpio13, gpio14; gpio15, gpio16; gpio17, gpio18. >>> + items: >>> + enum: >>> + - gpio11, gpio12 >>> + - gpio13, gpio14 >>> + - gpio15, gpio16 >>> + - gpio17, gpio18 >>> + >>> function: >>> items: >>> - enum: >>> @@ -536,6 +580,7 @@ $defs: >>> - dtest4 >>> - func3 # supported by LV/MV GPIO subtypes >>> - func4 # supported by LV/MV GPIO subtypes >>> + - level-shifter # supported only by pmh0101 >>> >>> bias-disable: true >>> bias-pull-down: true >>> @@ -592,9 +637,24 @@ $defs: >>> configured as digital input. >>> enum: [1, 2, 3, 4] >>> >>> - required: >>> - - pins >>> - - function >>> + qcom,1p2v-1p8v-ls-en: >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + description: >>> + Enable or disable the bidirectional 1.2V/1.8V level shifter >>> + associated with the specified GPIO group. When set to 1, an RPMh >>> + vote is sent to AOP to enable the level shifter. When set to 0, >>> + the vote is withdrawn. Only valid when function is "level-shifter" >>> + and groups is a level-shifter GPIO pair (e.g., "gpio11, gpio12" >>> + on pmh0101). >> And there are no generic pinconf properties defining the voltage? > > The 1.2V and 1.8V voltages on each side of the bidirectional level > shifter are not configurable. They are fixed in the hardware with > built-in reference voltages at each side of the pins. I am adding this > custom pinconf parameter mainly to control its enabling status. Also, I > am adding "1p2v-1p8v" in the parameter name to provide additional > clarity for users about the "level-shifter" function. So there are or there are not? Best regards, Krzysztof