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Wed, 15 Oct 2025 03:06:20 -0700 (PDT) Message-ID: Subject: Re: [PATCH 2/6] spi: Support multi-bus controllers From: Nuno =?ISO-8859-1?Q?S=E1?= To: David Lechner , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , Nuno =?ISO-8859-1?Q?S=E1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org Date: Wed, 15 Oct 2025 11:06:53 +0100 In-Reply-To: <20251014-spi-add-multi-bus-support-v1-2-2098c12d6f5f@baylibre.com> References: <20251014-spi-add-multi-bus-support-v1-0-2098c12d6f5f@baylibre.com> <20251014-spi-add-multi-bus-support-v1-2-2098c12d6f5f@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2025-10-14 at 17:02 -0500, David Lechner wrote: > Add support for SPI controllers with multiple physical SPI data buses. > (A data bus in this context means lines connected to a serializer, so a > controller with two data buses would have two serializers in a single > controller). >=20 > This is common in the type of controller that can be used with parallel > flash memories, but can be used for general purpose SPI as well. >=20 > To indicate support, a controller just needs to set ctlr->num_data_bus > to something greater than 1. Peripherals indicate which bus they are > connected to via device tree (ACPI support can be added if needed). >=20 > Signed-off-by: David Lechner > --- LGTM, Acked-by: Nuno S=C3=A1 >=20 > This patch has been seen in a different series [1] by Sean before: >=20 > [1]: > https://lore.kernel.org/linux-spi/20250616220054.3968946-4-sean.anderson@= linux.dev/ >=20 > Changes: > * Use u8 array instead of bitfield so that the order of the mapping is > =C2=A0 preserved. (Now looks very much like chip select mapping.) > * Added doc strings for added fields. > * Tweaked the comments. > --- > =C2=A0drivers/spi/spi.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 28 ++++++++= +++++++++++++++++++- > =C2=A0include/linux/spi/spi.h | 17 +++++++++++++++++ > =C2=A02 files changed, 44 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c > index > 2e0647a06890290e1c9dc4a347a0864329795b08..84e5d5057eb41f1a522c4870265d78f= eb411 > 09c8 100644 > --- a/drivers/spi/spi.c > +++ b/drivers/spi/spi.c > @@ -2354,7 +2354,7 @@ static void of_spi_parse_dt_cs_delay(struct device_= node > *nc, > =C2=A0static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_= device > *spi, > =C2=A0 =C2=A0=C2=A0 struct device_node *nc) > =C2=A0{ > - u32 value, cs[SPI_DEVICE_CS_CNT_MAX]; > + u32 value, buses[SPI_DEVICE_DATA_BUS_CNT_MAX], > cs[SPI_DEVICE_CS_CNT_MAX]; > =C2=A0 int rc, idx; > =C2=A0 > =C2=A0 /* Mode (clock phase/polarity/etc.) */ > @@ -2446,6 +2446,31 @@ static int of_spi_parse_dt(struct spi_controller *= ctlr, > struct spi_device *spi, > =C2=A0 for (idx =3D 0; idx < rc; idx++) > =C2=A0 spi_set_chipselect(spi, idx, cs[idx]); > =C2=A0 > + rc =3D of_property_read_variable_u32_array(nc, "spi-buses", buses, 1, > + ARRAY_SIZE(buses)); > + if (rc < 0 && rc !=3D -EINVAL) { > + dev_err(&ctlr->dev, "%pOF has invalid 'spi-buses' property > (%d)\n", > + nc, rc); > + return rc; > + } > + > + if (rc =3D=3D -EINVAL) { > + /* Default when property is omitted. */ > + spi->num_data_bus =3D 1; > + } else { > + for (idx =3D 0; idx < rc; idx++) { > + if (buses[idx] >=3D ctlr->num_data_bus) { > + dev_err(&ctlr->dev, > + "%pOF has out of range 'spi-buses' > property (%d/%d)\n", > + nc, buses[idx], ctlr->num_data_bus); > + return -EINVAL; > + } > + spi->data_bus[idx] =3D buses[idx]; > + } > + > + spi->num_data_bus =3D rc; > + } > + > =C2=A0 /* > =C2=A0 * By default spi->chip_select[0] will hold the physical CS number= , > =C2=A0 * so set bit 0 in spi->cs_index_mask. > @@ -3054,6 +3079,7 @@ struct spi_controller *__spi_alloc_controller(struc= t > device *dev, > =C2=A0 mutex_init(&ctlr->add_lock); > =C2=A0 ctlr->bus_num =3D -1; > =C2=A0 ctlr->num_chipselect =3D 1; > + ctlr->num_data_bus =3D 1; > =C2=A0 ctlr->target =3D target; > =C2=A0 if (IS_ENABLED(CONFIG_SPI_SLAVE) && target) > =C2=A0 ctlr->dev.class =3D &spi_target_class; > diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h > index > cb2c2df3108999a73b67ef4a7b0d2cb07adfc669..c314194d4e7e2b396795ece10e14211= 8ca05 > f4eb 100644 > --- a/include/linux/spi/spi.h > +++ b/include/linux/spi/spi.h > @@ -23,6 +23,9 @@ > =C2=A0/* Max no. of CS supported per spi device */ > =C2=A0#define SPI_DEVICE_CS_CNT_MAX 4 > =C2=A0 > +/* Max no. of data buses supported per spi device */ > +#define SPI_DEVICE_DATA_BUS_CNT_MAX 8 > + > =C2=A0struct dma_chan; > =C2=A0struct software_node; > =C2=A0struct ptp_system_timestamp; > @@ -171,6 +174,9 @@ extern void spi_transfer_cs_change_delay_exec(struct > spi_message *msg, > =C2=A0 * @chip_select: Array of physical chipselect, spi->chipselect[i] g= ives > =C2=A0 * the corresponding physical CS for logical CS i. > =C2=A0 * @num_chipselect: Number of physical chipselects used. > + * @data_bus: Array of physical data buses. This is only used with > specialized > + * controllers that support multiple data buses. > + * @num_data_bus: Number of physical data buses used. > =C2=A0 * @cs_index_mask: Bit mask of the active chipselect(s) in the chip= select > array > =C2=A0 * @cs_gpiod: Array of GPIO descriptors of the corresponding chipse= lect lines > =C2=A0 * (optional, NULL when not using a GPIO line) > @@ -231,6 +237,8 @@ struct spi_device { > =C2=A0 > =C2=A0 u8 chip_select[SPI_DEVICE_CS_CNT_MAX]; > =C2=A0 u8 num_chipselect; > + u8 data_bus[SPI_DEVICE_DATA_BUS_CNT_MAX]; > + u8 num_data_bus; > =C2=A0 > =C2=A0 /* > =C2=A0 * Bit mask of the chipselect(s) that the driver need to use from > @@ -401,6 +409,7 @@ extern struct spi_device *spi_new_ancillary_device(st= ruct > spi_device *spi, u8 ch > =C2=A0 * SPI targets, and are numbered from zero to num_chipselects. > =C2=A0 * each target has a chipselect signal, but it's common that not > =C2=A0 * every chipselect is connected to a target. > + * @num_data_bus: Number of data buses supported by this controller. Def= ault > is 1. > =C2=A0 * @dma_alignment: SPI controller constraint on DMA buffers alignme= nt. > =C2=A0 * @mode_bits: flags understood by this controller driver > =C2=A0 * @buswidth_override_bits: flags to override for this controller d= river > @@ -576,6 +585,14 @@ struct spi_controller { > =C2=A0 */ > =C2=A0 u16 num_chipselect; > =C2=A0 > + /* > + * Some specialized SPI controllers can have more than one physical > + * bus interface per controller (each having it's own serializer). > This > + * specifies the number of buses in that case. Other controllers do > not > + * need to set this (defaults to 1). > + */ > + u16 num_data_bus; > + > =C2=A0 /* Some SPI controllers pose alignment requirements on DMAable > =C2=A0 * buffers; let protocol drivers know about these requirements. > =C2=A0 */