From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A110DC43334 for ; Thu, 9 Jun 2022 09:37:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242161AbiFIJh1 (ORCPT ); Thu, 9 Jun 2022 05:37:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242817AbiFIJhZ (ORCPT ); Thu, 9 Jun 2022 05:37:25 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 890B935A8B; Thu, 9 Jun 2022 02:37:21 -0700 (PDT) X-UUID: 48d6f07150184fc6bbdd8c08f08310b1-20220609 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:0211ed30-9829-4f3f-ab32-7321c82a6d99,OB:10,L OB:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,AC TION:release,TS:45 X-CID-INFO: VERSION:1.1.5,REQID:0211ed30-9829-4f3f-ab32-7321c82a6d99,OB:10,LOB :0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:45 X-CID-META: VersionHash:2a19b09,CLOUDID:52ae3ee5-2ba2-4dc1-b6c5-11feb6c769e0,C OID:fd6f8a451be4,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: 48d6f07150184fc6bbdd8c08f08310b1-20220609 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1918080817; Thu, 09 Jun 2022 17:37:16 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 9 Jun 2022 17:37:11 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 9 Jun 2022 17:37:11 +0800 Message-ID: Subject: Re: [PATCH v10 18/21] drm/mediatek: Add mt8195 Embedded DisplayPort driver From: CK Hu To: Rex-BC Chen , Guillaume Ranquet , Chun-Kuang Hu , "Philipp Zabel" , David Airlie , "Daniel Vetter" , Rob Herring , "Krzysztof Kozlowski" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , "Kishon Vijay Abraham I" , Vinod Koul , "Helge Deller" , Jitao shi CC: Markus Schneider-Pargmann , , , , , , , Date: Thu, 9 Jun 2022 17:37:11 +0800 In-Reply-To: <20220523104758.29531-19-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> <20220523104758.29531-19-granquet@baylibre.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi, Rex: On Mon, 2022-05-23 at 12:47 +0200, Guillaume Ranquet wrote: > From: Markus Schneider-Pargmann > > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC. > > It supports the mt8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jason-JH.Lin . > > Signed-off-by: Markus Schneider-Pargmann > Signed-off-by: Guillaume Ranquet > --- [snip] > + > +static int mtk_dp_power_disable(struct mtk_dp *mtk_dp) > +{ > + int ret; > + > + ret = mtk_dp_write(mtk_dp, MTK_DP_TOP_PWR_STATE, 0); > + > + if (ret) > + return ret; > + > + ret = mtk_dp_write(mtk_dp, MTK_DP_0034, MTK_DP_0034 is defined as: +#define MTK_DP_0034 (BIT(2) | BIT(4) | BIT(5)) I think this a weird address. > + DA_CKM_CKTX0_EN_FORCE_EN | > DA_CKM_BIAS_LPF_EN_FORCE_VAL | > + DA_CKM_BIAS_EN_FORCE_VAL | > + DA_XTP_GLB_LDO_EN_FORCE_VAL | > + DA_XTP_GLB_AVD10_ON_FORCE_VAL); > + > + if (ret) > + return ret; > + > + /* Disable RX */ > + ret = mtk_dp_write(mtk_dp, MTK_DP_1040, 0); MTK_DP_1040 is defined as: +#define MTK_DP_1040 (BIT(6) | BIT(12)) I think this a weird address. Regards, CK > + > + if (ret) > + return ret; > + > + ret = mtk_dp_write(mtk_dp, MTK_DP_TOP_MEM_PD, > + 0x550 | BIT(FUSE_SEL_SHIFT) | > BIT(MEM_ISO_EN_SHIFT)); > + > + return ret; > +}