[PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin

Konrad Dybcio
2024-04-05T08:41:40Z

On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
abstracted through SMEM, instead of being directly available in a fuse.

Add support for SMEM-based speed binning, which includes getting
"feature code" and "product code" from said source and parsing them
to form something that lets us match OPPs against.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 +++---
drivers/gpu/drm/msm/adreno/adreno_device.c | 2 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 39 +++++++++++++++++++++++++++---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 12 ++++++---
4 files changed, 51 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 4cbdfabbcee5..6776fd80f7a6 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2890,13 +2890,15 @@ static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse)
return UINT_MAX;
}

-static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info)
+static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu,
+ struct device *dev,
+ const struct adreno_info *info)
{
u32 supp_hw;
u32 speedbin;
int ret;

- ret = adreno_read_speedbin(dev, &speedbin);
+ ret = adreno_read_speedbin(adreno_gpu, dev, &speedbin);
/*
* -ENOENT means that the platform doesn't support speedbin which is
* fine
@@ -3056,7 +3058,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)

a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx);

- ret = a6xx_set_supported_hw(&pdev->dev, config->info);
+ ret = a6xx_set_supported_hw(adreno_gpu, &pdev->dev, config->info);
if (ret) {
a6xx_destroy(&(a6xx_gpu->base.base));
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index c3703a51287b..901ef767e491 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -6,6 +6,8 @@
* Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
*/

+#include <linux/soc/qcom/socinfo.h>
+
#include "adreno_gpu.h"

bool hang_debug = false;
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 074fb498706f..0e4ff532ac3c 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -21,6 +21,9 @@
#include "msm_gem.h"
#include "msm_mmu.h"

+#include <linux/soc/qcom/smem.h>
+#include <linux/soc/qcom/socinfo.h>
+
static u64 address_space_size = 0;
MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space");
module_param(address_space_size, ullong, 0600);
@@ -1057,9 +1060,37 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
adreno_ocmem->hdl);
}

-int adreno_read_speedbin(struct device *dev, u32 *speedbin)
+int adreno_read_speedbin(struct adreno_gpu *adreno_gpu,
+ struct device *dev, u32 *speedbin)
{
- return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
+ u32 fcode, pcode;
+ int ret;
+
+ /* Try reading the speedbin via a nvmem cell first */
+ ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
+ if (!ret && ret != -EINVAL)
+ return ret;
+
+ ret = qcom_smem_get_feature_code(&fcode);
+ if (ret) {
+ dev_err(dev, "Couldn't get feature code from SMEM!\n");
+ return ret;
+ }
+
+ ret = qcom_smem_get_product_code(&pcode);
+ if (ret) {
+ dev_err(dev, "Couldn't get product code from SMEM!\n");
+ return ret;
+ }
+
+ /* Don't consider fcode for external feature codes */
+ if (fcode <= SOCINFO_FC_EXT_RESERVE)
+ fcode = SOCINFO_FC_UNKNOWN;
+
+ *speedbin = FIELD_PREP(ADRENO_SKU_ID_PCODE, pcode) |
+ FIELD_PREP(ADRENO_SKU_ID_FCODE, fcode);
+
+ return ret;
}

int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
@@ -1098,9 +1129,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
devm_pm_opp_set_clkname(dev, "core");
}

- if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
+ if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin)
speedbin = 0xffff;
- adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
+ adreno_gpu->speedbin = speedbin;

gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
ADRENO_CHIPID_ARGS(config->chip_id));
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 460b399be37b..1770a9e20484 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -81,7 +81,12 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a702_hwcg[], a730_hwcg[], a740_hwcg[];

struct adreno_speedbin {
- uint16_t fuse;
+ /* <= 16-bit for NVMEM fuses, 32b for SOCID values */
+ uint32_t fuse;
+#define ADRENO_SKU_ID_PCODE GENMASK(31, 16)
+#define ADRENO_SKU_ID_FCODE GENMASK(15, 0)
+#define ADRENO_SKU_ID(pcode, fcode) (pcode << 16 | fcode)
+
uint16_t speedbin;
};

@@ -137,7 +142,7 @@ struct adreno_gpu {
struct msm_gpu base;
const struct adreno_info *info;
uint32_t chip_id;
- uint16_t speedbin;
+ uint32_t speedbin;
const struct adreno_gpu_funcs *funcs;

/* interesting register offsets to dump: */
@@ -520,7 +525,8 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
struct adreno_smmu_fault_info *info, const char *block,
u32 scratch[4]);

-int adreno_read_speedbin(struct device *dev, u32 *speedbin);
+int adreno_read_speedbin(struct adreno_gpu *adreno_gpu,
+ struct device *dev, u32 *speedbin);

/*
* For a5xx and a6xx targets load the zap shader that is used to pull the GPU

--
2.40.1