Re: [PATCH 0/6] Add SMEM-based speedbin matching

Dmitry Baryshkov
2024-04-06T03:28:18Z

On Fri, Apr 05, 2024 at 10:41:28AM +0200, Konrad Dybcio wrote:
> Newer (SM8550+) SoCs don't seem to have a nice speedbin fuse anymore,
> but instead rely on a set of combinations of "feature code" (FC) and
> "product code" (PC) identifiers to match the bins. This series adds
> support for that.
>
> I suppose a qcom/for-soc immutable branch would be in order if we want
> to land this in the upcoming cycle.
>
> FWIW I preferred the fuses myself..
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> Konrad Dybcio (5):
> soc: qcom: Move some socinfo defines to the header, expand them
> soc: qcom: smem: Add pcode/fcode getters
> drm/msm/adreno: Implement SMEM-based speed bin
> drm/msm/adreno: Add speedbin data for SM8550 / A740
> arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs
>
> Neil Armstrong (1):
> drm/msm/adreno: Allow specifying default speedbin value

Generic comment: as you are reworking speed bins implementaiton, could
you please take a broader look. A5xx just reads nvmem manually. A6xx
uses adreno_read_speedbin(). And then we call adreno_read_speedbin
second time from from adreno_gpu_init(). Can we get to the point where
the function is called only once for all the platforms which implements
speed binning?

--
With best wishes
Dmitry