devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Krzysztof Kozlowski <krzk@kernel.org>
To: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Jonathan Cameron <jic23@kernel.org>,
	robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	agross@kernel.org, andersson@kernel.org, lumag@kernel.org,
	dmitry.baryshkov@oss.qualcomm.com, konradybcio@kernel.org,
	daniel.lezcano@linaro.org, sboyd@kernel.org, amitk@kernel.org,
	thara.gopinath@gmail.com, lee@kernel.org, rafael@kernel.org,
	subbaraman.narayanamurthy@oss.qualcomm.com,
	david.collins@oss.qualcomm.com,
	anjelique.melendez@oss.qualcomm.com,
	kamal.wadhwa@oss.qualcomm.com, rui.zhang@intel.com,
	lukasz.luba@arm.com, devicetree@vger.kernel.org,
	linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
	cros-qcom-dts-watchers@chromium.org, quic_kotarake@quicinc.com,
	neil.armstrong@linaro.org, stephan.gerhold@linaro.org,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: Re: [PATCH V7 3/5] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC
Date: Fri, 17 Oct 2025 15:40:00 +0200	[thread overview]
Message-ID: <d8a78b7c-e3a9-44b5-986d-8ac32f328eb6@kernel.org> (raw)
In-Reply-To: <68a9b8e8-bdf4-430f-baef-6a293ccea78d@oss.qualcomm.com>

On 17/10/2025 13:18, Jishnu Prakash wrote:
> Hi Krzysztof,
> 
> On 10/9/2025 5:22 AM, Krzysztof Kozlowski wrote:
>> On 08/10/2025 23:20, Jishnu Prakash wrote:
>>> Hi Krzysztof,
>>>
>>> On 10/4/2025 12:22 PM, Krzysztof Kozlowski wrote:
>>>> On Sat, 4 Oct 2025 at 11:42, Jishnu Prakash
>>>> <jishnu.prakash@oss.qualcomm.com> wrote:
>>>>>
>>>>> Hi Jonathan,
>>>>>
>>>>> On 9/27/2025 7:17 PM, Jonathan Cameron wrote:
>>>>>> On Fri, 19 Sep 2025 20:17:43 +0530
>>>>>> Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> wrote:
>>>>>>
>>>>>>> Hi Krzysztof,
>>>>>>>
>>>>>>> On 9/18/2025 5:45 AM, Krzysztof Kozlowski wrote:
>>>>>>>> On 18/09/2025 04:47, Jishnu Prakash wrote:
>>>>>>>>> Hi Krzysztof,
>>>>>>>>>
>>>>>>>>> On 9/17/2025 5:59 AM, Krzysztof Kozlowski wrote:
>>>>>>>>>> On 16/09/2025 16:28, Jishnu Prakash wrote:
>>>>>>>>>>>> You cannot have empty spaces in ID constants. These are abstract
>>>>>>>>>>>> numbers.
>>>>>>>>>>>>
>>>>>>>>>>>> Otherwise please point me to driver using this constant.
>>>>>>>>>>>
>>>>>>>>>>> These constants are for ADC channel numbers, which are fixed in HW.
>>>>>>>>>>>
>>>>>>>>>>> They are used in this driver: drivers/iio/adc/qcom-spmi-adc5-gen3.c,
>>>>>>>>>>> which is added in patch 4 of this series.
>>>>>>>>>>>
>>>>>>>>>>> They can be found in the array named adc5_gen3_chans_pmic[].
>>>>>>>>>>
>>>>>>>>>> Really? So point me to the line there using ADC5_GEN3_VREF_BAT_THERM.
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> We may not be using all of these channels right now - we can add them
>>>>>>>>> later based on requirements coming up. For now, I'll remove the channels
>>>>>>>>> not used in adc5_gen3_chans_pmic[].
>>>>>>>>
>>>>>>>> You are not implementing the feedback then. Please read it carefully.
>>>>>>>>
>>>>>>>
>>>>>>> Sorry, I misunderstood - so you actually meant I should remove the
>>>>>>> empty spaces in the definitions, like this?
>>>>>>>
>>>>>>> -#define ADC5_GEN3_VREF_BAT_THERM               0x15
>>>>>>> +#define ADC5_GEN3_VREF_BAT_THERM 0x15
>>>>>>>
>>>>>>> I thought this at first, but I somehow doubted this later, as I saw some
>>>>>>> other recently added files with empty spaces in #define lines, like:
>>>>>>>
>>>>>>> include/dt-bindings/iio/adc/mediatek,mt6373-auxadc.h
>>>>>>> include/dt-bindings/regulator/st,stm32mp15-regulator.h
>>>>>>>
>>>>>>> I can make this change, if you prefer this. Please let me know
>>>>>>> if I'm still missing something.
>>>>>>>
>>>>>>> Also please let me know if you want me to remove the unused
>>>>>>> channels - I would prefer to keep them if there's no issue,
>>>>>>> as we might need them later.
>>>>>>>
>>>>>> He is referring to 0x14 and below not being defined values.  So what
>>>>>> do they mean if they turn up in the DT?
>>>>>>
>>>>>
>>>>> Thanks for your clarification. To address your first point above, the macros
>>>>> added here only represent the ADC channel numbers which are supported for
>>>>> ADC5 Gen3 devices. If there are numbers missing in between (like 0x14),
>>>>> that is because there exist no valid ADC channels in HW matching those
>>>>> channel numbers.
>>>>>
>>>>> For your question above, if any of the undefined channels are used in the DT,
>>>>> they should ideally be treated as invalid when parsed in the driver probe and
>>>>> lead to an error. When I checked the code again, I saw we do not have such an
>>>>> explicit check right now, so I will add that in the next patch series.
>>>>>
>>>>> And to be clear on which channel numbers are supported, I think it may be
>>>>> best if, for now, we only add support for the channel numbers referenced in
>>>>> the array adc5_gen3_chans_pmic[] in drivers/iio/adc/qcom-spmi-adc5-gen3.c.
>>>>>
>>>>> There are only 18 channel numbers used in this array and I would remove
>>>>> all channels except for these from the binding files. During parsing, we
>>>>> would use this array to confirm if an ADC channel added in DT is supported.
>>>>>
>>>>> In case we need to add support for any more channels later, we could add
>>>>> their macros in the binding file and update the array correspondingly at
>>>>> that time.
>>>>>
>>>>> Does all this sound fine? Please let me know if you have any more concerns
>>>>> or queries.
>>>>
>>>> No, it doesn't.  You keep ignoring my arguments and responding to
>>>> something else. I prefer not to store hardware values as bindings,
>>>> because these are not bindings (and you failed to prove which SW
>>>> interface they bind) and it's really not necessary.
> 
> Sorry about the delay in replying. Let me go step by step
> over the use of the macros and how they are used by clients
> SW.
> 
> 1. In ADC Gen3, this is the superset of channels supported on all
> PMICs (with ADC):
> 
> Ref: include/dt-bindings/iio/adc/qcom,spmi-vadc.h

That's not a driver. Not SW.

> 
> /* ADC channels for PMIC5 Gen3 */
> 
> #define ADC5_GEN3_REF_GND		0x00
> #define ADC5_GEN3_1P25VREF		0x01
> #define ADC5_GEN3_VREF_VADC		0x02
> #define ADC5_GEN3_DIE_TEMP		0x03
> ....
> 
> 
> 2. Since some PMICs may not have all of these channels supported in
> HW, we have the PMIC-specific channel definitions (starting with PMIC
> name like PM8550_..) made referencing the above definitions.
> 
> Ref: include/dt-bindings/iio/adc/qcom,pm8550-adc5-gen3.h:

That's not a driver. Not SW.


> ...
>     #define PM8550_ADC5_GEN3_DIE_TEMP(sid)	((sid) << 8 | ADC5_GEN3_DIE_TEMP)
> ...
> 
> side note: This is also used for the "reg" property in the ADC channel
> definition DT nodes.
> 
> Here `sid` is needed as there can be different instances of same PMIC
> using different `sid`s on a single SoC, and also on different SoCs, the
> same PMIC may have different `sid`s.
> 
> 
> 3. This PMIC-specific definition will be used by clients like below
> (in io-channels) to get the ADC channel they need to read.
> 
>     pmic@1 {
>         temp-alarm@a00 {
>             compatible = "qcom,spmi-temp-alarm";
> 	    ...
>             io-channels = <&pmk8550_adc PM8550_ADC5_GEN3_DIE_TEMP(1)>;
>             io-channel-names = "thermal";
>         };
>     };

That's not a driver. Not SW.

> 
> 
> Can you please provide your suggestions on changes we can make
> in the above points ?

You just pasted DT. I asked about SW, software. Please read carefully
previous comments.


Best regards,
Krzysztof

  reply	other threads:[~2025-10-17 13:40 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-26  8:36 [PATCH V7 0/5] Add support for QCOM SPMI PMIC5 Gen3 ADC Jishnu Prakash
2025-08-26  8:36 ` [PATCH V7 1/5] dt-bindings: iio/adc: Move QCOM ADC bindings to iio/adc folder Jishnu Prakash
2025-08-26  8:36 ` [PATCH V7 2/5] dt-bindings: iio: adc: Split out QCOM VADC channel properties Jishnu Prakash
2025-08-26  8:36 ` [PATCH V7 3/5] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC Jishnu Prakash
2025-08-29  7:19   ` Krzysztof Kozlowski
2025-09-16 14:28     ` Jishnu Prakash
2025-09-17  0:29       ` Krzysztof Kozlowski
2025-09-17 19:47         ` Jishnu Prakash
2025-09-18  0:15           ` Krzysztof Kozlowski
2025-09-19 14:47             ` Jishnu Prakash
2025-09-27 13:47               ` Jonathan Cameron
2025-10-04  2:41                 ` Jishnu Prakash
2025-10-04  6:52                   ` Krzysztof Kozlowski
2025-10-08 14:20                     ` Jishnu Prakash
2025-10-08 23:52                       ` Krzysztof Kozlowski
2025-10-17 11:18                         ` Jishnu Prakash
2025-10-17 13:40                           ` Krzysztof Kozlowski [this message]
2025-10-20 12:51                             ` Konrad Dybcio
2025-10-20 15:55                               ` Krzysztof Kozlowski
2025-10-22 11:02                                 ` Konrad Dybcio
2025-10-27 16:30                                   ` Krzysztof Kozlowski
2025-11-01  2:20                                     ` Jishnu Prakash
2025-08-26  8:36 ` [PATCH V7 4/5] " Jishnu Prakash
2025-08-30 17:42   ` Jonathan Cameron
2025-09-17 19:47     ` Jishnu Prakash
2025-08-26  8:36 ` [PATCH V7 5/5] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring Jishnu Prakash
2025-08-27  1:44   ` Dmitry Baryshkov
2025-08-29  7:14   ` Krzysztof Kozlowski
2025-08-30 17:58   ` Jonathan Cameron
2025-09-17 19:47     ` Jishnu Prakash
2025-08-29  7:11 ` [PATCH V7 0/5] Add support for QCOM SPMI PMIC5 Gen3 ADC Krzysztof Kozlowski
2025-09-16 14:27   ` Jishnu Prakash
2025-08-29  7:12 ` Krzysztof Kozlowski
2025-08-29  8:09   ` Dmitry Baryshkov
2025-08-29  9:11     ` Krzysztof Kozlowski
2025-08-29  9:20       ` Dmitry Baryshkov
2025-08-29 16:31         ` Jonathan Cameron
2025-09-17 19:43           ` Bjorn Andersson
2025-09-19 14:47             ` Jishnu Prakash

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=d8a78b7c-e3a9-44b5-986d-8ac32f328eb6@kernel.org \
    --to=krzk@kernel.org \
    --cc=Jonathan.Cameron@huawei.com \
    --cc=agross@kernel.org \
    --cc=amitk@kernel.org \
    --cc=andersson@kernel.org \
    --cc=anjelique.melendez@oss.qualcomm.com \
    --cc=conor+dt@kernel.org \
    --cc=cros-qcom-dts-watchers@chromium.org \
    --cc=daniel.lezcano@linaro.org \
    --cc=david.collins@oss.qualcomm.com \
    --cc=devicetree@vger.kernel.org \
    --cc=dmitry.baryshkov@oss.qualcomm.com \
    --cc=jic23@kernel.org \
    --cc=jishnu.prakash@oss.qualcomm.com \
    --cc=kamal.wadhwa@oss.qualcomm.com \
    --cc=konradybcio@kernel.org \
    --cc=krzk+dt@kernel.org \
    --cc=krzysztof.kozlowski@linaro.org \
    --cc=lee@kernel.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-iio@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pm@vger.kernel.org \
    --cc=lukasz.luba@arm.com \
    --cc=lumag@kernel.org \
    --cc=neil.armstrong@linaro.org \
    --cc=quic_kotarake@quicinc.com \
    --cc=rafael@kernel.org \
    --cc=robh@kernel.org \
    --cc=rui.zhang@intel.com \
    --cc=sboyd@kernel.org \
    --cc=stephan.gerhold@linaro.org \
    --cc=subbaraman.narayanamurthy@oss.qualcomm.com \
    --cc=thara.gopinath@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).