[PATCH RFC v2 0/6] ASoC: qcom: enable HDMI audio on SM8[456]50 HDK boards

[PATCH RFC v2 0/6] ASoC: qcom: enable HDMI audio on SM8[456]50 HDK boards

[Neil Armstrong]

Now the I2S interface is working on AudioReach platforms,
add the required plumbing and DT nodes to allow playing
audio via the on-board DSI-HDMI bridge.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Changes in v2:
- Fixed MCLK_5 id
- Moved clk set in card code, using calculation from rate
- Removed clock rate from DT
- Renamed dai link
- Fixed DT patchs subject prefix
- Link to v1: https://lore.kernel.org/r/20251006-topic-sm8x50-next-hdk-i2s-v1-0-184b15a87e0a@linaro.org

---
Neil Armstrong (6):
      ASoC: qcom: qdsp6: q6prm: add the missing MCLK clock IDs
      ASoC: dt-bindings: qcom,sm8250: Add clocks properties for I2S
      ASoC: soc: qcom: sc8280xp: add support for I2S clocks
      arm64: dts: qcom: sm8450-hdk: Enable I2S for HDMI
      arm64: dts: qcom: sm8550-hdk: Enable I2S for HDMI
      arm64: dts: qcom: sm8650-hdk: Enable I2S for HDMI

 .../devicetree/bindings/sound/qcom,sm8250.yaml     |  21 ++++
 arch/arm64/boot/dts/qcom/sm8450-hdk.dts            |  26 ++++
 arch/arm64/boot/dts/qcom/sm8450.dtsi               |  40 +++++++
 arch/arm64/boot/dts/qcom/sm8550-hdk.dts            |  26 ++++
 arch/arm64/boot/dts/qcom/sm8550.dtsi               |  73 ++++++++++++
 arch/arm64/boot/dts/qcom/sm8650-hdk.dts            |  25 ++++
 arch/arm64/boot/dts/qcom/sm8650.dtsi               |  40 +++++++
 sound/soc/qcom/qdsp6/q6prm-clocks.c                |   5 +
 sound/soc/qcom/qdsp6/q6prm.h                       |  11 ++
 sound/soc/qcom/sc8280xp.c                          | 132 ++++++++++++++++++++-
 10 files changed, 398 insertions(+), 1 deletion(-)
---
base-commit: 7c3ba4249a3604477ea9c077e10089ba7ddcaa03
change-id: 20251006-topic-sm8x50-next-hdk-i2s-66838fe961db

Best regards,
-- 
Neil Armstrong <neil.armstrong@linaro.org>

[PATCH RFC v2 1/6] ASoC: qcom: qdsp6: q6prm: add the missing MCLK clock IDs

[Neil Armstrong]

Add the missing MCLK ids for the q6prm DSP interface.

Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 sound/soc/qcom/qdsp6/q6prm-clocks.c |  5 +++++
 sound/soc/qcom/qdsp6/q6prm.h        | 11 +++++++++++
 2 files changed, 16 insertions(+)

diff --git a/sound/soc/qcom/qdsp6/q6prm-clocks.c b/sound/soc/qcom/qdsp6/q6prm-clocks.c
index 4c574b48ab0040bc39ae16ec324b41dfc152b408..51b131fa95316cff50342ff60bfc9e3608939d6c 100644
--- a/sound/soc/qcom/qdsp6/q6prm-clocks.c
+++ b/sound/soc/qcom/qdsp6/q6prm-clocks.c
@@ -42,6 +42,11 @@ static const struct q6dsp_clk_init q6prm_clks[] = {
 	Q6PRM_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT),
 	Q6PRM_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT),
 	Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_OSR),
+	Q6PRM_CLK(LPASS_CLK_ID_MCLK_1),
+	Q6PRM_CLK(LPASS_CLK_ID_MCLK_2),
+	Q6PRM_CLK(LPASS_CLK_ID_MCLK_3),
+	Q6PRM_CLK(LPASS_CLK_ID_MCLK_4),
+	Q6PRM_CLK(LPASS_CLK_ID_MCLK_5),
 	Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_MCLK),
 	Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK),
 	Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_MCLK),
diff --git a/sound/soc/qcom/qdsp6/q6prm.h b/sound/soc/qcom/qdsp6/q6prm.h
index a988a32086fe105e32c4fd713b8e0a3d17b83bca..6917e70bcb8a5f3a6bc0ce3ace2fbf42725a3133 100644
--- a/sound/soc/qcom/qdsp6/q6prm.h
+++ b/sound/soc/qcom/qdsp6/q6prm.h
@@ -52,6 +52,17 @@
 /* Clock ID for QUINARY MI2S OSR CLK  */
 #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR                         0x116
 
+/* Clock ID for MCLK1 */
+#define Q6PRM_LPASS_CLK_ID_MCLK_1                                 0x300
+/* Clock ID for MCLK2 */
+#define Q6PRM_LPASS_CLK_ID_MCLK_2                                 0x301
+/* Clock ID for MCLK3 */
+#define Q6PRM_LPASS_CLK_ID_MCLK_3                                 0x302
+/* Clock ID for MCLK4 */
+#define Q6PRM_LPASS_CLK_ID_MCLK_4                                 0x303
+/* Clock ID for MCLK5 */
+#define Q6PRM_LPASS_CLK_ID_MCLK_5                                 0x304
+
 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK			0x305
 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK			0x306
 

-- 
2.34.1

[PATCH RFC v2 2/6] ASoC: dt-bindings: qcom,sm8250: Add clocks properties for I2S

[Neil Armstrong]

In order to describe the block and master clock of each I2S bus, add
the first 5 I2S busses clock entries.

The names (primary, secondary, tertiarty, quaternary, quinary, senary)
uses the LPASS clock naming which were used for a long time on Qualcomm
LPASS firmware interfaces.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 .../devicetree/bindings/sound/qcom,sm8250.yaml      | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
index 8ac91625dce5ccba5c5f31748c36296b12fac1a6..d1420d138b7ed8152aa53769c4d495e1674275e6 100644
--- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
+++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
@@ -64,6 +64,27 @@ properties:
     $ref: /schemas/types.yaml#/definitions/string
     description: User visible long sound card name
 
+  clocks:
+    minItems: 2
+    maxItems: 12
+
+  clock-names:
+    minItems: 2
+    items:
+      # mclk is the I2S Master Clock, mi2s the I2S Bit Clock
+      - const: primary-mi2s
+      - const: primary-mclk
+      - const: secondary-mi2s
+      - const: secondary-mclk
+      - const: tertiary-mi2s
+      - const: tertiary-mclk
+      - const: quaternary-mi2s
+      - const: quaternary-mclk
+      - const: quinary-mi2s
+      - const: quinary-mclk
+      - const: senary-mi2s
+      - const: senary-mclk
+
 patternProperties:
   ".*-dai-link$":
     description:

-- 
2.34.1

Re: [PATCH RFC v2 2/6] ASoC: dt-bindings: qcom,sm8250: Add clocks properties for I2S

[Srinivas Kandagatla]

On 10/8/25 7:56 PM, Neil Armstrong wrote:
> In order to describe the block and master clock of each I2S bus, add
> the first 5 I2S busses clock entries.
> 
> The names (primary, secondary, tertiarty, quaternary, quinary, senary)
> uses the LPASS clock naming which were used for a long time on Qualcomm
> LPASS firmware interfaces.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
>  .../devicetree/bindings/sound/qcom,sm8250.yaml      | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
> index 8ac91625dce5ccba5c5f31748c36296b12fac1a6..d1420d138b7ed8152aa53769c4d495e1674275e6 100644
> --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
> +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
> @@ -64,6 +64,27 @@ properties:
>      $ref: /schemas/types.yaml#/definitions/string
>      description: User visible long sound card name
>  
> +  clocks:
> +    minItems: 2
> +    maxItems: 12
> +
> +  clock-names:
> +    minItems: 2
> +    items:
> +      # mclk is the I2S Master Clock, mi2s the I2S Bit Clock
> +      - const: primary-mi2s
> +      - const: primary-mclk
> +      - const: secondary-mi2s
> +      - const: secondary-mclk
> +      - const: tertiary-mi2s
> +      - const: tertiary-mclk
> +      - const: quaternary-mi2s
> +      - const: quaternary-mclk
> +      - const: quinary-mi2s
> +      - const: quinary-mclk
> +      - const: senary-mi2s
> +      - const: senary-mclk
> +

I don't this is correct way to handling bitclk and mclks for I2S, these
are normally handled as part of snd_soc_dai_set_sysclk() transparently
without need of any device tree description.

Also doing this way is an issue as this is going to break existing Elite
based platforms, and the device description should not change across
these both audio firmwares.

thanks,
Srini

>  patternProperties:
>    ".*-dai-link$":
>      description:
> 

Re: [PATCH RFC v2 2/6] ASoC: dt-bindings: qcom,sm8250: Add clocks properties for I2S

[Neil Armstrong]

On 10/9/25 15:36, Srinivas Kandagatla wrote:
> 
> 
> On 10/8/25 7:56 PM, Neil Armstrong wrote:
>> In order to describe the block and master clock of each I2S bus, add
>> the first 5 I2S busses clock entries.
>>
>> The names (primary, secondary, tertiarty, quaternary, quinary, senary)
>> uses the LPASS clock naming which were used for a long time on Qualcomm
>> LPASS firmware interfaces.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>>   .../devicetree/bindings/sound/qcom,sm8250.yaml      | 21 +++++++++++++++++++++
>>   1 file changed, 21 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>> index 8ac91625dce5ccba5c5f31748c36296b12fac1a6..d1420d138b7ed8152aa53769c4d495e1674275e6 100644
>> --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>> +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>> @@ -64,6 +64,27 @@ properties:
>>       $ref: /schemas/types.yaml#/definitions/string
>>       description: User visible long sound card name
>>   
>> +  clocks:
>> +    minItems: 2
>> +    maxItems: 12
>> +
>> +  clock-names:
>> +    minItems: 2
>> +    items:
>> +      # mclk is the I2S Master Clock, mi2s the I2S Bit Clock
>> +      - const: primary-mi2s
>> +      - const: primary-mclk
>> +      - const: secondary-mi2s
>> +      - const: secondary-mclk
>> +      - const: tertiary-mi2s
>> +      - const: tertiary-mclk
>> +      - const: quaternary-mi2s
>> +      - const: quaternary-mclk
>> +      - const: quinary-mi2s
>> +      - const: quinary-mclk
>> +      - const: senary-mi2s
>> +      - const: senary-mclk
>> +
> 
> I don't this is correct way to handling bitclk and mclks for I2S, these
> are normally handled as part of snd_soc_dai_set_sysclk() transparently
> without need of any device tree description.
> 
> Also doing this way is an issue as this is going to break existing Elite
> based platforms, and the device description should not change across
> these both audio firmwares.

This is only for AudioReach platforms, on those platforms the
clocks are registered in DT and are not accessible by the card.

Device description is obviously different for the AudioReach platforms.

Neil

> 
> thanks,
> Srini
> 
>>   patternProperties:
>>     ".*-dai-link$":
>>       description:
>>
> 

Re: [PATCH RFC v2 2/6] ASoC: dt-bindings: qcom,sm8250: Add clocks properties for I2S

[Srinivas Kandagatla]

On 10/9/25 3:03 PM, Neil Armstrong wrote:
> On 10/9/25 15:36, Srinivas Kandagatla wrote:
>>
>>
>> On 10/8/25 7:56 PM, Neil Armstrong wrote:
>>> In order to describe the block and master clock of each I2S bus, add
>>> the first 5 I2S busses clock entries.
>>>
>>> The names (primary, secondary, tertiarty, quaternary, quinary, senary)
>>> uses the LPASS clock naming which were used for a long time on Qualcomm
>>> LPASS firmware interfaces.
>>>
>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>>> ---
>>>   .../devicetree/bindings/sound/qcom,sm8250.yaml      | 21 ++++++++++
>>> +++++++++++
>>>   1 file changed, 21 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>> b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>> index
>>> 8ac91625dce5ccba5c5f31748c36296b12fac1a6..d1420d138b7ed8152aa53769c4d495e1674275e6 100644
>>> --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>> +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>> @@ -64,6 +64,27 @@ properties:
>>>       $ref: /schemas/types.yaml#/definitions/string
>>>       description: User visible long sound card name
>>>   +  clocks:
>>> +    minItems: 2
>>> +    maxItems: 12
>>> +
>>> +  clock-names:
>>> +    minItems: 2
>>> +    items:
>>> +      # mclk is the I2S Master Clock, mi2s the I2S Bit Clock
>>> +      - const: primary-mi2s
>>> +      - const: primary-mclk
>>> +      - const: secondary-mi2s
>>> +      - const: secondary-mclk
>>> +      - const: tertiary-mi2s
>>> +      - const: tertiary-mclk
>>> +      - const: quaternary-mi2s
>>> +      - const: quaternary-mclk
>>> +      - const: quinary-mi2s
>>> +      - const: quinary-mclk
>>> +      - const: senary-mi2s
>>> +      - const: senary-mclk
>>> +
>>
>> I don't this is correct way to handling bitclk and mclks for I2S, these
>> are normally handled as part of snd_soc_dai_set_sysclk() transparently
>> without need of any device tree description.
>>
>> Also doing this way is an issue as this is going to break existing Elite
>> based platforms, and the device description should not change across
>> these both audio firmwares.
> 
> This is only for AudioReach platforms, on those platforms the
> clocks are registered in DT and are not accessible by the card.
> 
Clocks will be acessable via snd_soc_dai_set_sysclk ->
q6prm_set_lpass_clock once set_sysclk support is added to q6apm-lpass
i2s dai ops.


> Device description is obviously different for the AudioReach platforms.

Why should it be different, its same device.
We have platforms that use both Elite and Audioreach.

--srini
> 
> Neil
> 
>>
>> thanks,
>> Srini
>>
>>>   patternProperties:
>>>     ".*-dai-link$":
>>>       description:
>>>
>>
> 

Re: [PATCH RFC v2 2/6] ASoC: dt-bindings: qcom,sm8250: Add clocks properties for I2S

[Neil Armstrong]

On 10/9/25 16:06, Srinivas Kandagatla wrote:
> 
> 
> On 10/9/25 3:03 PM, Neil Armstrong wrote:
>> On 10/9/25 15:36, Srinivas Kandagatla wrote:
>>>
>>>
>>> On 10/8/25 7:56 PM, Neil Armstrong wrote:
>>>> In order to describe the block and master clock of each I2S bus, add
>>>> the first 5 I2S busses clock entries.
>>>>
>>>> The names (primary, secondary, tertiarty, quaternary, quinary, senary)
>>>> uses the LPASS clock naming which were used for a long time on Qualcomm
>>>> LPASS firmware interfaces.
>>>>
>>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>>>> ---
>>>>    .../devicetree/bindings/sound/qcom,sm8250.yaml      | 21 ++++++++++
>>>> +++++++++++
>>>>    1 file changed, 21 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>> b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>> index
>>>> 8ac91625dce5ccba5c5f31748c36296b12fac1a6..d1420d138b7ed8152aa53769c4d495e1674275e6 100644
>>>> --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>> +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>> @@ -64,6 +64,27 @@ properties:
>>>>        $ref: /schemas/types.yaml#/definitions/string
>>>>        description: User visible long sound card name
>>>>    +  clocks:
>>>> +    minItems: 2
>>>> +    maxItems: 12
>>>> +
>>>> +  clock-names:
>>>> +    minItems: 2
>>>> +    items:
>>>> +      # mclk is the I2S Master Clock, mi2s the I2S Bit Clock
>>>> +      - const: primary-mi2s
>>>> +      - const: primary-mclk
>>>> +      - const: secondary-mi2s
>>>> +      - const: secondary-mclk
>>>> +      - const: tertiary-mi2s
>>>> +      - const: tertiary-mclk
>>>> +      - const: quaternary-mi2s
>>>> +      - const: quaternary-mclk
>>>> +      - const: quinary-mi2s
>>>> +      - const: quinary-mclk
>>>> +      - const: senary-mi2s
>>>> +      - const: senary-mclk
>>>> +
>>>
>>> I don't this is correct way to handling bitclk and mclks for I2S, these
>>> are normally handled as part of snd_soc_dai_set_sysclk() transparently
>>> without need of any device tree description.
>>>
>>> Also doing this way is an issue as this is going to break existing Elite
>>> based platforms, and the device description should not change across
>>> these both audio firmwares.
>>
>> This is only for AudioReach platforms, on those platforms the
>> clocks are registered in DT and are not accessible by the card.
>>
> Clocks will be acessable via snd_soc_dai_set_sysclk ->
> q6prm_set_lpass_clock once set_sysclk support is added to q6apm-lpass
> i2s dai ops.
> 
> 
>> Device description is obviously different for the AudioReach platforms.
> 
> Why should it be different, its same device.
> We have platforms that use both Elite and Audioreach.

I'm perfectly aware of that, it's the case for sc7280/qcm6490. And I agree
the card bindings is the same, but it doesn't mean the DSP elements are the
same and uses in the same manner.

So let's forget the bindings and forget those clocks entries, and imagine
I'll implement those _sys_sysclk calls like for the Elite platforms.
This means I'll bypass the clock framework by directly setting the PRM
clocks, this is clearly a layer violation.

Neil

> 
> --srini
>>
>> Neil
>>
>>>
>>> thanks,
>>> Srini
>>>
>>>>    patternProperties:
>>>>      ".*-dai-link$":
>>>>        description:
>>>>
>>>
>>
> 

Re: [PATCH RFC v2 2/6] ASoC: dt-bindings: qcom,sm8250: Add clocks properties for I2S

[Srinivas Kandagatla]

On 10/9/25 3:25 PM, Neil Armstrong wrote:
> On 10/9/25 16:06, Srinivas Kandagatla wrote:
>>
>>
>> On 10/9/25 3:03 PM, Neil Armstrong wrote:
>>> On 10/9/25 15:36, Srinivas Kandagatla wrote:
>>>>
>>>>
>>>> On 10/8/25 7:56 PM, Neil Armstrong wrote:
>>>>> In order to describe the block and master clock of each I2S bus, add
>>>>> the first 5 I2S busses clock entries.
>>>>>
>>>>> The names (primary, secondary, tertiarty, quaternary, quinary, senary)
>>>>> uses the LPASS clock naming which were used for a long time on
>>>>> Qualcomm
>>>>> LPASS firmware interfaces.
>>>>>
>>>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>>>>> ---
>>>>>    .../devicetree/bindings/sound/qcom,sm8250.yaml      | 21 ++++++++++
>>>>> +++++++++++
>>>>>    1 file changed, 21 insertions(+)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>>> b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>>> index
>>>>> 8ac91625dce5ccba5c5f31748c36296b12fac1a6..d1420d138b7ed8152aa53769c4d495e1674275e6 100644
>>>>> --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>>> +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>>> @@ -64,6 +64,27 @@ properties:
>>>>>        $ref: /schemas/types.yaml#/definitions/string
>>>>>        description: User visible long sound card name
>>>>>    +  clocks:
>>>>> +    minItems: 2
>>>>> +    maxItems: 12
>>>>> +
>>>>> +  clock-names:
>>>>> +    minItems: 2
>>>>> +    items:
>>>>> +      # mclk is the I2S Master Clock, mi2s the I2S Bit Clock
>>>>> +      - const: primary-mi2s
>>>>> +      - const: primary-mclk
>>>>> +      - const: secondary-mi2s
>>>>> +      - const: secondary-mclk
>>>>> +      - const: tertiary-mi2s
>>>>> +      - const: tertiary-mclk
>>>>> +      - const: quaternary-mi2s
>>>>> +      - const: quaternary-mclk
>>>>> +      - const: quinary-mi2s
>>>>> +      - const: quinary-mclk
>>>>> +      - const: senary-mi2s
>>>>> +      - const: senary-mclk
>>>>> +
>>>>
>>>> I don't this is correct way to handling bitclk and mclks for I2S, these
>>>> are normally handled as part of snd_soc_dai_set_sysclk() transparently
>>>> without need of any device tree description.
>>>>
>>>> Also doing this way is an issue as this is going to break existing
>>>> Elite
>>>> based platforms, and the device description should not change across
>>>> these both audio firmwares.
>>>
>>> This is only for AudioReach platforms, on those platforms the
>>> clocks are registered in DT and are not accessible by the card.
>>>
>> Clocks will be acessable via snd_soc_dai_set_sysclk ->
>> q6prm_set_lpass_clock once set_sysclk support is added to q6apm-lpass
>> i2s dai ops.
>>
>>
>>> Device description is obviously different for the AudioReach platforms.
>>
>> Why should it be different, its same device.
>> We have platforms that use both Elite and Audioreach.
> 
> I'm perfectly aware of that, it's the case for sc7280/qcm6490. And I agree
> the card bindings is the same, but it doesn't mean the DSP elements are the
> same and uses in the same manner.
> 
> So let's forget the bindings and forget those clocks entries, and imagine
> I'll implement those _sys_sysclk calls like for the Elite platforms.
> This means I'll bypass the clock framework by directly setting the PRM
> clocks, this is clearly a layer violation.

You can claim clocks in the dsp layer (q6apm-lpass-dais) instead of
claiming it in machine layer, it does not necessarily have to bypass the
clk framework.

--srini
> 
> Neil
> 
>>
>> --srini
>>>
>>> Neil
>>>
>>>>
>>>> thanks,
>>>> Srini
>>>>
>>>>>    patternProperties:
>>>>>      ".*-dai-link$":
>>>>>        description:
>>>>>
>>>>
>>>
>>
> 

Re: [PATCH RFC v2 2/6] ASoC: dt-bindings: qcom,sm8250: Add clocks properties for I2S

[Neil Armstrong]

On 10/9/25 16:29, Srinivas Kandagatla wrote:
> 
> 
> On 10/9/25 3:25 PM, Neil Armstrong wrote:
>> On 10/9/25 16:06, Srinivas Kandagatla wrote:
>>>
>>>
>>> On 10/9/25 3:03 PM, Neil Armstrong wrote:
>>>> On 10/9/25 15:36, Srinivas Kandagatla wrote:
>>>>>
>>>>>
>>>>> On 10/8/25 7:56 PM, Neil Armstrong wrote:
>>>>>> In order to describe the block and master clock of each I2S bus, add
>>>>>> the first 5 I2S busses clock entries.
>>>>>>
>>>>>> The names (primary, secondary, tertiarty, quaternary, quinary, senary)
>>>>>> uses the LPASS clock naming which were used for a long time on
>>>>>> Qualcomm
>>>>>> LPASS firmware interfaces.
>>>>>>
>>>>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>>>>>> ---
>>>>>>     .../devicetree/bindings/sound/qcom,sm8250.yaml      | 21 ++++++++++
>>>>>> +++++++++++
>>>>>>     1 file changed, 21 insertions(+)
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>>>> b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>>>> index
>>>>>> 8ac91625dce5ccba5c5f31748c36296b12fac1a6..d1420d138b7ed8152aa53769c4d495e1674275e6 100644
>>>>>> --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>>>> +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>>>> @@ -64,6 +64,27 @@ properties:
>>>>>>         $ref: /schemas/types.yaml#/definitions/string
>>>>>>         description: User visible long sound card name
>>>>>>     +  clocks:
>>>>>> +    minItems: 2
>>>>>> +    maxItems: 12
>>>>>> +
>>>>>> +  clock-names:
>>>>>> +    minItems: 2
>>>>>> +    items:
>>>>>> +      # mclk is the I2S Master Clock, mi2s the I2S Bit Clock
>>>>>> +      - const: primary-mi2s
>>>>>> +      - const: primary-mclk
>>>>>> +      - const: secondary-mi2s
>>>>>> +      - const: secondary-mclk
>>>>>> +      - const: tertiary-mi2s
>>>>>> +      - const: tertiary-mclk
>>>>>> +      - const: quaternary-mi2s
>>>>>> +      - const: quaternary-mclk
>>>>>> +      - const: quinary-mi2s
>>>>>> +      - const: quinary-mclk
>>>>>> +      - const: senary-mi2s
>>>>>> +      - const: senary-mclk
>>>>>> +
>>>>>
>>>>> I don't this is correct way to handling bitclk and mclks for I2S, these
>>>>> are normally handled as part of snd_soc_dai_set_sysclk() transparently
>>>>> without need of any device tree description.
>>>>>
>>>>> Also doing this way is an issue as this is going to break existing
>>>>> Elite
>>>>> based platforms, and the device description should not change across
>>>>> these both audio firmwares.
>>>>
>>>> This is only for AudioReach platforms, on those platforms the
>>>> clocks are registered in DT and are not accessible by the card.
>>>>
>>> Clocks will be acessable via snd_soc_dai_set_sysclk ->
>>> q6prm_set_lpass_clock once set_sysclk support is added to q6apm-lpass
>>> i2s dai ops.
>>>
>>>
>>>> Device description is obviously different for the AudioReach platforms.
>>>
>>> Why should it be different, its same device.
>>> We have platforms that use both Elite and Audioreach.
>>
>> I'm perfectly aware of that, it's the case for sc7280/qcm6490. And I agree
>> the card bindings is the same, but it doesn't mean the DSP elements are the
>> same and uses in the same manner.
>>
>> So let's forget the bindings and forget those clocks entries, and imagine
>> I'll implement those _sys_sysclk calls like for the Elite platforms.
>> This means I'll bypass the clock framework by directly setting the PRM
>> clocks, this is clearly a layer violation.
> 
> You can claim clocks in the dsp layer (q6apm-lpass-dais) instead of
> claiming it in machine layer, it does not necessarily have to bypass the
> clk framework.

The current q6afe implementation totally bypasses the clock framework:

static int q6afe_set_lpass_clock_v2(struct q6afe_port *port,
				 struct afe_clk_set *cfg)
{
	return q6afe_port_set_param(port, cfg, AFE_PARAM_ID_CLOCK_SET,
				    AFE_MODULE_CLOCK_SET, sizeof(*cfg));
}

I have no time right now to implement all that for q6apm & q6prm in the
way you propose, so I'll probably not send a new version.

Neil

> 
> --srini
>>
>> Neil
>>
>>>
>>> --srini
>>>>
>>>> Neil
>>>>
>>>>>
>>>>> thanks,
>>>>> Srini
>>>>>
>>>>>>     patternProperties:
>>>>>>       ".*-dai-link$":
>>>>>>         description:
>>>>>>
>>>>>
>>>>
>>>
>>
> 

Re: [PATCH RFC v2 2/6] ASoC: dt-bindings: qcom,sm8250: Add clocks properties for I2S

[Srinivas Kandagatla]

On 10/9/25 4:30 PM, Neil Armstrong wrote:
> On 10/9/25 16:29, Srinivas Kandagatla wrote:
>>
>>
>> On 10/9/25 3:25 PM, Neil Armstrong wrote:
>>> On 10/9/25 16:06, Srinivas Kandagatla wrote:
>>>>
>>>>
>>>> On 10/9/25 3:03 PM, Neil Armstrong wrote:
>>>>> On 10/9/25 15:36, Srinivas Kandagatla wrote:
>>>>>>
>>>>>>
>>>>>> On 10/8/25 7:56 PM, Neil Armstrong wrote:
>>>>>>> In order to describe the block and master clock of each I2S bus, add
>>>>>>> the first 5 I2S busses clock entries.
>>>>>>>
>>>>>>> The names (primary, secondary, tertiarty, quaternary, quinary,
>>>>>>> senary)
>>>>>>> uses the LPASS clock naming which were used for a long time on
>>>>>>> Qualcomm
>>>>>>> LPASS firmware interfaces.
>>>>>>>
>>>>>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>>>>>>> ---
>>>>>>>     .../devicetree/bindings/sound/qcom,sm8250.yaml      | 21 ++++
>>>>>>> ++++++
>>>>>>> +++++++++++
>>>>>>>     1 file changed, 21 insertions(+)
>>>>>>>
>>>>>>> diff --git a/Documentation/devicetree/bindings/sound/
>>>>>>> qcom,sm8250.yaml
>>>>>>> b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>>>>> index
>>>>>>> 8ac91625dce5ccba5c5f31748c36296b12fac1a6..d1420d138b7ed8152aa53769c4d495e1674275e6 100644
>>>>>>> --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>>>>> +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>>>>> @@ -64,6 +64,27 @@ properties:
>>>>>>>         $ref: /schemas/types.yaml#/definitions/string
>>>>>>>         description: User visible long sound card name
>>>>>>>     +  clocks:
>>>>>>> +    minItems: 2
>>>>>>> +    maxItems: 12
>>>>>>> +
>>>>>>> +  clock-names:
>>>>>>> +    minItems: 2
>>>>>>> +    items:
>>>>>>> +      # mclk is the I2S Master Clock, mi2s the I2S Bit Clock
>>>>>>> +      - const: primary-mi2s
>>>>>>> +      - const: primary-mclk
>>>>>>> +      - const: secondary-mi2s
>>>>>>> +      - const: secondary-mclk
>>>>>>> +      - const: tertiary-mi2s
>>>>>>> +      - const: tertiary-mclk
>>>>>>> +      - const: quaternary-mi2s
>>>>>>> +      - const: quaternary-mclk
>>>>>>> +      - const: quinary-mi2s
>>>>>>> +      - const: quinary-mclk
>>>>>>> +      - const: senary-mi2s
>>>>>>> +      - const: senary-mclk
>>>>>>> +
>>>>>>
>>>>>> I don't this is correct way to handling bitclk and mclks for I2S,
>>>>>> these
>>>>>> are normally handled as part of snd_soc_dai_set_sysclk()
>>>>>> transparently
>>>>>> without need of any device tree description.
>>>>>>
>>>>>> Also doing this way is an issue as this is going to break existing
>>>>>> Elite
>>>>>> based platforms, and the device description should not change across
>>>>>> these both audio firmwares.
>>>>>
>>>>> This is only for AudioReach platforms, on those platforms the
>>>>> clocks are registered in DT and are not accessible by the card.
>>>>>
>>>> Clocks will be acessable via snd_soc_dai_set_sysclk ->
>>>> q6prm_set_lpass_clock once set_sysclk support is added to q6apm-lpass
>>>> i2s dai ops.
>>>>
>>>>
>>>>> Device description is obviously different for the AudioReach
>>>>> platforms.
>>>>
>>>> Why should it be different, its same device.
>>>> We have platforms that use both Elite and Audioreach.
>>>
>>> I'm perfectly aware of that, it's the case for sc7280/qcm6490. And I
>>> agree
>>> the card bindings is the same, but it doesn't mean the DSP elements
>>> are the
>>> same and uses in the same manner.
>>>
>>> So let's forget the bindings and forget those clocks entries, and
>>> imagine
>>> I'll implement those _sys_sysclk calls like for the Elite platforms.
>>> This means I'll bypass the clock framework by directly setting the PRM
>>> clocks, this is clearly a layer violation.
>>
>> You can claim clocks in the dsp layer (q6apm-lpass-dais) instead of
>> claiming it in machine layer, it does not necessarily have to bypass the
>> clk framework.
> 
> The current q6afe implementation totally bypasses the clock framework:
> 
> static int q6afe_set_lpass_clock_v2(struct q6afe_port *port,
>                  struct afe_clk_set *cfg)
> {
>     return q6afe_port_set_param(port, cfg, AFE_PARAM_ID_CLOCK_SET,
>                     AFE_MODULE_CLOCK_SET, sizeof(*cfg));
> }
> 
> I have no time right now to implement all that for q6apm & q6prm in the
> way you propose, so I'll probably not send a new version.

This is not really scalable, you are suggesting that we add this for
every board, when you can do it more generically in the dsp code using
set_sysclk callback.



--srini
> 
> Neil
> 
>>
>> --srini
>>>
>>> Neil
>>>
>>>>
>>>> --srini
>>>>>
>>>>> Neil
>>>>>
>>>>>>
>>>>>> thanks,
>>>>>> Srini
>>>>>>
>>>>>>>     patternProperties:
>>>>>>>       ".*-dai-link$":
>>>>>>>         description:
>>>>>>>
>>>>>>
>>>>>
>>>>
>>>
>>
> 

Re: [PATCH RFC v2 2/6] ASoC: dt-bindings: qcom,sm8250: Add clocks properties for I2S

[Srinivas Kandagatla]

On 10/9/25 4:30 PM, Neil Armstrong wrote:
> On 10/9/25 16:29, Srinivas Kandagatla wrote:
>>
>>
>> On 10/9/25 3:25 PM, Neil Armstrong wrote:
>>> On 10/9/25 16:06, Srinivas Kandagatla wrote:
>>>>
>>>>
>>>> On 10/9/25 3:03 PM, Neil Armstrong wrote:
>>>>> On 10/9/25 15:36, Srinivas Kandagatla wrote:
>>>>>>
>>>>>>
>>>>>> On 10/8/25 7:56 PM, Neil Armstrong wrote:
>>>>>>> In order to describe the block and master clock of each I2S bus, add
>>>>>>> the first 5 I2S busses clock entries.
>>>>>>>
>>>>>>> The names (primary, secondary, tertiarty, quaternary, quinary,
>>>>>>> senary)
>>>>>>> uses the LPASS clock naming which were used for a long time on
>>>>>>> Qualcomm
>>>>>>> LPASS firmware interfaces.
>>>>>>>
>>>>>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>>>>>>> ---
>>>>>>>     .../devicetree/bindings/sound/qcom,sm8250.yaml      | 21 ++++
>>>>>>> ++++++
>>>>>>> +++++++++++
>>>>>>>     1 file changed, 21 insertions(+)
>>>>>>>
>>>>>>> diff --git a/Documentation/devicetree/bindings/sound/
>>>>>>> qcom,sm8250.yaml
>>>>>>> b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>>>>> index
>>>>>>> 8ac91625dce5ccba5c5f31748c36296b12fac1a6..d1420d138b7ed8152aa53769c4d495e1674275e6 100644
>>>>>>> --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>>>>> +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
>>>>>>> @@ -64,6 +64,27 @@ properties:
>>>>>>>         $ref: /schemas/types.yaml#/definitions/string
>>>>>>>         description: User visible long sound card name
>>>>>>>     +  clocks:
>>>>>>> +    minItems: 2
>>>>>>> +    maxItems: 12
>>>>>>> +
>>>>>>> +  clock-names:
>>>>>>> +    minItems: 2
>>>>>>> +    items:
>>>>>>> +      # mclk is the I2S Master Clock, mi2s the I2S Bit Clock
>>>>>>> +      - const: primary-mi2s
>>>>>>> +      - const: primary-mclk
>>>>>>> +      - const: secondary-mi2s
>>>>>>> +      - const: secondary-mclk
>>>>>>> +      - const: tertiary-mi2s
>>>>>>> +      - const: tertiary-mclk
>>>>>>> +      - const: quaternary-mi2s
>>>>>>> +      - const: quaternary-mclk
>>>>>>> +      - const: quinary-mi2s
>>>>>>> +      - const: quinary-mclk
>>>>>>> +      - const: senary-mi2s
>>>>>>> +      - const: senary-mclk
>>>>>>> +
>>>>>>
>>>>>> I don't this is correct way to handling bitclk and mclks for I2S,
>>>>>> these
>>>>>> are normally handled as part of snd_soc_dai_set_sysclk()
>>>>>> transparently
>>>>>> without need of any device tree description.
>>>>>>
>>>>>> Also doing this way is an issue as this is going to break existing
>>>>>> Elite
>>>>>> based platforms, and the device description should not change across
>>>>>> these both audio firmwares.
>>>>>
>>>>> This is only for AudioReach platforms, on those platforms the
>>>>> clocks are registered in DT and are not accessible by the card.
>>>>>
>>>> Clocks will be acessable via snd_soc_dai_set_sysclk ->
>>>> q6prm_set_lpass_clock once set_sysclk support is added to q6apm-lpass
>>>> i2s dai ops.
>>>>
>>>>
>>>>> Device description is obviously different for the AudioReach
>>>>> platforms.
>>>>
>>>> Why should it be different, its same device.
>>>> We have platforms that use both Elite and Audioreach.
>>>
>>> I'm perfectly aware of that, it's the case for sc7280/qcm6490. And I
>>> agree
>>> the card bindings is the same, but it doesn't mean the DSP elements
>>> are the

> }
> 
> I have no time right now to implement all that for q6apm & q6prm in the
> way you propose, so I'll probably not send a new version.

Or Update the codec driver to handle the mclk, instead of putting this
in machine driver.
BIT clks are normally automatically setup by DSP based on interface
index, type and pcm params.

--srini

> 
> Neil
> 
>>
>> --srini
>>>
>>> Neil
>>>
>>>>
>>>> --srini
>>>>>
>>>>> Neil
>>>>>
>>>>>>
>>>>>> thanks,
>>>>>> Srini
>>>>>>
>>>>>>>     patternProperties:
>>>>>>>       ".*-dai-link$":
>>>>>>>         description:
>>>>>>>
>>>>>>
>>>>>
>>>>
>>>
>>
> 

[PATCH RFC v2 3/6] ASoC: soc: qcom: sc8280xp: add support for I2S clocks

[Neil Armstrong]

Add support for getting the I2S clocks used for the MI2S
interfaces, and enable/disable the clocks on the PCM
startup and shutdown card callbacks.

The rate can be easily calculated since the card forces 48Hz,
2 channels at 16bit slot size.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 sound/soc/qcom/sc8280xp.c | 132 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 131 insertions(+), 1 deletion(-)

diff --git a/sound/soc/qcom/sc8280xp.c b/sound/soc/qcom/sc8280xp.c
index 78e327bc2f07767b1032f09af7f45b947e7eb67a..82b173c2dabbd1478df49ba9f0cc53e82bf2f8d2 100644
--- a/sound/soc/qcom/sc8280xp.c
+++ b/sound/soc/qcom/sc8280xp.c
@@ -4,6 +4,8 @@
 #include <dt-bindings/sound/qcom,q6afe.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of_clk.h>
 #include <sound/soc.h>
 #include <sound/soc-dapm.h>
 #include <sound/pcm.h>
@@ -15,15 +17,47 @@
 #include "common.h"
 #include "sdw.h"
 
+#define I2S_MAX_CLKS	5
+
+#define I2S_MCLKFS	256
+#define I2S_SLOTSIZE	16
+#define I2S_MCLK_RATE(rate, channels) \
+		((rate) * (channels) * I2S_MCLKFS)
+#define I2S_BIT_RATE(rate, channels) \
+		((rate) * (channels) * I2S_SLOTSIZE)
+
+#define I2S_DEFAULT_RATE	48000
+#define I2S_DEFAULT_CHANNELS	2
+
 struct sc8280xp_snd_data {
 	bool stream_prepared[AFE_PORT_MAX];
 	struct snd_soc_card *card;
 	struct sdw_stream_runtime *sruntime[AFE_PORT_MAX];
 	struct snd_soc_jack jack;
 	struct snd_soc_jack dp_jack[8];
+	struct clk *i2s_clk[I2S_MAX_CLKS];
+	struct clk *i2s_mclk[I2S_MAX_CLKS];
 	bool jack_setup;
 };
 
+static int sc8280xp_snd_i2s_index(struct snd_soc_dai *dai)
+{
+	switch (dai->id) {
+	case PRIMARY_MI2S_RX...PRIMARY_MI2S_TX:
+		return 0;
+	case  SECONDARY_MI2S_RX...SECONDARY_MI2S_TX:
+		return 1;
+	case TERTIARY_MI2S_RX...TERTIARY_MI2S_TX:
+		return 2;
+	case QUATERNARY_MI2S_RX...QUATERNARY_MI2S_TX:
+		return 3;
+	case QUINARY_MI2S_RX...QUINARY_MI2S_TX:
+		return 4;
+	default:
+		return -1;
+	}
+}
+
 static int sc8280xp_snd_init(struct snd_soc_pcm_runtime *rtd)
 {
 	struct sc8280xp_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
@@ -31,10 +65,22 @@ static int sc8280xp_snd_init(struct snd_soc_pcm_runtime *rtd)
 	struct snd_soc_card *card = rtd->card;
 	struct snd_soc_jack *dp_jack  = NULL;
 	int dp_pcm_id = 0;
+	int index, ret;
 
 	switch (cpu_dai->id) {
 	case PRIMARY_MI2S_RX...QUATERNARY_MI2S_TX:
 	case QUINARY_MI2S_RX...QUINARY_MI2S_TX:
+		index = sc8280xp_snd_i2s_index(cpu_dai);
+		ret = clk_set_rate(data->i2s_mclk[index],
+				   I2S_MCLK_RATE(I2S_DEFAULT_RATE,
+						 I2S_DEFAULT_CHANNELS));
+		if (ret)
+			dev_err(data->card->dev, "Unable to set mclk rate\n");
+		ret = clk_set_rate(data->i2s_clk[index],
+				   I2S_BIT_RATE(I2S_DEFAULT_RATE,
+						I2S_DEFAULT_CHANNELS));
+		if (ret)
+			dev_err(data->card->dev, "Unable to set bit rate\n");
 		snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_BP_FP);
 		break;
 	case WSA_CODEC_DMA_RX_0:
@@ -68,12 +114,54 @@ static int sc8280xp_snd_init(struct snd_soc_pcm_runtime *rtd)
 	return qcom_snd_wcd_jack_setup(rtd, &data->jack, &data->jack_setup);
 }
 
+static int sc8280xp_snd_startup(struct snd_pcm_substream *substream)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct sc8280xp_snd_data *pdata = snd_soc_card_get_drvdata(rtd->card);
+	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+	struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
+	unsigned int codec_dai_fmt = SND_SOC_DAIFMT_BC_FC |
+				     SND_SOC_DAIFMT_NB_NF |
+				     SND_SOC_DAIFMT_I2S;
+	int index, ret;
+
+	switch (cpu_dai->id) {
+	case PRIMARY_MI2S_RX...QUATERNARY_MI2S_TX:
+	case QUINARY_MI2S_RX...QUINARY_MI2S_TX:
+		index = sc8280xp_snd_i2s_index(cpu_dai);
+		ret = clk_prepare_enable(pdata->i2s_mclk[index]);
+		if (ret)
+			dev_err(pdata->card->dev, "Unable to enable bit clock\n");
+		ret = clk_prepare_enable(pdata->i2s_clk[index]);
+		if (ret)
+			dev_err(pdata->card->dev, "Unable to enable master clock\n");
+		snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
+		break;
+	default:
+		break;
+	}
+
+	return qcom_snd_sdw_startup(substream);
+}
+
 static void sc8280xp_snd_shutdown(struct snd_pcm_substream *substream)
 {
 	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
 	struct sc8280xp_snd_data *pdata = snd_soc_card_get_drvdata(rtd->card);
 	struct sdw_stream_runtime *sruntime = pdata->sruntime[cpu_dai->id];
+	int index;
+
+	switch (cpu_dai->id) {
+	case PRIMARY_MI2S_RX...TERTIARY_MI2S_RX:
+	case QUINARY_MI2S_RX...QUINARY_MI2S_TX:
+		index = sc8280xp_snd_i2s_index(cpu_dai);
+		clk_disable_unprepare(pdata->i2s_clk[index]);
+		clk_disable_unprepare(pdata->i2s_mclk[index]);
+		break;
+	default:
+		break;
+	}
 
 	pdata->sruntime[cpu_dai->id] = NULL;
 	sdw_release_stream(sruntime);
@@ -141,7 +229,7 @@ static int sc8280xp_snd_hw_free(struct snd_pcm_substream *substream)
 }
 
 static const struct snd_soc_ops sc8280xp_be_ops = {
-	.startup = qcom_snd_sdw_startup,
+	.startup = sc8280xp_snd_startup,
 	.shutdown = sc8280xp_snd_shutdown,
 	.hw_params = sc8280xp_snd_hw_params,
 	.hw_free = sc8280xp_snd_hw_free,
@@ -162,6 +250,44 @@ static void sc8280xp_add_be_ops(struct snd_soc_card *card)
 	}
 }
 
+static const char * const i2s_bus_names[I2S_MAX_CLKS] = {
+	"primary",
+	"secondary",
+	"tertiary",
+	"quaternary",
+	"quinary",
+};
+
+static int sc8280xp_get_i2s_clocks(struct platform_device *pdev,
+				   struct sc8280xp_snd_data *data)
+{
+	struct device *dev = &pdev->dev;
+	int i;
+
+	if (!device_property_present(dev, "clocks"))
+		return 0;
+
+	for (i = 0; i < I2S_MAX_CLKS; ++i) {
+		char name[32];
+
+		snprintf(name, 32, "%s-mi2s", i2s_bus_names[i]);
+		data->i2s_clk[i] = devm_clk_get_optional(dev, name);
+		if (IS_ERR(data->i2s_clk[i]))
+			return dev_err_probe(dev, PTR_ERR(data->i2s_clk[i]),
+					     "unable to get %s clock\n",
+					     name);
+
+		snprintf(name, 32, "%s-mclk", i2s_bus_names[i]);
+		data->i2s_mclk[i] = devm_clk_get_optional(dev, name);
+		if (IS_ERR(data->i2s_mclk[i]))
+			return dev_err_probe(dev, PTR_ERR(data->i2s_mclk[i]),
+					     "unable to get %s clock\n",
+					     name);
+	}
+
+	return 0;
+}
+
 static int sc8280xp_platform_probe(struct platform_device *pdev)
 {
 	struct snd_soc_card *card;
@@ -185,6 +311,10 @@ static int sc8280xp_platform_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
+	ret = sc8280xp_get_i2s_clocks(pdev, data);
+	if (ret)
+		return ret;
+
 	card->driver_name = of_device_get_match_data(dev);
 	sc8280xp_add_be_ops(card);
 	return devm_snd_soc_register_card(dev, card);

-- 
2.34.1

Re: [PATCH RFC v2 3/6] ASoC: soc: qcom: sc8280xp: add support for I2S clocks

[Konrad Dybcio]

On 10/8/25 8:56 PM, Neil Armstrong wrote:
> Add support for getting the I2S clocks used for the MI2S
> interfaces, and enable/disable the clocks on the PCM
> startup and shutdown card callbacks.
> 
> The rate can be easily calculated since the card forces 48Hz,
> 2 channels at 16bit slot size.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---

[...]

> +static int sc8280xp_snd_i2s_index(struct snd_soc_dai *dai)
> +{
> +	switch (dai->id) {
> +	case PRIMARY_MI2S_RX...PRIMARY_MI2S_TX:

I have mixed feelings about the range syntax here.. it's only 2 entries
per and it's quite error-prone (no errors in this case, but it
encourages the thinking that things are always contiguous)..

[...]

>  	switch (cpu_dai->id) {
>  	case PRIMARY_MI2S_RX...QUATERNARY_MI2S_TX:
>  	case QUINARY_MI2S_RX...QUINARY_MI2S_TX:

whereas e.g. here we see that it's not really the case, but it's
tempting for someone trying to 'clean up' the code to change it to:

case PRIMARY_MI2S_RX...QUINARY_MI2S_TX 

and the reviewers may not catch it

Konrad

Re: [PATCH RFC v2 3/6] ASoC: soc: qcom: sc8280xp: add support for I2S clocks

[Neil Armstrong]

On 10/9/25 11:41, Konrad Dybcio wrote:
> On 10/8/25 8:56 PM, Neil Armstrong wrote:
>> Add support for getting the I2S clocks used for the MI2S
>> interfaces, and enable/disable the clocks on the PCM
>> startup and shutdown card callbacks.
>>
>> The rate can be easily calculated since the card forces 48Hz,
>> 2 channels at 16bit slot size.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
> 
> [...]
> 
>> +static int sc8280xp_snd_i2s_index(struct snd_soc_dai *dai)
>> +{
>> +	switch (dai->id) {
>> +	case PRIMARY_MI2S_RX...PRIMARY_MI2S_TX:
> 
> I have mixed feelings about the range syntax here.. it's only 2 entries
> per and it's quite error-prone (no errors in this case, but it
> encourages the thinking that things are always contiguous)..
> 
> [...]
> 
>>   	switch (cpu_dai->id) {
>>   	case PRIMARY_MI2S_RX...QUATERNARY_MI2S_TX:
>>   	case QUINARY_MI2S_RX...QUINARY_MI2S_TX:
> 
> whereas e.g. here we see that it's not really the case, but it's
> tempting for someone trying to 'clean up' the code to change it to:
> 
> case PRIMARY_MI2S_RX...QUINARY_MI2S_TX
> 
> and the reviewers may not catch it

I understand your point, but I just took what was already in the file...

Is my change correct, yes, is the style of the code improvable, yes.

I'll do my best to fix the style issue later on.

Neil

> 
> Konrad

Re: [PATCH RFC v2 3/6] ASoC: soc: qcom: sc8280xp: add support for I2S clocks

[Konrad Dybcio]

On 10/9/25 11:45 AM, Neil Armstrong wrote:
> On 10/9/25 11:41, Konrad Dybcio wrote:
>> On 10/8/25 8:56 PM, Neil Armstrong wrote:
>>> Add support for getting the I2S clocks used for the MI2S
>>> interfaces, and enable/disable the clocks on the PCM
>>> startup and shutdown card callbacks.
>>>
>>> The rate can be easily calculated since the card forces 48Hz,
>>> 2 channels at 16bit slot size.
>>>
>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>>> ---
>>
>> [...]
>>
>>> +static int sc8280xp_snd_i2s_index(struct snd_soc_dai *dai)
>>> +{
>>> +    switch (dai->id) {
>>> +    case PRIMARY_MI2S_RX...PRIMARY_MI2S_TX:
>>
>> I have mixed feelings about the range syntax here.. it's only 2 entries
>> per and it's quite error-prone (no errors in this case, but it
>> encourages the thinking that things are always contiguous)..
>>
>> [...]
>>
>>>       switch (cpu_dai->id) {
>>>       case PRIMARY_MI2S_RX...QUATERNARY_MI2S_TX:
>>>       case QUINARY_MI2S_RX...QUINARY_MI2S_TX:
>>
>> whereas e.g. here we see that it's not really the case, but it's
>> tempting for someone trying to 'clean up' the code to change it to:
>>
>> case PRIMARY_MI2S_RX...QUINARY_MI2S_TX
>>
>> and the reviewers may not catch it
> 
> I understand your point, but I just took what was already in the file...
> 
> Is my change correct, yes, is the style of the code improvable, yes.
> 
> I'll do my best to fix the style issue later on.

That works, thanks

Konrad

Re: [PATCH RFC v2 3/6] ASoC: soc: qcom: sc8280xp: add support for I2S clocks

[Alexey Klimov]

On Wed Oct 8, 2025 at 7:56 PM BST, Neil Armstrong wrote:
> Add support for getting the I2S clocks used for the MI2S
> interfaces, and enable/disable the clocks on the PCM
> startup and shutdown card callbacks.
>
> The rate can be easily calculated since the card forces 48Hz,
> 2 channels at 16bit slot size.

48 kHz?

48 Hz rate will result in too narrow analog range to reconstruct anything
apart from beeps probably.

Best regards,
Alexey

Re: [PATCH RFC v2 3/6] ASoC: soc: qcom: sc8280xp: add support for I2S clocks

[Neil Armstrong]

On 10/9/25 13:21, Alexey Klimov wrote:
> On Wed Oct 8, 2025 at 7:56 PM BST, Neil Armstrong wrote:
>> Add support for getting the I2S clocks used for the MI2S
>> interfaces, and enable/disable the clocks on the PCM
>> startup and shutdown card callbacks.
>>
>> The rate can be easily calculated since the card forces 48Hz,
>> 2 channels at 16bit slot size.
> 
> 48 kHz?

Yeah obviously, I'll fix the commit log.

Neil

> 
> 48 Hz rate will result in too narrow analog range to reconstruct anything
> apart from beeps probably.
> 
> Best regards,
> Alexey

Re: [PATCH RFC v2 3/6] ASoC: soc: qcom: sc8280xp: add support for I2S clocks

[Srinivas Kandagatla]

On 10/8/25 7:56 PM, Neil Armstrong wrote:
> Add support for getting the I2S clocks used for the MI2S
> interfaces, and enable/disable the clocks on the PCM
> startup and shutdown card callbacks.
> 
> The rate can be easily calculated since the card forces 48Hz,
> 2 channels at 16bit slot size.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
>  sound/soc/qcom/sc8280xp.c | 132 +++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 131 insertions(+), 1 deletion(-)
> 
> diff --git a/sound/soc/qcom/sc8280xp.c b/sound/soc/qcom/sc8280xp.c
> index 78e327bc2f07767b1032f09af7f45b947e7eb67a..82b173c2dabbd1478df49ba9f0cc53e82bf2f8d2 100644
> --- a/sound/soc/qcom/sc8280xp.c
> +++ b/sound/soc/qcom/sc8280xp.c
> @@ -4,6 +4,8 @@
>  #include <dt-bindings/sound/qcom,q6afe.h>
>  #include <linux/module.h>
>  #include <linux/platform_device.h>
> +#include <linux/clk.h>
> +#include <linux/of_clk.h>
>  #include <sound/soc.h>
>  #include <sound/soc-dapm.h>
>  #include <sound/pcm.h>
> @@ -15,15 +17,47 @@
>  #include "common.h"
>  #include "sdw.h"
>  
> +#define I2S_MAX_CLKS	5
> +
> +#define I2S_MCLKFS	256
> +#define I2S_SLOTSIZE	16
> +#define I2S_MCLK_RATE(rate, channels) \
> +		((rate) * (channels) * I2S_MCLKFS)
> +#define I2S_BIT_RATE(rate, channels) \
> +		((rate) * (channels) * I2S_SLOTSIZE)
> +
> +#define I2S_DEFAULT_RATE	48000
> +#define I2S_DEFAULT_CHANNELS	2
> +

Sorry for not providing this feedback on v1, we should use
snd_soc_dai_set_sysclk to do this whole clk handling.

and implment this set_sysclk in q6i2s_ops of q6apm-lpass-dais.c  like
q6afe-lpass-dais.c


--srini

>  struct sc8280xp_snd_data {
>  	bool stream_prepared[AFE_PORT_MAX];
>  	struct snd_soc_card *card;
>  	struct sdw_stream_runtime *sruntime[AFE_PORT_MAX];
>  	struct snd_soc_jack jack;
>  	struct snd_soc_jack dp_jack[8];
> +	struct clk *i2s_clk[I2S_MAX_CLKS];
> +	struct clk *i2s_mclk[I2S_MAX_CLKS];
>  	bool jack_setup;
>  };
>  
> +static int sc8280xp_snd_i2s_index(struct snd_soc_dai *dai)
> +{
> +	switch (dai->id) {
> +	case PRIMARY_MI2S_RX...PRIMARY_MI2S_TX:
> +		return 0;
> +	case  SECONDARY_MI2S_RX...SECONDARY_MI2S_TX:
> +		return 1;
> +	case TERTIARY_MI2S_RX...TERTIARY_MI2S_TX:
> +		return 2;
> +	case QUATERNARY_MI2S_RX...QUATERNARY_MI2S_TX:
> +		return 3;
> +	case QUINARY_MI2S_RX...QUINARY_MI2S_TX:
> +		return 4;
> +	default:
> +		return -1;
> +	}
> +}
> +
>  static int sc8280xp_snd_init(struct snd_soc_pcm_runtime *rtd)
>  {
>  	struct sc8280xp_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
> @@ -31,10 +65,22 @@ static int sc8280xp_snd_init(struct snd_soc_pcm_runtime *rtd)
>  	struct snd_soc_card *card = rtd->card;
>  	struct snd_soc_jack *dp_jack  = NULL;
>  	int dp_pcm_id = 0;
> +	int index, ret;
>  
>  	switch (cpu_dai->id) {
>  	case PRIMARY_MI2S_RX...QUATERNARY_MI2S_TX:
>  	case QUINARY_MI2S_RX...QUINARY_MI2S_TX:
> +		index = sc8280xp_snd_i2s_index(cpu_dai);
> +		ret = clk_set_rate(data->i2s_mclk[index],
> +				   I2S_MCLK_RATE(I2S_DEFAULT_RATE,
> +						 I2S_DEFAULT_CHANNELS));
> +		if (ret)
> +			dev_err(data->card->dev, "Unable to set mclk rate\n");
> +		ret = clk_set_rate(data->i2s_clk[index],
> +				   I2S_BIT_RATE(I2S_DEFAULT_RATE,
> +						I2S_DEFAULT_CHANNELS));
> +		if (ret)
> +			dev_err(data->card->dev, "Unable to set bit rate\n");
>  		snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_BP_FP);
>  		break;
>  	case WSA_CODEC_DMA_RX_0:
> @@ -68,12 +114,54 @@ static int sc8280xp_snd_init(struct snd_soc_pcm_runtime *rtd)
>  	return qcom_snd_wcd_jack_setup(rtd, &data->jack, &data->jack_setup);
>  }
>  
> +static int sc8280xp_snd_startup(struct snd_pcm_substream *substream)
> +{
> +	struct snd_soc_pcm_runtime *rtd = substream->private_data;
> +	struct sc8280xp_snd_data *pdata = snd_soc_card_get_drvdata(rtd->card);
> +	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
> +	struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
> +	unsigned int codec_dai_fmt = SND_SOC_DAIFMT_BC_FC |
> +				     SND_SOC_DAIFMT_NB_NF |
> +				     SND_SOC_DAIFMT_I2S;
> +	int index, ret;
> +
> +	switch (cpu_dai->id) {
> +	case PRIMARY_MI2S_RX...QUATERNARY_MI2S_TX:
> +	case QUINARY_MI2S_RX...QUINARY_MI2S_TX:
> +		index = sc8280xp_snd_i2s_index(cpu_dai);
> +		ret = clk_prepare_enable(pdata->i2s_mclk[index]);
> +		if (ret)
> +			dev_err(pdata->card->dev, "Unable to enable bit clock\n");
> +		ret = clk_prepare_enable(pdata->i2s_clk[index]);
> +		if (ret)
> +			dev_err(pdata->card->dev, "Unable to enable master clock\n");
> +		snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	return qcom_snd_sdw_startup(substream);
> +}
> +
>  static void sc8280xp_snd_shutdown(struct snd_pcm_substream *substream)
>  {
>  	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
>  	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
>  	struct sc8280xp_snd_data *pdata = snd_soc_card_get_drvdata(rtd->card);
>  	struct sdw_stream_runtime *sruntime = pdata->sruntime[cpu_dai->id];
> +	int index;
> +
> +	switch (cpu_dai->id) {
> +	case PRIMARY_MI2S_RX...TERTIARY_MI2S_RX:
> +	case QUINARY_MI2S_RX...QUINARY_MI2S_TX:
> +		index = sc8280xp_snd_i2s_index(cpu_dai);
> +		clk_disable_unprepare(pdata->i2s_clk[index]);
> +		clk_disable_unprepare(pdata->i2s_mclk[index]);
> +		break;
> +	default:
> +		break;
> +	}
>  
>  	pdata->sruntime[cpu_dai->id] = NULL;
>  	sdw_release_stream(sruntime);
> @@ -141,7 +229,7 @@ static int sc8280xp_snd_hw_free(struct snd_pcm_substream *substream)
>  }
>  
>  static const struct snd_soc_ops sc8280xp_be_ops = {
> -	.startup = qcom_snd_sdw_startup,
> +	.startup = sc8280xp_snd_startup,
>  	.shutdown = sc8280xp_snd_shutdown,
>  	.hw_params = sc8280xp_snd_hw_params,
>  	.hw_free = sc8280xp_snd_hw_free,
> @@ -162,6 +250,44 @@ static void sc8280xp_add_be_ops(struct snd_soc_card *card)
>  	}
>  }
>  
> +static const char * const i2s_bus_names[I2S_MAX_CLKS] = {
> +	"primary",
> +	"secondary",
> +	"tertiary",
> +	"quaternary",
> +	"quinary",
> +};
> +
> +static int sc8280xp_get_i2s_clocks(struct platform_device *pdev,
> +				   struct sc8280xp_snd_data *data)
> +{
> +	struct device *dev = &pdev->dev;
> +	int i;
> +
> +	if (!device_property_present(dev, "clocks"))
> +		return 0;
> +
> +	for (i = 0; i < I2S_MAX_CLKS; ++i) {
> +		char name[32];
> +
> +		snprintf(name, 32, "%s-mi2s", i2s_bus_names[i]);
> +		data->i2s_clk[i] = devm_clk_get_optional(dev, name);
> +		if (IS_ERR(data->i2s_clk[i]))
> +			return dev_err_probe(dev, PTR_ERR(data->i2s_clk[i]),
> +					     "unable to get %s clock\n",
> +					     name);
> +
> +		snprintf(name, 32, "%s-mclk", i2s_bus_names[i]);
> +		data->i2s_mclk[i] = devm_clk_get_optional(dev, name);
> +		if (IS_ERR(data->i2s_mclk[i]))
> +			return dev_err_probe(dev, PTR_ERR(data->i2s_mclk[i]),
> +					     "unable to get %s clock\n",
> +					     name);
> +	}
> +
> +	return 0;
> +}
> +
>  static int sc8280xp_platform_probe(struct platform_device *pdev)
>  {
>  	struct snd_soc_card *card;
> @@ -185,6 +311,10 @@ static int sc8280xp_platform_probe(struct platform_device *pdev)
>  	if (ret)
>  		return ret;
>  
> +	ret = sc8280xp_get_i2s_clocks(pdev, data);
> +	if (ret)
> +		return ret;
> +
>  	card->driver_name = of_device_get_match_data(dev);
>  	sc8280xp_add_be_ops(card);
>  	return devm_snd_soc_register_card(dev, card);
> 

Re: [PATCH RFC v2 3/6] ASoC: soc: qcom: sc8280xp: add support for I2S clocks

[Neil Armstrong]

On 10/9/25 15:40, Srinivas Kandagatla wrote:
> 
> 
> On 10/8/25 7:56 PM, Neil Armstrong wrote:
>> Add support for getting the I2S clocks used for the MI2S
>> interfaces, and enable/disable the clocks on the PCM
>> startup and shutdown card callbacks.
>>
>> The rate can be easily calculated since the card forces 48Hz,
>> 2 channels at 16bit slot size.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>>   sound/soc/qcom/sc8280xp.c | 132 +++++++++++++++++++++++++++++++++++++++++++++-
>>   1 file changed, 131 insertions(+), 1 deletion(-)
>>
>> diff --git a/sound/soc/qcom/sc8280xp.c b/sound/soc/qcom/sc8280xp.c
>> index 78e327bc2f07767b1032f09af7f45b947e7eb67a..82b173c2dabbd1478df49ba9f0cc53e82bf2f8d2 100644
>> --- a/sound/soc/qcom/sc8280xp.c
>> +++ b/sound/soc/qcom/sc8280xp.c
>> @@ -4,6 +4,8 @@
>>   #include <dt-bindings/sound/qcom,q6afe.h>
>>   #include <linux/module.h>
>>   #include <linux/platform_device.h>
>> +#include <linux/clk.h>
>> +#include <linux/of_clk.h>
>>   #include <sound/soc.h>
>>   #include <sound/soc-dapm.h>
>>   #include <sound/pcm.h>
>> @@ -15,15 +17,47 @@
>>   #include "common.h"
>>   #include "sdw.h"
>>   
>> +#define I2S_MAX_CLKS	5
>> +
>> +#define I2S_MCLKFS	256
>> +#define I2S_SLOTSIZE	16
>> +#define I2S_MCLK_RATE(rate, channels) \
>> +		((rate) * (channels) * I2S_MCLKFS)
>> +#define I2S_BIT_RATE(rate, channels) \
>> +		((rate) * (channels) * I2S_SLOTSIZE)
>> +
>> +#define I2S_DEFAULT_RATE	48000
>> +#define I2S_DEFAULT_CHANNELS	2
>> +
> 
> Sorry for not providing this feedback on v1, we should use
> snd_soc_dai_set_sysclk to do this whole clk handling.
> 
> and implment this set_sysclk in q6i2s_ops of q6apm-lpass-dais.c  like
> q6afe-lpass-dais.c

Why ? This makes no sense, why exposing all the clocks in DT ?

This works, so why going back to the hardcoded Elite path ?

Neil

> 
> 
> --srini
> 
>>   struct sc8280xp_snd_data {
>>   	bool stream_prepared[AFE_PORT_MAX];
>>   	struct snd_soc_card *card;
>>   	struct sdw_stream_runtime *sruntime[AFE_PORT_MAX];
>>   	struct snd_soc_jack jack;
>>   	struct snd_soc_jack dp_jack[8];
>> +	struct clk *i2s_clk[I2S_MAX_CLKS];
>> +	struct clk *i2s_mclk[I2S_MAX_CLKS];
>>   	bool jack_setup;
>>   };
>>   
>> +static int sc8280xp_snd_i2s_index(struct snd_soc_dai *dai)
>> +{
>> +	switch (dai->id) {
>> +	case PRIMARY_MI2S_RX...PRIMARY_MI2S_TX:
>> +		return 0;
>> +	case  SECONDARY_MI2S_RX...SECONDARY_MI2S_TX:
>> +		return 1;
>> +	case TERTIARY_MI2S_RX...TERTIARY_MI2S_TX:
>> +		return 2;
>> +	case QUATERNARY_MI2S_RX...QUATERNARY_MI2S_TX:
>> +		return 3;
>> +	case QUINARY_MI2S_RX...QUINARY_MI2S_TX:
>> +		return 4;
>> +	default:
>> +		return -1;
>> +	}
>> +}
>> +
>>   static int sc8280xp_snd_init(struct snd_soc_pcm_runtime *rtd)
>>   {
>>   	struct sc8280xp_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
>> @@ -31,10 +65,22 @@ static int sc8280xp_snd_init(struct snd_soc_pcm_runtime *rtd)
>>   	struct snd_soc_card *card = rtd->card;
>>   	struct snd_soc_jack *dp_jack  = NULL;
>>   	int dp_pcm_id = 0;
>> +	int index, ret;
>>   
>>   	switch (cpu_dai->id) {
>>   	case PRIMARY_MI2S_RX...QUATERNARY_MI2S_TX:
>>   	case QUINARY_MI2S_RX...QUINARY_MI2S_TX:
>> +		index = sc8280xp_snd_i2s_index(cpu_dai);
>> +		ret = clk_set_rate(data->i2s_mclk[index],
>> +				   I2S_MCLK_RATE(I2S_DEFAULT_RATE,
>> +						 I2S_DEFAULT_CHANNELS));
>> +		if (ret)
>> +			dev_err(data->card->dev, "Unable to set mclk rate\n");
>> +		ret = clk_set_rate(data->i2s_clk[index],
>> +				   I2S_BIT_RATE(I2S_DEFAULT_RATE,
>> +						I2S_DEFAULT_CHANNELS));
>> +		if (ret)
>> +			dev_err(data->card->dev, "Unable to set bit rate\n");
>>   		snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_BP_FP);
>>   		break;
>>   	case WSA_CODEC_DMA_RX_0:
>> @@ -68,12 +114,54 @@ static int sc8280xp_snd_init(struct snd_soc_pcm_runtime *rtd)
>>   	return qcom_snd_wcd_jack_setup(rtd, &data->jack, &data->jack_setup);
>>   }
>>   
>> +static int sc8280xp_snd_startup(struct snd_pcm_substream *substream)
>> +{
>> +	struct snd_soc_pcm_runtime *rtd = substream->private_data;
>> +	struct sc8280xp_snd_data *pdata = snd_soc_card_get_drvdata(rtd->card);
>> +	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
>> +	struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
>> +	unsigned int codec_dai_fmt = SND_SOC_DAIFMT_BC_FC |
>> +				     SND_SOC_DAIFMT_NB_NF |
>> +				     SND_SOC_DAIFMT_I2S;
>> +	int index, ret;
>> +
>> +	switch (cpu_dai->id) {
>> +	case PRIMARY_MI2S_RX...QUATERNARY_MI2S_TX:
>> +	case QUINARY_MI2S_RX...QUINARY_MI2S_TX:
>> +		index = sc8280xp_snd_i2s_index(cpu_dai);
>> +		ret = clk_prepare_enable(pdata->i2s_mclk[index]);
>> +		if (ret)
>> +			dev_err(pdata->card->dev, "Unable to enable bit clock\n");
>> +		ret = clk_prepare_enable(pdata->i2s_clk[index]);
>> +		if (ret)
>> +			dev_err(pdata->card->dev, "Unable to enable master clock\n");
>> +		snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
>> +		break;
>> +	default:
>> +		break;
>> +	}
>> +
>> +	return qcom_snd_sdw_startup(substream);
>> +}
>> +
>>   static void sc8280xp_snd_shutdown(struct snd_pcm_substream *substream)
>>   {
>>   	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
>>   	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
>>   	struct sc8280xp_snd_data *pdata = snd_soc_card_get_drvdata(rtd->card);
>>   	struct sdw_stream_runtime *sruntime = pdata->sruntime[cpu_dai->id];
>> +	int index;
>> +
>> +	switch (cpu_dai->id) {
>> +	case PRIMARY_MI2S_RX...TERTIARY_MI2S_RX:
>> +	case QUINARY_MI2S_RX...QUINARY_MI2S_TX:
>> +		index = sc8280xp_snd_i2s_index(cpu_dai);
>> +		clk_disable_unprepare(pdata->i2s_clk[index]);
>> +		clk_disable_unprepare(pdata->i2s_mclk[index]);
>> +		break;
>> +	default:
>> +		break;
>> +	}
>>   
>>   	pdata->sruntime[cpu_dai->id] = NULL;
>>   	sdw_release_stream(sruntime);
>> @@ -141,7 +229,7 @@ static int sc8280xp_snd_hw_free(struct snd_pcm_substream *substream)
>>   }
>>   
>>   static const struct snd_soc_ops sc8280xp_be_ops = {
>> -	.startup = qcom_snd_sdw_startup,
>> +	.startup = sc8280xp_snd_startup,
>>   	.shutdown = sc8280xp_snd_shutdown,
>>   	.hw_params = sc8280xp_snd_hw_params,
>>   	.hw_free = sc8280xp_snd_hw_free,
>> @@ -162,6 +250,44 @@ static void sc8280xp_add_be_ops(struct snd_soc_card *card)
>>   	}
>>   }
>>   
>> +static const char * const i2s_bus_names[I2S_MAX_CLKS] = {
>> +	"primary",
>> +	"secondary",
>> +	"tertiary",
>> +	"quaternary",
>> +	"quinary",
>> +};
>> +
>> +static int sc8280xp_get_i2s_clocks(struct platform_device *pdev,
>> +				   struct sc8280xp_snd_data *data)
>> +{
>> +	struct device *dev = &pdev->dev;
>> +	int i;
>> +
>> +	if (!device_property_present(dev, "clocks"))
>> +		return 0;
>> +
>> +	for (i = 0; i < I2S_MAX_CLKS; ++i) {
>> +		char name[32];
>> +
>> +		snprintf(name, 32, "%s-mi2s", i2s_bus_names[i]);
>> +		data->i2s_clk[i] = devm_clk_get_optional(dev, name);
>> +		if (IS_ERR(data->i2s_clk[i]))
>> +			return dev_err_probe(dev, PTR_ERR(data->i2s_clk[i]),
>> +					     "unable to get %s clock\n",
>> +					     name);
>> +
>> +		snprintf(name, 32, "%s-mclk", i2s_bus_names[i]);
>> +		data->i2s_mclk[i] = devm_clk_get_optional(dev, name);
>> +		if (IS_ERR(data->i2s_mclk[i]))
>> +			return dev_err_probe(dev, PTR_ERR(data->i2s_mclk[i]),
>> +					     "unable to get %s clock\n",
>> +					     name);
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>>   static int sc8280xp_platform_probe(struct platform_device *pdev)
>>   {
>>   	struct snd_soc_card *card;
>> @@ -185,6 +311,10 @@ static int sc8280xp_platform_probe(struct platform_device *pdev)
>>   	if (ret)
>>   		return ret;
>>   
>> +	ret = sc8280xp_get_i2s_clocks(pdev, data);
>> +	if (ret)
>> +		return ret;
>> +
>>   	card->driver_name = of_device_get_match_data(dev);
>>   	sc8280xp_add_be_ops(card);
>>   	return devm_snd_soc_register_card(dev, card);
>>
> 

[PATCH RFC v2 4/6] arm64: dts: qcom: sm8450-hdk: Enable I2S for HDMI

[Neil Armstrong]

Add the necessary nodes to configure the right I2S interface
to output audio via the DSI HDMI bridge.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 26 +++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sm8450.dtsi    | 40 +++++++++++++++++++++++++++++++++
 2 files changed, 66 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
index 0c6aa7ddf43263f30595b3f0733ec3e126e38608..7b822086a57c600ae9b5668d6d7a375d0ec55fa7 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
@@ -667,6 +667,8 @@ lt9611_codec: hdmi-bridge@2b {
 		pinctrl-names = "default";
 		pinctrl-0 = <&lt9611_irq_pin &lt9611_rst_pin>;
 
+		#sound-dai-cells = <1>;
+
 		ports {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1016,6 +1018,14 @@ &sound {
 			"TX SWR_INPUT0", "ADC3_OUTPUT",
 			"TX SWR_INPUT1", "ADC4_OUTPUT";
 
+	pinctrl-0 = <&i2s0_default_state>, <&audio_mclk0_default_state>;
+	pinctrl-names = "default";
+
+	clocks = <&q6prmcc LPASS_CLK_ID_PRI_MI2S_IBIT LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+		 <&q6prmcc LPASS_CLK_ID_MCLK_1 LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+	clock-names = "primart-mi2s",
+		      "primary-mclk";
+
 	wcd-playback-dai-link {
 		link-name = "WCD Playback";
 
@@ -1079,6 +1089,22 @@ platform {
 			sound-dai = <&q6apm>;
 		};
 	};
+
+	prim-mi2s-dai-link {
+		link-name = "HDMI Playback";
+
+		cpu {
+			sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>;
+		};
+
+		codec {
+			sound-dai = <&lt9611_codec 0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+	};
 };
 
 &swr0 {
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 23420e6924728cb80fc9e44fb4d7e01fbffae21f..5ddc1169e8c23327261820f7baa31983a3eb0bf8 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -4288,6 +4288,46 @@ qup_uart20_default: qup-uart20-default-state {
 				pins = "gpio76", "gpio77", "gpio78", "gpio79";
 				function = "qup20";
 			};
+
+			audio_mclk0_default_state: audio-mclk0-default-state {
+				pins = "gpio125";
+				function = "pri_mi2s";
+				drive-strength = <8>;
+				bias-disable;
+				output-high;
+			};
+
+			i2s0_default_state: i2s0-default-state {
+				sck-pins {
+					pins = "gpio126";
+					function = "mi2s0_sck";
+					drive-strength = <8>;
+					bias-disable;
+					output-high;
+				};
+
+				data0-pins {
+					pins = "gpio127";
+					function = "mi2s0_data0";
+					drive-strength = <8>;
+					bias-disable;
+				};
+
+				data1-pins {
+					pins = "gpio128";
+					function = "mi2s0_data1";
+					drive-strength = <8>;
+					bias-disable;
+				};
+
+				ws-pins {
+					pins = "gpio129";
+					function = "mi2s0_ws";
+					drive-strength = <8>;
+					bias-disable;
+					output-high;
+				};
+			};
 		};
 
 		lpass_tlmm: pinctrl@3440000 {

-- 
2.34.1

Re: [PATCH RFC v2 4/6] arm64: dts: qcom: sm8450-hdk: Enable I2S for HDMI

[Konrad Dybcio]

On 10/8/25 8:56 PM, Neil Armstrong wrote:
> Add the necessary nodes to configure the right I2S interface
> to output audio via the DSI HDMI bridge.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 26 +++++++++++++++++++++
>  arch/arm64/boot/dts/qcom/sm8450.dtsi    | 40 +++++++++++++++++++++++++++++++++
>  2 files changed, 66 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
> index 0c6aa7ddf43263f30595b3f0733ec3e126e38608..7b822086a57c600ae9b5668d6d7a375d0ec55fa7 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
> @@ -667,6 +667,8 @@ lt9611_codec: hdmi-bridge@2b {
>  		pinctrl-names = "default";
>  		pinctrl-0 = <&lt9611_irq_pin &lt9611_rst_pin>;
>  
> +		#sound-dai-cells = <1>;
> +
>  		ports {
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> @@ -1016,6 +1018,14 @@ &sound {
>  			"TX SWR_INPUT0", "ADC3_OUTPUT",
>  			"TX SWR_INPUT1", "ADC4_OUTPUT";
>  
> +	pinctrl-0 = <&i2s0_default_state>, <&audio_mclk0_default_state>;
> +	pinctrl-names = "default";
> +
> +	clocks = <&q6prmcc LPASS_CLK_ID_PRI_MI2S_IBIT LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> +		 <&q6prmcc LPASS_CLK_ID_MCLK_1 LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> +	clock-names = "primart-mi2s",

"primary-mi2s"

[...]

> +			audio_mclk0_default_state: audio-mclk0-default-state {
> +				pins = "gpio125";
> +				function = "pri_mi2s";
> +				drive-strength = <8>;
> +				bias-disable;
> +				output-high;
> +			};
> +
> +			i2s0_default_state: i2s0-default-state {
> +				sck-pins {
> +					pins = "gpio126";
> +					function = "mi2s0_sck";
> +					drive-strength = <8>;
> +					bias-disable;
> +					output-high;

I doubt output-high for a clock pin is what you want..

> +				};
> +
> +				data0-pins {
> +					pins = "gpio127";
> +					function = "mi2s0_data0";
> +					drive-strength = <8>;
> +					bias-disable;
> +				};
> +
> +				data1-pins {
> +					pins = "gpio128";
> +					function = "mi2s0_data1";
> +					drive-strength = <8>;
> +					bias-disable;
> +				};
> +
> +				ws-pins {
> +					pins = "gpio129";
> +					function = "mi2s0_ws";
> +					drive-strength = <8>;
> +					bias-disable;
> +					output-high;

here too

Konrad

Re: [PATCH RFC v2 4/6] arm64: dts: qcom: sm8450-hdk: Enable I2S for HDMI

[Neil Armstrong]

On 10/9/25 14:37, Konrad Dybcio wrote:
> On 10/8/25 8:56 PM, Neil Armstrong wrote:
>> Add the necessary nodes to configure the right I2S interface
>> to output audio via the DSI HDMI bridge.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 26 +++++++++++++++++++++
>>   arch/arm64/boot/dts/qcom/sm8450.dtsi    | 40 +++++++++++++++++++++++++++++++++
>>   2 files changed, 66 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
>> index 0c6aa7ddf43263f30595b3f0733ec3e126e38608..7b822086a57c600ae9b5668d6d7a375d0ec55fa7 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
>> +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
>> @@ -667,6 +667,8 @@ lt9611_codec: hdmi-bridge@2b {
>>   		pinctrl-names = "default";
>>   		pinctrl-0 = <&lt9611_irq_pin &lt9611_rst_pin>;
>>   
>> +		#sound-dai-cells = <1>;
>> +
>>   		ports {
>>   			#address-cells = <1>;
>>   			#size-cells = <0>;
>> @@ -1016,6 +1018,14 @@ &sound {
>>   			"TX SWR_INPUT0", "ADC3_OUTPUT",
>>   			"TX SWR_INPUT1", "ADC4_OUTPUT";
>>   
>> +	pinctrl-0 = <&i2s0_default_state>, <&audio_mclk0_default_state>;
>> +	pinctrl-names = "default";
>> +
>> +	clocks = <&q6prmcc LPASS_CLK_ID_PRI_MI2S_IBIT LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> +		 <&q6prmcc LPASS_CLK_ID_MCLK_1 LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> +	clock-names = "primart-mi2s",
> 
> "primary-mi2s"
> 
> [...]

Damn typo

> 
>> +			audio_mclk0_default_state: audio-mclk0-default-state {
>> +				pins = "gpio125";
>> +				function = "pri_mi2s";
>> +				drive-strength = <8>;
>> +				bias-disable;
>> +				output-high;
>> +			};
>> +
>> +			i2s0_default_state: i2s0-default-state {
>> +				sck-pins {
>> +					pins = "gpio126";
>> +					function = "mi2s0_sck";
>> +					drive-strength = <8>;
>> +					bias-disable;
>> +					output-high;
> 
> I doubt output-high for a clock pin is what you want..

This was copied from downstream:

================><============================
		i2s0_sck_active: i2s0_sck_active {
<snip>
			config {
				pins = "gpio126";
				drive-strength = <8>;   /* 8 mA */
				bias-disable;           /* NO PULL */
				output-high;
			};
<snip>
		i2s0_ws_active: i2s0_ws_active {
<snip>
			config {
				pins = "gpio129";
				drive-strength = <8>;   /* 8 mA */
				bias-disable;           /* NO PULL */
				output-high;
			};
================><============================

And also set the same way arch/arm64/boot/dts/qcom/sm4250.dtsi

And I guess this level would only set when the function is not active.

Neil

> 
>> +				};
>> +
>> +				data0-pins {
>> +					pins = "gpio127";
>> +					function = "mi2s0_data0";
>> +					drive-strength = <8>;
>> +					bias-disable;
>> +				};
>> +
>> +				data1-pins {
>> +					pins = "gpio128";
>> +					function = "mi2s0_data1";
>> +					drive-strength = <8>;
>> +					bias-disable;
>> +				};
>> +
>> +				ws-pins {
>> +					pins = "gpio129";
>> +					function = "mi2s0_ws";
>> +					drive-strength = <8>;
>> +					bias-disable;
>> +					output-high;
> 
> here too
> 
> Konrad

[PATCH RFC v2 5/6] arm64: dts: qcom: sm8550-hdk: Enable I2S for HDMI

[Neil Armstrong]

Add the necessary nodes to configure the right I2S interface
to output audio via the DSI HDMI bridge.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 26 ++++++++++++
 arch/arm64/boot/dts/qcom/sm8550.dtsi    | 73 +++++++++++++++++++++++++++++++++
 2 files changed, 99 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index b5d7f0cd443a18b167c94e450b5b9412897b2ba2..7c163344b064a90bfa4f9629e2aaf409cbe81965 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -215,6 +215,14 @@ sound {
 				"TX SWR_INPUT1", "ADC2_OUTPUT",
 				"TX SWR_INPUT1", "ADC4_OUTPUT";
 
+		pinctrl-0 = <&i2s0_default_state>, <&audio_mclk0_default_state>;
+		pinctrl-names = "default";
+
+		clocks = <&q6prmcc LPASS_CLK_ID_PRI_MI2S_IBIT LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+			 <&q6prmcc LPASS_CLK_ID_MCLK_1 LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+		clock-names = "primary-mi2s",
+			      "primary-mclk";
+
 		wcd-playback-dai-link {
 			link-name = "WCD Playback";
 
@@ -278,6 +286,22 @@ platform {
 				sound-dai = <&q6apm>;
 			};
 		};
+
+		prim-mi2s-dai-link {
+			link-name = "HDMI Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>;
+			};
+
+			codec {
+				sound-dai = <&lt9611_codec 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
 	};
 
 	wcn7850-pmu {
@@ -891,6 +915,8 @@ lt9611_codec: hdmi-bridge@2b {
 		pinctrl-0 = <&lt9611_irq_pin>, <&lt9611_rst_pin>;
 		pinctrl-names = "default";
 
+		#sound-dai-cells = <1>;
+
 		ports {
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 7724dba75db79a9e66a2c61e1ea3607bacfdf5bb..73df93288f6e0ed71ec1e7f5ae09276e7593fd60 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -4956,6 +4956,79 @@ data-pins {
 					drive-strength = <10>;
 				};
 			};
+
+			audio_mclk0_default_state: audio-mclk0-default-state {
+				pins = "gpio125";
+				function = "audio_ext_mclk0";
+				drive-strength = <8>;
+				bias-disable;
+				output-high;
+			};
+
+			i2s0_default_state: i2s0-default-state {
+				sck-pins {
+					pins = "gpio126";
+					function = "i2s0_sck";
+					drive-strength = <8>;
+					bias-disable;
+					output-high;
+				};
+
+				data0-pins {
+					pins = "gpio127";
+					function = "i2s0_data0";
+					drive-strength = <8>;
+					bias-disable;
+				};
+
+				data1-pins {
+					pins = "gpio128";
+					function = "i2s0_data1";
+					drive-strength = <8>;
+					bias-disable;
+				};
+
+				ws-pins {
+					pins = "gpio129";
+					function = "i2s0_ws";
+					drive-strength = <8>;
+					bias-disable;
+					output-high;
+				};
+			};
+
+			audio_mclk1_default_state: audio-mclk1-default-state {
+				pins = "gpio124";
+				function = "audio_ext_mclk1";
+				drive-strength = <8>;
+				bias-disable;
+				output-high;
+			};
+
+			i2s1_default_state: i2s1-default-state {
+				sck-pins {
+					pins = "gpio121";
+					function = "i2s1_sck";
+					drive-strength = <8>;
+					bias-disable;
+					output-high;
+				};
+
+				data0-pins {
+					pins = "gpio122";
+					function = "i2s1_data0";
+					drive-strength = <8>;
+					bias-disable;
+				};
+
+				ws-pins {
+					pins = "gpio123";
+					function = "i2s1_ws";
+					drive-strength = <8>;
+					bias-disable;
+					output-high;
+				};
+			};
 		};
 
 		apps_smmu: iommu@15000000 {

-- 
2.34.1

[PATCH RFC v2 6/6] arm64: dts: qcom: sm8650-hdk: Enable I2S for HDMI

[Neil Armstrong]

Add the necessary nodes to configure the right I2S interface
to output audio via the DSI HDMI bridge.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 25 +++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sm8650.dtsi    | 40 +++++++++++++++++++++++++++++++++
 2 files changed, 65 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
index 87d7190dc991b11f5d1162aabb693dcadd198c51..e15c65a97852f2e27d1c1d282945feeddec20f6f 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
@@ -171,6 +171,14 @@ sound {
 				"TX SWR_INPUT1", "ADC2_OUTPUT",
 				"TX SWR_INPUT3", "ADC4_OUTPUT";
 
+		pinctrl-0 = <&i2s0_default_state>, <&audio_mclk0_default_state>;
+		pinctrl-names = "default";
+
+		clocks = <&q6prmcc LPASS_CLK_ID_PRI_MI2S_IBIT LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+			 <&q6prmcc LPASS_CLK_ID_MCLK_1 LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+		clock-names = "primary-mi2s",
+			      "primary-mclk";
+
 		wcd-playback-dai-link {
 			link-name = "WCD Playback";
 
@@ -218,6 +226,22 @@ platform {
 				sound-dai = <&q6apm>;
 			};
 		};
+
+		pri-mi2s-dai-link {
+			link-name = "HDMI Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>;
+			};
+
+			codec {
+				sound-dai = <&lt9611_codec 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
 	};
 
 	vph_pwr: regulator-vph-pwr {
@@ -853,6 +877,7 @@ &i2c6 {
 	lt9611_codec: hdmi-bridge@2b {
 		compatible = "lontium,lt9611uxc";
 		reg = <0x2b>;
+		#sound-dai-cells = <1>;
 
 		interrupts-extended = <&tlmm 85 IRQ_TYPE_EDGE_FALLING>;
 
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index ebf1971b1bfbebf4df5a80247a6682ac8e413e3b..7cf5073a29ed4aaf72662a4e05ba1c6bfb118a3f 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -6203,6 +6203,46 @@ wake-pins {
 				};
 			};
 
+			audio_mclk0_default_state: audio-mclk0-default-state {
+				pins = "gpio125";
+				function = "audio_ext_mclk0";
+				drive-strength = <8>;
+				bias-disable;
+				output-high;
+			};
+
+			i2s0_default_state: i2s0-default-state {
+				sck-pins {
+					pins = "gpio126";
+					function = "i2s0_sck";
+					drive-strength = <8>;
+					bias-disable;
+					output-high;
+				};
+
+				data0-pins {
+					pins = "gpio127";
+					function = "i2s0_data0";
+					drive-strength = <8>;
+					bias-disable;
+				};
+
+				data1-pins {
+					pins = "gpio128";
+					function = "i2s0_data1";
+					drive-strength = <8>;
+					bias-disable;
+				};
+
+				ws-pins {
+					pins = "gpio129";
+					function = "i2s0_ws";
+					drive-strength = <8>;
+					bias-disable;
+					output-high;
+				};
+			};
+
 			qup_i2c0_data_clk: qup-i2c0-data-clk-state {
 				/* SDA, SCL */
 				pins = "gpio32", "gpio33";

-- 
2.34.1