[PATCH 6/6] irqchip: brcmstb-l2: Add support for the BCM7271 L2 controller

[PATCH 6/6] irqchip: brcmstb-l2: Add support for the BCM7271 L2 controller

[Doug Berger]

Add the initialization of the generic irq chip for the BCM7271 L2
interrupt controller.  This controller only supports level
interrupts and uses the "brcm,bcm7271-l2-intc" compatibility
string.

Signed-off-by: Doug Berger <opendmb@gmail.com>
---
 .../bindings/interrupt-controller/brcm,l2-intc.txt |  3 +-
 drivers/irqchip/irq-brcmstb-l2.c                   | 86 ++++++++++++++++------
 2 files changed, 66 insertions(+), 23 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
index 448273a30a11..36df06c5c567 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
@@ -2,7 +2,8 @@ Broadcom Generic Level 2 Interrupt Controller
 
 Required properties:
 
-- compatible: should be "brcm,l2-intc"
+- compatible: should be "brcm,l2-intc" for latched interrupt controllers
+              should be "brcm,bcm7271-l2-intc" for level interrupt controllers
 - reg: specifies the base physical address and size of the registers
 - interrupt-controller: identifies the node as an interrupt controller
 - #interrupt-cells: specifies the number of cells needed to encode an
diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c
index ce3850530e2b..f77e6c9530dc 100644
--- a/drivers/irqchip/irq-brcmstb-l2.c
+++ b/drivers/irqchip/irq-brcmstb-l2.c
@@ -31,13 +31,34 @@
 #include <linux/irqchip.h>
 #include <linux/irqchip/chained_irq.h>
 
-/* Register offsets in the L2 interrupt controller */
-#define CPU_STATUS	0x00
-#define CPU_SET		0x04
-#define CPU_CLEAR	0x08
-#define CPU_MASK_STATUS	0x0c
-#define CPU_MASK_SET	0x10
-#define CPU_MASK_CLEAR	0x14
+struct brcmstb_intc_init_params {
+	irq_flow_handler_t handler;
+	int cpu_status;
+	int cpu_clear;
+	int cpu_mask_status;
+	int cpu_mask_set;
+	int cpu_mask_clear;
+};
+
+/* Register offsets in the L2 latched interrupt controller */
+static const struct brcmstb_intc_init_params l2_edge_intc_init = {
+	.handler		= handle_edge_irq,
+	.cpu_status		= 0x00,
+	.cpu_clear		= 0x08,
+	.cpu_mask_status	= 0x0c,
+	.cpu_mask_set		= 0x10,
+	.cpu_mask_clear		= 0x14
+};
+
+/* Register offsets in the L2 level interrupt controller */
+static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
+	.handler		= handle_level_irq,
+	.cpu_status		= 0x00,
+	.cpu_clear		= -1, /* Register not present */
+	.cpu_mask_status	= 0x04,
+	.cpu_mask_set		= 0x08,
+	.cpu_mask_clear		= 0x0C
+};
 
 /* L2 intc private data structure */
 struct brcmstb_l2_intc_data {
@@ -102,7 +123,7 @@ static void brcmstb_l2_intc_resume(struct irq_data *d)
 	struct brcmstb_l2_intc_data *b = gc->private;
 
 	irq_gc_lock(gc);
-	if (ct->chip.irq_ack != irq_gc_noop) {
+	if (ct->chip.irq_ack) {
 		/* Clear unmasked non-wakeup interrupts */
 		irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
 				ct->regs.ack);
@@ -115,7 +136,9 @@ static void brcmstb_l2_intc_resume(struct irq_data *d)
 }
 
 static int __init brcmstb_l2_intc_of_init(struct device_node *np,
-					  struct device_node *parent)
+					  struct device_node *parent,
+					  const struct brcmstb_intc_init_params
+					  *init_params)
 {
 	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
 	struct brcmstb_l2_intc_data *data;
@@ -137,12 +160,12 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np,
 	}
 
 	/* Disable all interrupts by default */
-	writel(0xffffffff, base + CPU_MASK_SET);
+	writel(0xffffffff, base + init_params->cpu_mask_set);
 
 	/* Wakeup interrupts may be retained from S5 (cold boot) */
 	data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
-	if (!data->can_wake)
-		writel(0xffffffff, base + CPU_CLEAR);
+	if (!data->can_wake && (init_params->cpu_clear >= 0))
+		writel(0xffffffff, base + init_params->cpu_clear);
 
 	parent_irq = irq_of_parse_and_map(np, 0);
 	if (!parent_irq) {
@@ -167,7 +190,7 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np,
 
 	/* Allocate a single Generic IRQ chip for this node */
 	ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
-				np->full_name, handle_edge_irq, clr, 0, flags);
+			np->full_name, init_params->handler, clr, 0, flags);
 	if (ret) {
 		pr_err("failed to allocate generic irq chip\n");
 		goto out_free_domain;
@@ -180,21 +203,26 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np,
 	data->gc = irq_get_domain_generic_chip(data->domain, 0);
 	data->gc->reg_base = base;
 	data->gc->private = data;
-	data->status_offset = CPU_STATUS;
-	data->mask_offset = CPU_MASK_STATUS;
+	data->status_offset = init_params->cpu_status;
+	data->mask_offset = init_params->cpu_mask_status;
 
 	ct = data->gc->chip_types;
 
-	ct->chip.irq_ack = irq_gc_ack_set_bit;
-	ct->regs.ack = CPU_CLEAR;
+	if (init_params->cpu_clear >= 0) {
+		ct->regs.ack = init_params->cpu_clear;
+		ct->chip.irq_ack = irq_gc_ack_set_bit;
+		ct->chip.irq_mask_ack = irq_gc_mask_disable_and_ack_set;
+	} else {
+		/* No Ack - but still slightly more efficient to define this */
+		ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
+	}
 
 	ct->chip.irq_mask = irq_gc_mask_disable_reg;
-	ct->chip.irq_mask_ack = irq_gc_mask_disable_and_ack_set;
-	ct->regs.disable = CPU_MASK_SET;
-	ct->regs.mask = CPU_MASK_STATUS;
+	ct->regs.disable = init_params->cpu_mask_set;
+	ct->regs.mask = init_params->cpu_mask_status;
 
 	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
-	ct->regs.enable = CPU_MASK_CLEAR;
+	ct->regs.enable = init_params->cpu_mask_clear;
 
 	ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
 	ct->chip.irq_resume = brcmstb_l2_intc_resume;
@@ -220,4 +248,18 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np,
 	kfree(data);
 	return ret;
 }
-IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_intc_of_init);
+
+int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
+	struct device_node *parent)
+{
+	return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
+}
+IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init);
+
+int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
+	struct device_node *parent)
+{
+	return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
+}
+IRQCHIP_DECLARE(bcm7271_l2_intc, "brcm,bcm7271-l2-intc",
+	brcmstb_l2_lvl_intc_of_init);
-- 
2.13.0

Re: [PATCH 0/6] Add support for BCM7271 style interrupt controller

[Doug Berger]

Sorry, messed up the CC list.

On 07/07/2017 12:20 PM, Doug Berger wrote:
> This patch set extends the functionality of the irq-brcmstb-l2 interrupt
> controller driver to cover a hardware variant first introduced in the
> BCM7271 SoC.  The main difference between this variant and the block
> found in earlier brcmstb SoCs is that this variant only supports level
> sensitive interrupts and therefore does not latch the interrupt state
> based on edges.  Since there is no longer a need to ack interrupts with
> a register write to clear the latch the register map has been changed.
> 
> Therefore the change to add support for the new hardware block is to
> abstract the register accesses to accommodate different maps and to
> identify the block with a new device-tree compatible string.
> 
> I also took the opportunity to make some small efficiency enhancements
> to the driver.  One of these was to make use of the slightly more
> efficient irq_mask_ack method.  However, I discovered that the defined
> irq_gc_mask_disable_reg_and_ack() generic irq function was insufficient
> for my needs.  The first three commits of this set are intended to be a
> correction and extension of the existing generic irq implementation to
> provide a set of functions that can be used by interrupt controller
> drivers for their irq_mask_ack method.
> 
> I believe these first three commits should be added to the irq/core
> repository and the remaining commits should be added to the Broadcom
> github repository but have included the complete set here for improved
> context.  This entire set is therefore based on the irq/core master
> branch.  Please let me know if you would like a different packaging.
> 
> If the changes to genirq are not acceptable I can implement the
> irq_mask_ask method locally in the irq-brcmstb-l2 driver and submit
> that on its own.
> 
> Doug Berger (5):
>   genirq: generic chip: add generic irq_mask_ack functions
>   genirq: generic chip: remove irq_gc_mask_disable_reg_and_ack()
>   irqchip: brcmstb-l2: Remove some processing from the handler
>   irqchip: brcmstb-l2: Abstract register accesses
>   irqchip: brcmstb-l2: Add support for the BCM7271 L2 controller
> 
> Florian Fainelli (1):
>   irqchip/tango: Use irq_gc_mask_disable_and_ack_set
> 
>  .../bindings/interrupt-controller/brcm,l2-intc.txt |   3 +-
>  drivers/irqchip/irq-brcmstb-l2.c                   | 145 ++++++++++++++-------
>  drivers/irqchip/irq-tango.c                        |   2 +-
>  include/linux/irq.h                                |   7 +-
>  kernel/irq/generic-chip.c                          | 110 +++++++++++++++-
>  5 files changed, 214 insertions(+), 53 deletions(-)
> 

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Re: [PATCH 0/6] Add support for BCM7271 style interrupt controller

[Florian Fainelli]

On 07/07/2017 12:34 PM, Doug Berger wrote:
> Sorry, messed up the CC list.
> 
> On 07/07/2017 12:20 PM, Doug Berger wrote:
>> This patch set extends the functionality of the irq-brcmstb-l2 interrupt
>> controller driver to cover a hardware variant first introduced in the
>> BCM7271 SoC.  The main difference between this variant and the block
>> found in earlier brcmstb SoCs is that this variant only supports level
>> sensitive interrupts and therefore does not latch the interrupt state
>> based on edges.  Since there is no longer a need to ack interrupts with
>> a register write to clear the latch the register map has been changed.
>>
>> Therefore the change to add support for the new hardware block is to
>> abstract the register accesses to accommodate different maps and to
>> identify the block with a new device-tree compatible string.
>>
>> I also took the opportunity to make some small efficiency enhancements
>> to the driver.  One of these was to make use of the slightly more
>> efficient irq_mask_ack method.  However, I discovered that the defined
>> irq_gc_mask_disable_reg_and_ack() generic irq function was insufficient
>> for my needs.  The first three commits of this set are intended to be a
>> correction and extension of the existing generic irq implementation to
>> provide a set of functions that can be used by interrupt controller
>> drivers for their irq_mask_ack method.
>>
>> I believe these first three commits should be added to the irq/core
>> repository and the remaining commits should be added to the Broadcom
>> github repository but have included the complete set here for improved
>> context.  This entire set is therefore based on the irq/core master
>> branch.  Please let me know if you would like a different packaging.

The irqchip maintainers (Thomas, Jason, Marc Z.) will probably want to
get irqchip drivers changes through their tree:

IRQCHIP DRIVERS
M:      Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
M:      Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>
M:      Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
L:      linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
S:      Maintained
T:      git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
irq/core
T:      git git://git.infradead.org/users/jcooper/linux.git irqchip/core
F:      Documentation/devicetree/bindings/interrupt-controller/
F:      drivers/irqchip/

Will reply to the individual patches, thanks for getting this out.

>>
>> If the changes to genirq are not acceptable I can implement the
>> irq_mask_ask method locally in the irq-brcmstb-l2 driver and submit
>> that on its own.
>>
>> Doug Berger (5):
>>   genirq: generic chip: add generic irq_mask_ack functions
>>   genirq: generic chip: remove irq_gc_mask_disable_reg_and_ack()
>>   irqchip: brcmstb-l2: Remove some processing from the handler
>>   irqchip: brcmstb-l2: Abstract register accesses
>>   irqchip: brcmstb-l2: Add support for the BCM7271 L2 controller
>>
>> Florian Fainelli (1):
>>   irqchip/tango: Use irq_gc_mask_disable_and_ack_set
>>
>>  .../bindings/interrupt-controller/brcm,l2-intc.txt |   3 +-
>>  drivers/irqchip/irq-brcmstb-l2.c                   | 145 ++++++++++++++-------
>>  drivers/irqchip/irq-tango.c                        |   2 +-
>>  include/linux/irq.h                                |   7 +-
>>  kernel/irq/generic-chip.c                          | 110 +++++++++++++++-
>>  5 files changed, 214 insertions(+), 53 deletions(-)
>>
> 


-- 
Florian
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Re: [PATCH 6/6] irqchip: brcmstb-l2: Add support for the BCM7271 L2 controller

[Rob Herring]

On Fri, Jul 07, 2017 at 12:20:16PM -0700, Doug Berger wrote:
> Add the initialization of the generic irq chip for the BCM7271 L2
> interrupt controller.  This controller only supports level
> interrupts and uses the "brcm,bcm7271-l2-intc" compatibility
> string.
> 
> Signed-off-by: Doug Berger <opendmb@gmail.com>
> ---
>  .../bindings/interrupt-controller/brcm,l2-intc.txt |  3 +-

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/irqchip/irq-brcmstb-l2.c                   | 86 ++++++++++++++++------
>  2 files changed, 66 insertions(+), 23 deletions(-)

Re: [PATCH 6/6] irqchip: brcmstb-l2: Add support for the BCM7271 L2 controller

[Florian Fainelli]

On 07/07/2017 12:20 PM, Doug Berger wrote:
> Add the initialization of the generic irq chip for the BCM7271 L2
> interrupt controller.  This controller only supports level
> interrupts and uses the "brcm,bcm7271-l2-intc" compatibility
> string.
> 
> Signed-off-by: Doug Berger <opendmb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Reviewed-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
-- 
Florian
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