From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Johan Hovold <johan@kernel.org>, Abel Vesa <abel.vesa@linaro.org>
Cc: Bjorn Andersson <andersson@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Rajendra Nayak <quic_rjendra@quicinc.com>,
Sibi Sankar <quic_sibis@quicinc.com>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: qcom: x1e80100: Make the PCIe 6a PHY support 4 lanes mode
Date: Tue, 4 Jun 2024 14:00:10 +0200 [thread overview]
Message-ID: <d93fe55e-7c65-48cb-bdaf-5e15bc22be30@linaro.org> (raw)
In-Reply-To: <Zl28nvnpGFRsYpGh@hovoldconsulting.com>
On 6/3/24 14:52, Johan Hovold wrote:
[...]
>
> As I just mentioned in my reply on the PHY patch, this does not seem to
> work on the CRD were the link still come up as 2-lane (also with the
> clocks fixed):
>
> qcom-pcie 1bf8000.pci: PCIe Gen.4 x2 link up
>
> So something appears to be wrong here or in the PHY changes.
Is the device on the other end x4-capable? Or does it not matter in
this log line?
Konrad
next prev parent reply other threads:[~2024-06-04 12:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-31 17:00 [PATCH 0/2] arm64: dts: qcom: x1e80100: Fix the PCIe 6a node Abel Vesa
2024-05-31 17:00 ` [PATCH 1/2] arm64: dts: qcom: x1e80100: Fix PCIe 6a reg offsets and add MHI Abel Vesa
2024-06-04 12:04 ` Konrad Dybcio
2024-05-31 17:00 ` [PATCH 2/2] arm64: dts: qcom: x1e80100: Make the PCIe 6a PHY support 4 lanes mode Abel Vesa
2024-05-31 19:55 ` Dmitry Baryshkov
2024-06-03 12:52 ` Johan Hovold
2024-06-04 12:00 ` Konrad Dybcio [this message]
2024-06-04 12:20 ` Johan Hovold
2024-06-04 12:38 ` Konrad Dybcio
2024-06-04 12:45 ` Abel Vesa
2024-06-04 12:55 ` Konrad Dybcio
2024-06-04 14:35 ` Abel Vesa
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