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AJvYcCVJG9PZKm7zrjlvSwrzYQHaxKxh7VkBmXm3PeZA4Fh20uNlg/PmWATbuBCzCFRlo+wNh2blh8hMy9lpvLbR4QW+1sL0oBNUmh92mg== X-Gm-Message-State: AOJu0Ywz6JUv1olgnn24PA5UdEQNx7KJ9ySiiO1RnE1v1ceF8c+KGpH6 MSsrg80hdvJC0zIqbDaYxAX1KL9/8iW6Huisp3oCXrR+/vmIXYD3+W1+cjord08= X-Google-Smtp-Source: AGHT+IFKwWGMcmPYu0Ub5wCx2QiMD01tH+85fFGHMfPp5sK/V1U4H3V0F6RY+8M0VE4TG4elEaDvoQ== X-Received: by 2002:a92:dc83:0:b0:365:29e4:d95d with SMTP id c3-20020a92dc83000000b0036529e4d95dmr966458iln.30.1711066434179; Thu, 21 Mar 2024 17:13:54 -0700 (PDT) Received: from [100.64.0.1] ([136.226.86.189]) by smtp.gmail.com with ESMTPSA id y18-20020a056638015200b00476f1daad44sm206727jao.54.2024.03.21.17.13.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Mar 2024 17:13:53 -0700 (PDT) Message-ID: Date: Thu, 21 Mar 2024 19:13:52 -0500 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RISC-V] [tech-j-ext] [RFC PATCH 5/9] riscv: Split per-CPU and per-thread envcfg bits Content-Language: en-US To: Deepak Gupta , Conor Dooley , Palmer Dabbelt Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, tech-j-ext@lists.risc-v.org, kasan-dev@googlegroups.com, Evgenii Stepanov , Krzysztof Kozlowski , Rob Herring , Andrew Jones , Guo Ren , Heiko Stuebner , Paul Walmsley References: <20240319215915.832127-1-samuel.holland@sifive.com> <20240319215915.832127-6-samuel.holland@sifive.com> <40ab1ce5-8700-4a63-b182-1e864f6c9225@sifive.com> From: Samuel Holland In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 2024-03-19 11:39 PM, Deepak Gupta wrote: >>>> --- a/arch/riscv/include/asm/switch_to.h >>>> +++ b/arch/riscv/include/asm/switch_to.h >>>> @@ -69,6 +69,17 @@ static __always_inline bool has_fpu(void) { return false; } >>>> #define __switch_to_fpu(__prev, __next) do { } while (0) >>>> #endif >>>> >>>> +static inline void sync_envcfg(struct task_struct *task) >>>> +{ >>>> + csr_write(CSR_ENVCFG, this_cpu_read(riscv_cpu_envcfg) | task->thread.envcfg); >>>> +} >>>> + >>>> +static inline void __switch_to_envcfg(struct task_struct *next) >>>> +{ >>>> + if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG)) >>> >>> I've seen `riscv_cpu_has_extension_unlikely` generating branchy code >>> even if ALTERNATIVES was turned on. >>> Can you check disasm on your end as well. IMHO, `entry.S` is a better >>> place to pick up *envcfg. >> >> The branchiness is sort of expected, since that function is implemented by >> switching on/off a branch instruction, so the alternate code is necessarily a >> separate basic block. It's a tradeoff so we don't have to write assembly code >> for every bit of code that depends on an extension. However, the cost should be >> somewhat lowered since the branch is unconditional and so entirely predictable. >> >> If the branch turns out to be problematic for performance, then we could use >> ALTERNATIVE directly in sync_envcfg() to NOP out the CSR write. > > Yeah I lean towards using alternatives directly. One thing to note here: we can't use alternatives directly if the behavior needs to be different on different harts (i.e. a subset of harts implement the envcfg CSR). I think we need some policy about which ISA extensions are allowed to be asymmetric across harts, or else we add too much complexity. Regards, Samuel