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[83.9.31.248]) by smtp.gmail.com with ESMTPSA id l26-20020a19c21a000000b004e88a166eb6sm454048lfc.46.2023.05.09.13.17.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 May 2023 13:17:39 -0700 (PDT) Message-ID: Date: Tue, 9 May 2023 22:17:37 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.1 Subject: Re: [PATCH V4 3/3] arm64: dts: qcom: sm8450: Add video clock controller Content-Language: en-US To: Taniya Das , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Andy Gross , Michael Turquette Cc: Bjorn Andersson , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_skakitap@quicinc.com, quic_jkona@quicinc.com References: <20230509172148.7627-1-quic_tdas@quicinc.com> <20230509172148.7627-4-quic_tdas@quicinc.com> From: Konrad Dybcio In-Reply-To: <20230509172148.7627-4-quic_tdas@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 9.05.2023 19:21, Taniya Das wrote: > Add device node for video clock controller on Qualcomm SM8450 platform. > > Signed-off-by: Taniya Das > --- > Changes since V3: > - None. > > Changes since V2: > - No changes. > > Changes since V1: > - No changes. > > arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 595533aeafc4..00ff8efa53c7 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -756,6 +756,18 @@ > "usb3_phy_wrapper_gcc_usb30_pipe_clk"; > }; > > + videocc: clock-controller@aaf0000 { Nodes should be sorted by unit address. This one belongs before cci@ac15000. > + compatible = "qcom,sm8450-videocc"; > + reg = <0 0x0aaf0000 0 0x10000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_VIDEO_AHB_CLK>; Older SoCs used to provide a vote on XO_A for videocc ahb_clk_src, I'd assume that's now taken care of internally? Konrad > + power-domains = <&rpmhpd SM8450_MMCX>; > + required-opps = <&rpmhpd_opp_low_svs>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > gpi_dma2: dma-controller@800000 { > compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; > #dma-cells = <3>;