[PATCH 0/7] Add support for IPQ5018 tsens

[PATCH 0/7] Add support for IPQ5018 tsens

[Sricharan Ramabadhran]

IPQ5018 has tsens V1.0 IP with 4 sensors and 1 interrupt.
There is no RPM present in the soc to do tsens early enable.
Adding support for the same here.

Sricharan Ramabadhran (7):
  dt-bindings: thermal: qcom-tsens: Add ipq5018 compatible
  thermal/drivers/qcom: Add new feat for soc without rpm
  thermal/drivers/qcom/tsens: Add support for IPQ5018 tsens.
  thermal/drivers/qcom: Add IPQ5018 compatible.
  dt-bindings: nvmem: Add compatible for IPQ5018
  arm64: dts: qcom: ipq5018: Add tsens node
  arm64: dts: qcom: ipq5018: Add thermal zones

 .../bindings/nvmem/qcom,qfprom.yaml           |   1 +
 .../bindings/thermal/qcom-tsens.yaml          |  19 +++
 arch/arm64/boot/dts/qcom/ipq5018.dtsi         |  81 ++++++++++++
 drivers/thermal/qcom/tsens-v1.c               | 115 ++++++++++++++++++
 drivers/thermal/qcom/tsens.c                  |   5 +-
 drivers/thermal/qcom/tsens.h                  |   5 +-
 6 files changed, 224 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH 1/7] dt-bindings: thermal: qcom-tsens: Add ipq5018 compatible

[Sricharan Ramabadhran]

IPQ5018 has tsens v1.0 block with 4 sensors and 1 interrupt.

Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
 .../bindings/thermal/qcom-tsens.yaml          | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
index 27e9e16e6455..2309bb6dce1b 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
@@ -42,6 +42,7 @@ properties:
               - qcom,msm8956-tsens
               - qcom,msm8976-tsens
               - qcom,qcs404-tsens
+              - qcom,ipq5018-tsens
           - const: qcom,tsens-v1
 
       - description: v2 of TSENS
@@ -409,4 +410,22 @@ examples:
            #qcom,sensors = <16>;
            #thermal-sensor-cells = <1>;
     };
+
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    // Example 5 (for any IPQ5018 based SoC-s):
+    tsens5: thermal-sensor@4a9000 {
+           compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1";
+           reg = <0x4a9000 0x1000>, /* TM */
+                 <0x4a8000 0x1000>; /* SORT */
+
+           nvmem-cells = <&tsens_calib>;
+           nvmem-cell-names = "calib";
+
+           interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+           interrupt-names = "uplow";
+
+           #qcom,sensors = <5>;
+           #thermal-sensor-cells = <1>;
+    };
 ...
-- 
2.34.1

Re: [PATCH 1/7] dt-bindings: thermal: qcom-tsens: Add ipq5018 compatible

[Krzysztof Kozlowski]

On 28/08/2023 21:18, Sricharan Ramabadhran wrote:
> IPQ5018 has tsens v1.0 block with 4 sensors and 1 interrupt.
> 
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---
>  .../bindings/thermal/qcom-tsens.yaml          | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> index 27e9e16e6455..2309bb6dce1b 100644
> --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> @@ -42,6 +42,7 @@ properties:
>                - qcom,msm8956-tsens
>                - qcom,msm8976-tsens
>                - qcom,qcs404-tsens
> +              - qcom,ipq5018-tsens

This does not look like placed in alphanumeric order.

>            - const: qcom,tsens-v1
>  
>        - description: v2 of TSENS
> @@ -409,4 +410,22 @@ examples:
>             #qcom,sensors = <16>;
>             #thermal-sensor-cells = <1>;
>      };
> +
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    // Example 5 (for any IPQ5018 based SoC-s):

No need for new example for a difference in compatible. Drop it.
Best regards,
Krzysztof

Re: [PATCH 1/7] dt-bindings: thermal: qcom-tsens: Add ipq5018 compatible

[Sricharan Ramabadhran]

Hi Krzysztof,

On 8/29/2023 12:51 AM, Krzysztof Kozlowski wrote:
> On 28/08/2023 21:18, Sricharan Ramabadhran wrote:
>> IPQ5018 has tsens v1.0 block with 4 sensors and 1 interrupt.
>>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> ---
>>   .../bindings/thermal/qcom-tsens.yaml          | 19 +++++++++++++++++++
>>   1 file changed, 19 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
>> index 27e9e16e6455..2309bb6dce1b 100644
>> --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
>> +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
>> @@ -42,6 +42,7 @@ properties:
>>                 - qcom,msm8956-tsens
>>                 - qcom,msm8976-tsens
>>                 - qcom,qcs404-tsens
>> +              - qcom,ipq5018-tsens
> 
> This does not look like placed in alphanumeric order.
> 

  ok, will sort.

>>             - const: qcom,tsens-v1
>>   
>>         - description: v2 of TSENS
>> @@ -409,4 +410,22 @@ examples:
>>              #qcom,sensors = <16>;
>>              #thermal-sensor-cells = <1>;
>>       };
>> +
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    // Example 5 (for any IPQ5018 based SoC-s):
> 
> No need for new example for a difference in compatible. Drop it.

  ok, will drop it.

Regards,
  Sricharan

[PATCH 2/7] thermal/drivers/qcom: Add new feat for soc without rpm

[Sricharan Ramabadhran]

Some of the tsens IP like the one in IPQ5018 does not have a
RPM in the soc. Hence the early init to enable tsens would not
be done. So add a flag for that in feat and skip enable checks.

Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
 drivers/thermal/qcom/tsens.c | 2 +-
 drivers/thermal/qcom/tsens.h | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c
index 98c356acfe98..f39495b61952 100644
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -974,7 +974,7 @@ int __init init_common(struct tsens_priv *priv)
 	ret = regmap_field_read(priv->rf[TSENS_EN], &enabled);
 	if (ret)
 		goto err_put_device;
-	if (!enabled) {
+	if (!enabled && !(priv->feat->no_early_init)) {
 		dev_err(dev, "%s: device not enabled\n", __func__);
 		ret = -ENODEV;
 		goto err_put_device;
diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h
index 2805de1c6827..fb73e3dd0de9 100644
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -505,6 +505,8 @@ enum regfield_ids {
  * @srot_split: does the IP neatly splits the register space into SROT and TM,
  *              with SROT only being available to secure boot firmware?
  * @has_watchdog: does this IP support watchdog functionality?
+ * @no_early_init: does this IP reside in a soc that does not have rpm to
+ *                 do pre-init.
  * @max_sensors: maximum sensors supported by this version of the IP
  * @trip_min_temp: minimum trip temperature supported by this version of the IP
  * @trip_max_temp: maximum trip temperature supported by this version of the IP
@@ -516,6 +518,7 @@ struct tsens_features {
 	unsigned int adc:1;
 	unsigned int srot_split:1;
 	unsigned int has_watchdog:1;
+	unsigned int no_early_init:1;
 	unsigned int max_sensors;
 	int trip_min_temp;
 	int trip_max_temp;
-- 
2.34.1

Re: [PATCH 2/7] thermal/drivers/qcom: Add new feat for soc without rpm

[Dmitry Baryshkov]

On Mon, 28 Aug 2023 at 22:20, Sricharan Ramabadhran
<quic_srichara@quicinc.com> wrote:
>
> Some of the tsens IP like the one in IPQ5018 does not have a
> RPM in the soc. Hence the early init to enable tsens would not

Tsens IP doesn't have RPM. Please rephrase this.

> be done. So add a flag for that in feat and skip enable checks.
>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---
>  drivers/thermal/qcom/tsens.c | 2 +-
>  drivers/thermal/qcom/tsens.h | 3 +++
>  2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c
> index 98c356acfe98..f39495b61952 100644
> --- a/drivers/thermal/qcom/tsens.c
> +++ b/drivers/thermal/qcom/tsens.c
> @@ -974,7 +974,7 @@ int __init init_common(struct tsens_priv *priv)
>         ret = regmap_field_read(priv->rf[TSENS_EN], &enabled);
>         if (ret)
>                 goto err_put_device;
> -       if (!enabled) {
> +       if (!enabled && !(priv->feat->no_early_init)) {
>                 dev_err(dev, "%s: device not enabled\n", __func__);
>                 ret = -ENODEV;
>                 goto err_put_device;
> diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h
> index 2805de1c6827..fb73e3dd0de9 100644
> --- a/drivers/thermal/qcom/tsens.h
> +++ b/drivers/thermal/qcom/tsens.h
> @@ -505,6 +505,8 @@ enum regfield_ids {
>   * @srot_split: does the IP neatly splits the register space into SROT and TM,
>   *              with SROT only being available to secure boot firmware?
>   * @has_watchdog: does this IP support watchdog functionality?
> + * @no_early_init: does this IP reside in a soc that does not have rpm to
> + *                 do pre-init.
>   * @max_sensors: maximum sensors supported by this version of the IP
>   * @trip_min_temp: minimum trip temperature supported by this version of the IP
>   * @trip_max_temp: maximum trip temperature supported by this version of the IP
> @@ -516,6 +518,7 @@ struct tsens_features {
>         unsigned int adc:1;
>         unsigned int srot_split:1;
>         unsigned int has_watchdog:1;
> +       unsigned int no_early_init:1;

s/no_early_init/ignore_enable/

>         unsigned int max_sensors;
>         int trip_min_temp;
>         int trip_max_temp;
> --
> 2.34.1
>


-- 
With best wishes
Dmitry

Re: [PATCH 2/7] thermal/drivers/qcom: Add new feat for soc without rpm

[Sricharan Ramabadhran]

Hi Dmitry,

On 8/29/2023 2:47 AM, Dmitry Baryshkov wrote:
> On Mon, 28 Aug 2023 at 22:20, Sricharan Ramabadhran
> <quic_srichara@quicinc.com> wrote:
>>
>> Some of the tsens IP like the one in IPQ5018 does not have a
>> RPM in the soc. Hence the early init to enable tsens would not
> 
> Tsens IP doesn't have RPM. Please rephrase this.
> 

  ok.

>> be done. So add a flag for that in feat and skip enable checks.
>>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> ---
>>   drivers/thermal/qcom/tsens.c | 2 +-
>>   drivers/thermal/qcom/tsens.h | 3 +++
>>   2 files changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c
>> index 98c356acfe98..f39495b61952 100644
>> --- a/drivers/thermal/qcom/tsens.c
>> +++ b/drivers/thermal/qcom/tsens.c
>> @@ -974,7 +974,7 @@ int __init init_common(struct tsens_priv *priv)
>>          ret = regmap_field_read(priv->rf[TSENS_EN], &enabled);
>>          if (ret)
>>                  goto err_put_device;
>> -       if (!enabled) {
>> +       if (!enabled && !(priv->feat->no_early_init)) {
>>                  dev_err(dev, "%s: device not enabled\n", __func__);
>>                  ret = -ENODEV;
>>                  goto err_put_device;
>> diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h
>> index 2805de1c6827..fb73e3dd0de9 100644
>> --- a/drivers/thermal/qcom/tsens.h
>> +++ b/drivers/thermal/qcom/tsens.h
>> @@ -505,6 +505,8 @@ enum regfield_ids {
>>    * @srot_split: does the IP neatly splits the register space into SROT and TM,
>>    *              with SROT only being available to secure boot firmware?
>>    * @has_watchdog: does this IP support watchdog functionality?
>> + * @no_early_init: does this IP reside in a soc that does not have rpm to
>> + *                 do pre-init.
>>    * @max_sensors: maximum sensors supported by this version of the IP
>>    * @trip_min_temp: minimum trip temperature supported by this version of the IP
>>    * @trip_max_temp: maximum trip temperature supported by this version of the IP
>> @@ -516,6 +518,7 @@ struct tsens_features {
>>          unsigned int adc:1;
>>          unsigned int srot_split:1;
>>          unsigned int has_watchdog:1;
>> +       unsigned int no_early_init:1;
> 
> s/no_early_init/ignore_enable/
> 

  ok, will change.

Regards,
  Sricharan

[PATCH 3/7] thermal/drivers/qcom/tsens: Add support for IPQ5018 tsens

[Sricharan Ramabadhran]

IPQ5018 has tsens IP V1.0, 4 sensors and 1 interrupt.
The soc does not have a RPM, hence tsens has to be reset and
enabled in the driver init. Adding the driver support for same.

Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
 drivers/thermal/qcom/tsens-v1.c | 115 ++++++++++++++++++++++++++++++++
 drivers/thermal/qcom/tsens.h    |   2 +-
 2 files changed, 116 insertions(+), 1 deletion(-)

diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c
index dc1c4ae2d8b0..a74dae69408b 100644
--- a/drivers/thermal/qcom/tsens-v1.c
+++ b/drivers/thermal/qcom/tsens-v1.c
@@ -42,6 +42,59 @@ static struct tsens_legacy_calibration_format tsens_qcs404_nvmem = {
 	},
 };
 
+struct tsens_legacy_calibration_format tsens_ipq5018_nvmem = {
+	.base_len = 8,
+	.base_shift = 2,
+	.sp_len = 6,
+	.mode = { 0, 8 },
+	.invalid = { 0, 2 },
+	.base = { { 0, 11 }, { 0, 19 } },
+	.sp = {
+		{ { 0, 27 },  { 1, 1 } },
+		{ { 1, 7 },  { 1, 13 } },
+		{ { 1, 19 },  { 1, 25 } },
+		{ { 1, 31 },  { 2, 5 } },
+		{ { 2, 11 },  { 3, 0 } },
+	},
+};
+
+static void fixup_ipq5018_points(int mode, u32 *p1, u32 *p2)
+{
+	if (mode == NO_PT_CALIB) {
+		p1[0] = 403;
+		p2[0] = 688;
+		p1[1] = 390;
+		p2[1] = 674;
+		p1[2] = 341;
+		p2[2] = 635;
+		p1[3] = 387;
+		p2[3] = 673;
+		p1[4] = 347;
+		p2[4] = 639;
+	}
+}
+
+static int calibrate_ipq5018(struct tsens_priv *priv)
+{
+	u32 p1[10], p2[10];
+	u32 *qfprom_cdata;
+	int mode;
+
+	qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib");
+	if (IS_ERR(qfprom_cdata))
+		return PTR_ERR(qfprom_cdata);
+
+	mode = tsens_read_calibration_legacy(priv, &tsens_ipq5018_nvmem,
+					     p1, p2,
+					     qfprom_cdata, NULL);
+
+	fixup_ipq5018_points(mode, p1, p2);
+	compute_intercept_slope(priv, p1, p2, mode);
+	kfree(qfprom_cdata);
+
+	return 0;
+}
+
 static int calibrate_v1(struct tsens_priv *priv)
 {
 	u32 p1[10], p2[10];
@@ -79,6 +132,18 @@ static struct tsens_features tsens_v1_feat = {
 	.trip_max_temp	= 120000,
 };
 
+static struct tsens_features tsens_v1_ipq5018_feat = {
+	.ver_major	= VER_1_X,
+	.crit_int	= 0,
+	.combo_int	= 0,
+	.adc		= 1,
+	.srot_split	= 1,
+	.max_sensors	= 11,
+	.trip_min_temp	= -40000,
+	.trip_max_temp	= 120000,
+	.no_early_init	= 1,
+};
+
 static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
 	/* ----- SROT ------ */
 	/* VERSION */
@@ -150,6 +215,43 @@ static int __init init_8956(struct tsens_priv *priv) {
 	return init_common(priv);
 }
 
+static int init_ipq5018(struct tsens_priv *priv)
+{
+	int ret;
+	u32 mask;
+
+	init_common(priv);
+	if (!priv->tm_map)
+		return -ENODEV;
+
+	ret = regmap_field_write(priv->rf[TSENS_SW_RST], 1);
+	if (ret) {
+		dev_err(priv->dev, "Reset failed\n");
+		return ret;
+	}
+
+	mask = GENMASK(10, 0);
+	ret = regmap_field_update_bits(priv->rf[SENSOR_EN], mask, mask);
+	if (ret) {
+		dev_err(priv->dev, "Sensor Enable failed\n");
+		return ret;
+	}
+
+	ret = regmap_field_write(priv->rf[TSENS_EN], 1);
+	if (ret) {
+		dev_err(priv->dev, "Enable failed\n");
+		return ret;
+	}
+
+	ret = regmap_field_write(priv->rf[TSENS_SW_RST], 0);
+	if (ret) {
+		dev_err(priv->dev, "Reset failed\n");
+		return ret;
+	}
+
+	return 0;
+}
+
 static const struct tsens_ops ops_generic_v1 = {
 	.init		= init_common,
 	.calibrate	= calibrate_v1,
@@ -187,3 +289,16 @@ struct tsens_plat_data data_8976 = {
 	.feat		= &tsens_v1_feat,
 	.fields		= tsens_v1_regfields,
 };
+
+const struct tsens_ops ops_ipq5018 = {
+	.init		= init_ipq5018,
+	.calibrate	= calibrate_ipq5018,
+	.get_temp	= get_temp_tsens_valid,
+};
+
+struct tsens_plat_data data_ipq5018 = {
+	.num_sensors	= 5,
+	.ops		= &ops_ipq5018,
+	.feat		= &tsens_v1_ipq5018_feat,
+	.fields		= tsens_v1_regfields,
+};
diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h
index fb73e3dd0de9..5f0bdbeedf90 100644
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -645,7 +645,7 @@ extern struct tsens_plat_data data_8960;
 extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, data_8974, data_9607;
 
 /* TSENS v1 targets */
-extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956;
+extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956, data_ipq5018;
 
 /* TSENS v2 targets */
 extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;
-- 
2.34.1

Re: [PATCH 3/7] thermal/drivers/qcom/tsens: Add support for IPQ5018 tsens

[Krzysztof Kozlowski]

On 28/08/2023 21:18, Sricharan Ramabadhran wrote:
> IPQ5018 has tsens IP V1.0, 4 sensors and 1 interrupt.
> The soc does not have a RPM, hence tsens has to be reset and
> enabled in the driver init. Adding the driver support for same.
> 
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>

Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching.

Best regards,
Krzysztof

Re: [PATCH 3/7] thermal/drivers/qcom/tsens: Add support for IPQ5018 tsens

[Sricharan Ramabadhran]

On 8/29/2023 1:03 AM, Krzysztof Kozlowski wrote:
> On 28/08/2023 21:18, Sricharan Ramabadhran wrote:
>> IPQ5018 has tsens IP V1.0, 4 sensors and 1 interrupt.
>> The soc does not have a RPM, hence tsens has to be reset and
>> enabled in the driver init. Adding the driver support for same.
>>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> 
> Please use subject prefixes matching the subsystem. You can get them for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
> your patch is touching.
> 

  ok, will fix.

Regards,
  Sricharan

Re: [PATCH 3/7] thermal/drivers/qcom/tsens: Add support for IPQ5018 tsens

[Dmitry Baryshkov]

On Mon, 28 Aug 2023 at 22:20, Sricharan Ramabadhran
<quic_srichara@quicinc.com> wrote:
>
> IPQ5018 has tsens IP V1.0, 4 sensors and 1 interrupt.
> The soc does not have a RPM, hence tsens has to be reset and
> enabled in the driver init. Adding the driver support for same.
>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---
>  drivers/thermal/qcom/tsens-v1.c | 115 ++++++++++++++++++++++++++++++++
>  drivers/thermal/qcom/tsens.h    |   2 +-
>  2 files changed, 116 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c
> index dc1c4ae2d8b0..a74dae69408b 100644
> --- a/drivers/thermal/qcom/tsens-v1.c
> +++ b/drivers/thermal/qcom/tsens-v1.c
> @@ -42,6 +42,59 @@ static struct tsens_legacy_calibration_format tsens_qcs404_nvmem = {
>         },
>  };
>
> +struct tsens_legacy_calibration_format tsens_ipq5018_nvmem = {
> +       .base_len = 8,
> +       .base_shift = 2,
> +       .sp_len = 6,
> +       .mode = { 0, 8 },
> +       .invalid = { 0, 2 },
> +       .base = { { 0, 11 }, { 0, 19 } },
> +       .sp = {
> +               { { 0, 27 },  { 1, 1 } },
> +               { { 1, 7 },  { 1, 13 } },
> +               { { 1, 19 },  { 1, 25 } },
> +               { { 1, 31 },  { 2, 5 } },
> +               { { 2, 11 },  { 3, 0 } },
> +       },
> +};
> +
> +static void fixup_ipq5018_points(int mode, u32 *p1, u32 *p2)
> +{
> +       if (mode == NO_PT_CALIB) {
> +               p1[0] = 403;
> +               p2[0] = 688;
> +               p1[1] = 390;
> +               p2[1] = 674;
> +               p1[2] = 341;
> +               p2[2] = 635;
> +               p1[3] = 387;
> +               p2[3] = 673;
> +               p1[4] = 347;
> +               p2[4] = 639;
> +       }
> +}
> +
> +static int calibrate_ipq5018(struct tsens_priv *priv)
> +{
> +       u32 p1[10], p2[10];
> +       u32 *qfprom_cdata;
> +       int mode;
> +
> +       qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib");
> +       if (IS_ERR(qfprom_cdata))
> +               return PTR_ERR(qfprom_cdata);
> +
> +       mode = tsens_read_calibration_legacy(priv, &tsens_ipq5018_nvmem,
> +                                            p1, p2,
> +                                            qfprom_cdata, NULL);

No, this should be used only in _legacy_ cases. Please use
tsens_calibrate_common() / tsens_calibrate_nvmem() / etc.

> +
> +       fixup_ipq5018_points(mode, p1, p2);
> +       compute_intercept_slope(priv, p1, p2, mode);
> +       kfree(qfprom_cdata);
> +
> +       return 0;
> +}
> +
>  static int calibrate_v1(struct tsens_priv *priv)
>  {
>         u32 p1[10], p2[10];
> @@ -79,6 +132,18 @@ static struct tsens_features tsens_v1_feat = {
>         .trip_max_temp  = 120000,
>  };
>
> +static struct tsens_features tsens_v1_ipq5018_feat = {
> +       .ver_major      = VER_1_X,
> +       .crit_int       = 0,
> +       .combo_int      = 0,
> +       .adc            = 1,
> +       .srot_split     = 1,
> +       .max_sensors    = 11,
> +       .trip_min_temp  = -40000,
> +       .trip_max_temp  = 120000,
> +       .no_early_init  = 1,
> +};
> +
>  static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
>         /* ----- SROT ------ */
>         /* VERSION */
> @@ -150,6 +215,43 @@ static int __init init_8956(struct tsens_priv *priv) {
>         return init_common(priv);
>  }
>
> +static int init_ipq5018(struct tsens_priv *priv)
> +{
> +       int ret;
> +       u32 mask;
> +
> +       init_common(priv);
> +       if (!priv->tm_map)
> +               return -ENODEV;
> +
> +       ret = regmap_field_write(priv->rf[TSENS_SW_RST], 1);
> +       if (ret) {
> +               dev_err(priv->dev, "Reset failed\n");
> +               return ret;
> +       }
> +
> +       mask = GENMASK(10, 0);

#define this, then inline the variable. Or extract this codepiece into
generic function which uses num_sensors to calculate the mask

> +       ret = regmap_field_update_bits(priv->rf[SENSOR_EN], mask, mask);
> +       if (ret) {
> +               dev_err(priv->dev, "Sensor Enable failed\n");
> +               return ret;
> +       }
> +
> +       ret = regmap_field_write(priv->rf[TSENS_EN], 1);
> +       if (ret) {
> +               dev_err(priv->dev, "Enable failed\n");
> +               return ret;
> +       }
> +
> +       ret = regmap_field_write(priv->rf[TSENS_SW_RST], 0);
> +       if (ret) {
> +               dev_err(priv->dev, "Reset failed\n");

This error message is useless. You can not determine if it comes from
this error or from setting the reset bit.

> +               return ret;
> +       }
> +
> +       return 0;
> +}
> +
>  static const struct tsens_ops ops_generic_v1 = {
>         .init           = init_common,
>         .calibrate      = calibrate_v1,
> @@ -187,3 +289,16 @@ struct tsens_plat_data data_8976 = {
>         .feat           = &tsens_v1_feat,
>         .fields         = tsens_v1_regfields,
>  };
> +
> +const struct tsens_ops ops_ipq5018 = {
> +       .init           = init_ipq5018,
> +       .calibrate      = calibrate_ipq5018,
> +       .get_temp       = get_temp_tsens_valid,
> +};
> +
> +struct tsens_plat_data data_ipq5018 = {
> +       .num_sensors    = 5,
> +       .ops            = &ops_ipq5018,
> +       .feat           = &tsens_v1_ipq5018_feat,
> +       .fields         = tsens_v1_regfields,
> +};
> diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h
> index fb73e3dd0de9..5f0bdbeedf90 100644
> --- a/drivers/thermal/qcom/tsens.h
> +++ b/drivers/thermal/qcom/tsens.h
> @@ -645,7 +645,7 @@ extern struct tsens_plat_data data_8960;
>  extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, data_8974, data_9607;
>
>  /* TSENS v1 targets */
> -extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956;
> +extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956, data_ipq5018;
>
>  /* TSENS v2 targets */
>  extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;
> --
> 2.34.1
>


-- 
With best wishes
Dmitry

Re: [PATCH 3/7] thermal/drivers/qcom/tsens: Add support for IPQ5018 tsens

[Sricharan Ramabadhran]

<..>

>> +{
>> +       u32 p1[10], p2[10];
>> +       u32 *qfprom_cdata;
>> +       int mode;
>> +
>> +       qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib");
>> +       if (IS_ERR(qfprom_cdata))
>> +               return PTR_ERR(qfprom_cdata);
>> +
>> +       mode = tsens_read_calibration_legacy(priv, &tsens_ipq5018_nvmem,
>> +                                            p1, p2,
>> +                                            qfprom_cdata, NULL);
> 
> No, this should be used only in _legacy_ cases. Please use
> tsens_calibrate_common() / tsens_calibrate_nvmem() / etc.
> 

  ok.

>> +
>> +       fixup_ipq5018_points(mode, p1, p2);
>> +       compute_intercept_slope(priv, p1, p2, mode);
>> +       kfree(qfprom_cdata);
>> +
>> +       return 0;
>> +}
>> +
>>   static int calibrate_v1(struct tsens_priv *priv)
>>   {
>>          u32 p1[10], p2[10];
>> @@ -79,6 +132,18 @@ static struct tsens_features tsens_v1_feat = {
>>          .trip_max_temp  = 120000,
>>   };
>>
>> +static struct tsens_features tsens_v1_ipq5018_feat = {
>> +       .ver_major      = VER_1_X,
>> +       .crit_int       = 0,
>> +       .combo_int      = 0,
>> +       .adc            = 1,
>> +       .srot_split     = 1,
>> +       .max_sensors    = 11,
>> +       .trip_min_temp  = -40000,
>> +       .trip_max_temp  = 120000,
>> +       .no_early_init  = 1,
>> +};
>> +
>>   static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
>>          /* ----- SROT ------ */
>>          /* VERSION */
>> @@ -150,6 +215,43 @@ static int __init init_8956(struct tsens_priv *priv) {
>>          return init_common(priv);
>>   }
>>
>> +static int init_ipq5018(struct tsens_priv *priv)
>> +{
>> +       int ret;
>> +       u32 mask;
>> +
>> +       init_common(priv);
>> +       if (!priv->tm_map)
>> +               return -ENODEV;
>> +
>> +       ret = regmap_field_write(priv->rf[TSENS_SW_RST], 1);
>> +       if (ret) {
>> +               dev_err(priv->dev, "Reset failed\n");
>> +               return ret;
>> +       }
>> +
>> +       mask = GENMASK(10, 0);
> 
> #define this, then inline the variable. Or extract this codepiece into
> generic function which uses num_sensors to calculate the mask
> 

  ok.

>> +       ret = regmap_field_update_bits(priv->rf[SENSOR_EN], mask, mask);
>> +       if (ret) {
>> +               dev_err(priv->dev, "Sensor Enable failed\n");
>> +               return ret;
>> +       }
>> +
>> +       ret = regmap_field_write(priv->rf[TSENS_EN], 1);
>> +       if (ret) {
>> +               dev_err(priv->dev, "Enable failed\n");
>> +               return ret;
>> +       }
>> +
>> +       ret = regmap_field_write(priv->rf[TSENS_SW_RST], 0);
>> +       if (ret) {
>> +               dev_err(priv->dev, "Reset failed\n");
> 
> This error message is useless. You can not determine if it comes from
> this error or from setting the reset bit.
> 

  ok, will drop it.

Regards,
  Sricharan

[PATCH 4/7] thermal/drivers/qcom: Add IPQ5018 compatible

[Sricharan Ramabadhran]

IPQ5018 has tsens V1.0 IP with 4 sensors and 1 interrupt.

Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
 drivers/thermal/qcom/tsens.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c
index f39495b61952..a24eb88b3444 100644
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -1101,6 +1101,9 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, tsens_suspend, tsens_resume);
 
 static const struct of_device_id tsens_table[] = {
 	{
+		.compatible = "qcom,ipq5018-tsens",
+		.data = &data_ipq5018,
+	}, {
 		.compatible = "qcom,ipq8064-tsens",
 		.data = &data_8960,
 	}, {
-- 
2.34.1

Re: [PATCH 4/7] thermal/drivers/qcom: Add IPQ5018 compatible

[Krzysztof Kozlowski]

On 28/08/2023 21:18, Sricharan Ramabadhran wrote:
> IPQ5018 has tsens V1.0 IP with 4 sensors and 1 interrupt.
> 
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---
>  drivers/thermal/qcom/tsens.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c
> index f39495b61952..a24eb88b3444 100644
> --- a/drivers/thermal/qcom/tsens.c
> +++ b/drivers/thermal/qcom/tsens.c
> @@ -1101,6 +1101,9 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, tsens_suspend, tsens_resume);
>  
>  static const struct of_device_id tsens_table[] = {
>  	{
> +		.compatible = "qcom,ipq5018-tsens",
> +		.data = &data_ipq5018,
> +	}, {

This patch does not make sense on its own. It must be squashed. You
already brought the IPQ5018 in previous patch.

Best regards,
Krzysztof

Re: [PATCH 4/7] thermal/drivers/qcom: Add IPQ5018 compatible

[Sricharan Ramabadhran]

On 8/29/2023 1:03 AM, Krzysztof Kozlowski wrote:
> On 28/08/2023 21:18, Sricharan Ramabadhran wrote:
>> IPQ5018 has tsens V1.0 IP with 4 sensors and 1 interrupt.
>>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> ---
>>   drivers/thermal/qcom/tsens.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c
>> index f39495b61952..a24eb88b3444 100644
>> --- a/drivers/thermal/qcom/tsens.c
>> +++ b/drivers/thermal/qcom/tsens.c
>> @@ -1101,6 +1101,9 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, tsens_suspend, tsens_resume);
>>   
>>   static const struct of_device_id tsens_table[] = {
>>   	{
>> +		.compatible = "qcom,ipq5018-tsens",
>> +		.data = &data_ipq5018,
>> +	}, {
> 
> This patch does not make sense on its own. It must be squashed. You
> already brought the IPQ5018 in previous patch.
> 

  ok, will squash.

Regards,
  Sricharan

[PATCH 5/7] dt-bindings: nvmem: Add compatible for IPQ5018

[Sricharan Ramabadhran]

Document the QFPROM on IPQ5018.

Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
 Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
index 8740938c32eb..e26621ac1ca7 100644
--- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
+++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
@@ -18,6 +18,7 @@ properties:
       - enum:
           - qcom,apq8064-qfprom
           - qcom,apq8084-qfprom
+          - qcom,ipq5018-qfprom
           - qcom,ipq5332-qfprom
           - qcom,ipq6018-qfprom
           - qcom,ipq8064-qfprom
-- 
2.34.1

Re: [PATCH 5/7] dt-bindings: nvmem: Add compatible for IPQ5018

[Krzysztof Kozlowski]

On 28/08/2023 21:18, Sricharan Ramabadhran wrote:
> Document the QFPROM on IPQ5018.
> 
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---

I suggest you to send independent patches from different subsystem in
their own patchsets. You make it easier for the maintainer, thus help
yourself as well (usually).

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


---

This is an automated instruction, just in case, because many review tags
are being ignored. If you know the process, you can skip it (please do
not feel offended by me posting it here - no bad intentions intended).
If you do not know the process, here is a short explanation:

Please add Acked-by/Reviewed-by/Tested-by tags when posting new
versions, under or above your Signed-off-by tag. Tag is "received", when
provided in a message replied to you on the mailing list. Tools like b4
can help here. However, there's no need to repost patches *only* to add
the tags. The upstream maintainer will do that for tags received on the
version they apply.

https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577

Best regards,
Krzysztof

[PATCH 6/7] arm64: dts: qcom: ipq5018: Add tsens node

[Sricharan Ramabadhran]

IPQ5018 has tsens V1.0 IP with 4 sensors.
There is no RPM, so tsens has to manually enabled.
Adding the tsens and nvmem node.

Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 9f13d2dcdfd5..277b3cfc7f72 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -93,6 +93,29 @@ soc: soc@0 {
 		#size-cells = <1>;
 		ranges = <0 0 0 0xffffffff>;
 
+		qfprom_nvmem: qfprom_nvmem@a0000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
+			reg = <0xa0000 0x1000>;
+
+			tsens_calib: calib@248 {
+				reg = <0x248 0x10>;
+			};
+		};
+
+		tsens: thermal-sensor@4a9000 {
+			compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1";
+			reg = <0x4a9000 0x1000>, /* TM */
+			      <0x4a8000 0x1000>; /* SORT */
+			nvmem-cells = <&tsens_calib>;
+			nvmem-cell-names = "calib";
+			interrupts = <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "uplow";
+			#qcom,sensors = <5>;
+			#thermal-sensor-cells = <1>;
+		};
+
 		tlmm: pinctrl@1000000 {
 			compatible = "qcom,ipq5018-tlmm";
 			reg = <0x01000000 0x300000>;
-- 
2.34.1

Re: [PATCH 6/7] arm64: dts: qcom: ipq5018: Add tsens node

[Krzysztof Kozlowski]

On 28/08/2023 21:18, Sricharan Ramabadhran wrote:
> IPQ5018 has tsens V1.0 IP with 4 sensors.
> There is no RPM, so tsens has to manually enabled.
> Adding the tsens and nvmem node.
> 
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq5018.dtsi | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 9f13d2dcdfd5..277b3cfc7f72 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -93,6 +93,29 @@ soc: soc@0 {
>  		#size-cells = <1>;
>  		ranges = <0 0 0 0xffffffff>;
>  
> +		qfprom_nvmem: qfprom_nvmem@a0000 {

Nope. Come on, where do you see such node naming. Please do not send
code from downstream, but work on upstream sources. Open other most
recent DTS, take a look how it is done and try to do something similar.

> +			#address-cells = <1>;
> +			#size-cells = <1>;

compatible is always the first property. Then reg.

> +			compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
> +			reg = <0xa0000 0x1000>;
> +
> +			tsens_calib: calib@248 {
> +				reg = <0x248 0x10>;
> +			};
> +		};
> +

Best regards,
Krzysztof

Re: [PATCH 6/7] arm64: dts: qcom: ipq5018: Add tsens node

[Sricharan Ramabadhran]

On 8/29/2023 12:55 AM, Krzysztof Kozlowski wrote:
> On 28/08/2023 21:18, Sricharan Ramabadhran wrote:
>> IPQ5018 has tsens V1.0 IP with 4 sensors.
>> There is no RPM, so tsens has to manually enabled.
>> Adding the tsens and nvmem node.
>>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq5018.dtsi | 23 +++++++++++++++++++++++
>>   1 file changed, 23 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> index 9f13d2dcdfd5..277b3cfc7f72 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> @@ -93,6 +93,29 @@ soc: soc@0 {
>>   		#size-cells = <1>;
>>   		ranges = <0 0 0 0xffffffff>;
>>   
>> +		qfprom_nvmem: qfprom_nvmem@a0000 {
> 
> Nope. Come on, where do you see such node naming. Please do not send
> code from downstream, but work on upstream sources. Open other most
> recent DTS, take a look how it is done and try to do something similar.
> 

  sure, will fix it up.
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
> 
> compatible is always the first property. Then reg.

  ok, will fix.

Regards,
  Sricharan

Re: [PATCH 6/7] arm64: dts: qcom: ipq5018: Add tsens node

[Dmitry Baryshkov]

On Mon, 28 Aug 2023 at 22:20, Sricharan Ramabadhran
<quic_srichara@quicinc.com> wrote:
>
> IPQ5018 has tsens V1.0 IP with 4 sensors.
> There is no RPM, so tsens has to manually enabled.
> Adding the tsens and nvmem node.
>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq5018.dtsi | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 9f13d2dcdfd5..277b3cfc7f72 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -93,6 +93,29 @@ soc: soc@0 {
>                 #size-cells = <1>;
>                 ranges = <0 0 0 0xffffffff>;
>
> +               qfprom_nvmem: qfprom_nvmem@a0000 {
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
> +                       reg = <0xa0000 0x1000>;
> +
> +                       tsens_calib: calib@248 {
> +                               reg = <0x248 0x10>;
> +                       };

NAK. Please define per-sensor fields here.

> +               };
> +
> +               tsens: thermal-sensor@4a9000 {
> +                       compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1";
> +                       reg = <0x4a9000 0x1000>, /* TM */
> +                             <0x4a8000 0x1000>; /* SORT */
> +                       nvmem-cells = <&tsens_calib>;
> +                       nvmem-cell-names = "calib";
> +                       interrupts = <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "uplow";
> +                       #qcom,sensors = <5>;
> +                       #thermal-sensor-cells = <1>;
> +               };
> +
>                 tlmm: pinctrl@1000000 {
>                         compatible = "qcom,ipq5018-tlmm";
>                         reg = <0x01000000 0x300000>;
> --
> 2.34.1
>


-- 
With best wishes
Dmitry

[PATCH 7/7] arm64: dts: qcom: ipq5018: Add thermal zones

[Sricharan Ramabadhran]

IPQ5018 has 4 thermal sensors (zones). With the
critical temperature being 120'C and action is to reboot.
Adding all the 4 zones here.

Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 58 +++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 277b3cfc7f72..8ab82a6e8594 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -263,6 +263,64 @@ frame@b128000 {
 		};
 	};
 
+	thermal-zones {
+		ubi32-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens 1>;
+
+			trips {
+				ubi32-critical {
+					temperature = <120000>;
+					hysteresis = <2>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens 2>;
+
+			trips {
+				cpu-critical {
+					temperature = <120000>;
+					hysteresis = <2>;
+					type = "critical";
+				};
+			};
+		};
+
+		top-glue-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens 3>;
+
+			trips {
+				top_glue-critical {
+					temperature = <120000>;
+					hysteresis = <2>;
+					type = "critical";
+				};
+			};
+		};
+
+		gephy-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens 4>;
+
+			trips {
+				gephy-critical {
+					temperature = <120000>;
+					hysteresis = <2>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-- 
2.34.1

Re: [PATCH 7/7] arm64: dts: qcom: ipq5018: Add thermal zones

[Krzysztof Kozlowski]

On 28/08/2023 21:18, Sricharan Ramabadhran wrote:
> IPQ5018 has 4 thermal sensors (zones). With the
> critical temperature being 120'C and action is to reboot.
> Adding all the 4 zones here.
> 

Not much benefit of having it separate patch... You added the
thermal-sensor for this purpose.

Best regards,
Krzysztof

Re: [PATCH 7/7] arm64: dts: qcom: ipq5018: Add thermal zones

[Sricharan Ramabadhran]

On 8/29/2023 1:04 AM, Krzysztof Kozlowski wrote:
> On 28/08/2023 21:18, Sricharan Ramabadhran wrote:
>> IPQ5018 has 4 thermal sensors (zones). With the
>> critical temperature being 120'C and action is to reboot.
>> Adding all the 4 zones here.
>>
> 
> Not much benefit of having it separate patch... You added the
> thermal-sensor for this purpose.

  ok, will squash.

Regards,
  Sricharan