Re: [PATCH v4 net-next 5/5] net: pcs: pcs-mtk-lynxi: deprecate "mediatek,pnswap"

Frank Wunderlich
2026-03-30T17:52:35Z

Hi Vladimir

Thanks for the patch and sorry for my delay...i was away this weekend so i was not able to test.

traffic works again (but there is only read now) and this is the result of your debug prints:

root@bpi-r3:~# dmesg | grep SGMSYS_QPHY_WRAP_CTRL
[ 2.706963] SGMSYS_QPHY_WRAP_CTRL = 0x501, intending to write 0x500
[ 9.134081] SGMSYS_QPHY_WRAP_CTRL = 0x500, intending to write 0x500

R3/mt7986 has 2 MAC, and switch is on the first, so value will change, not sure why this is different.

i have not found SGMSYS_QPHY_WRAP_CTRL or something related with polarity in ethernet/mac-
(drivers/net/ethernet/mediatek/mtk_eth_soc.c) or switch-driver (drivers/net/dsa/mt7530{,-mdio}.c)
in case they manipulate this register too (of course they should not). Also looked into the pcs-handling
in both drivers, but see nothing related to polarity. And looked for possible duplicate register const
definition (other name for 0xec).

regards Frank

Am 26. März 2026 um 22:54 schrieb "Vladimir Oltean" <vladimir.oltean@nxp.com>:
>
> Hi Frank,
>
> On Tue, Mar 24, 2026 at 06:36:44AM +0000, Frank Wunderlich wrote:
>
> >
> > Hi,
> >
> > looks like this patch breaks BPI-R3 serdes between mt7986 SoC and mt7531 switch in 7.0 (6.19 is ok).
> > in ethtool i see only tx on mac but no rx. if i revert this patch i can ping through dsa-ports again.
> >
> > i did not completely understanding the code with the default-pol as it is now splitted between rx and tx.
> >
> > mt7986 and this board does not have mediatek,pnswap set, so the final regmap_update_bits writes val=0,
> > before there was only write to this register on invert mode...but i guess this should not break. Maybe some
> > kind of timing issue between mac and switch?
> >
> > maybe reverting this patch skips changes made here:
> > bde1ae2d52ab 2026-01-19 net: pcs: pcs-mtk-lynxi: pass SGMIISYS OF node to PCS
> >
> > I resend as last try was sending as html (option "always send as text" in webmailer seems to be ignored
> > somehow, had to choose "unformatted" in this response too).
> >
> > regards Frank
> >
> Sorry for the delay.
>
> If writing val=0 breaks the link, I'm curious
> (a) whether it still breaks if we don't write anything at all
> (b) what was the register value originally
>
> Could you please test the patch below and let me know what it prints,
> and whether traffic passes with it applied?
>
> -- >8 --
> diff --git a/drivers/net/pcs/pcs-mtk-lynxi.c b/drivers/net/pcs/pcs-mtk-lynxi.c
> index c12f8087af9b..5c5f45b93b82 100644
> --- a/drivers/net/pcs/pcs-mtk-lynxi.c
> +++ b/drivers/net/pcs/pcs-mtk-lynxi.c
> @@ -126,7 +126,7 @@ static int mtk_pcs_config_polarity(struct mtk_pcs_lynxi *mpcs,
> {
> struct fwnode_handle *fwnode = mpcs->fwnode, *pcs_fwnode;
> unsigned int pol, default_pol = PHY_POL_NORMAL;
> - unsigned int val = 0;
> + unsigned int val = 0, tmp;
> int ret;
>
> if (fwnode_property_read_bool(fwnode, "mediatek,pnswap"))
> @@ -153,8 +153,14 @@ static int mtk_pcs_config_polarity(struct mtk_pcs_lynxi *mpcs,
> if (pol == PHY_POL_INVERT)
> val |= SGMII_PN_SWAP_TX;
>
> - return regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
> - SGMII_PN_SWAP_RX | SGMII_PN_SWAP_TX, val);
> + ret = regmap_read(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL, &tmp);
> + if (ret)
> + return ret;
> +
> + pr_err("SGMSYS_QPHY_WRAP_CTRL = 0x%x, intending to write 0x%lx\n",
> + tmp, (tmp & ~(SGMII_PN_SWAP_RX | SGMII_PN_SWAP_TX)) | val);
> +
> + return 0;
> }
>
> static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
> -- >8 --
>

regards Frank