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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id q23-20020aa7da97000000b0042617ba6380sm1024491eds.10.2022.04.28.00.18.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Apr 2022 00:18:31 -0700 (PDT) Message-ID: Date: Thu, 28 Apr 2022 09:18:30 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH V4 12/15] dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8192/MT8195 Content-Language: en-US To: Rex-BC Chen , mturquette@baylibre.com, sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: p.zabel@pengutronix.de, angelogioacchino.delregno@collabora.com, chun-jie.chen@mediatek.com, wenst@chromium.org, runyang.chen@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> <20220427030950.23395-13-rex-bc.chen@mediatek.com> From: Krzysztof Kozlowski In-Reply-To: <20220427030950.23395-13-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 27/04/2022 05:09, Rex-BC Chen wrote: > - To support reset of infra_ao, add the bit definition of > thermal/PCIe/SVS for MT8192. > - To support reset of infra_ao, add the bit definition of > thermal/SVS for MT8195. > - Add the driver comment to separate the reset index for > TOPRGU and INFRA. > > Signed-off-by: Rex-BC Chen > --- > include/dt-bindings/reset/mt8192-resets.h | 8 ++++++++ > include/dt-bindings/reset/mt8195-resets.h | 6 ++++++ > 2 files changed, 14 insertions(+) > > diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h > index be9a7ca245b9..ee0ca02a39bf 100644 > --- a/include/dt-bindings/reset/mt8192-resets.h > +++ b/include/dt-bindings/reset/mt8192-resets.h > @@ -7,6 +7,7 @@ > #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 > #define _DT_BINDINGS_RESET_CONTROLLER_MT8192 > > +/* TOPRGU resets */ > #define MT8192_TOPRGU_MM_SW_RST 1 > #define MT8192_TOPRGU_MFG_SW_RST 2 > #define MT8192_TOPRGU_VENC_SW_RST 3 > @@ -27,4 +28,11 @@ > > #define MT8192_TOPRGU_SW_RST_NUM 23 > > +/* INFRA resets */ > +#define MT8192_INFRA_THERMAL_CTRL_RST 0 > +#define MT8192_INFRA_PEXTP_PHY_RST 79 > +#define MT8192_INFRA_PTP_RST 101 > +#define MT8192_INFRA_RST4_PCIE_TOP 129 > +#define MT8192_INFRA_THERMAL_CTRL_MCU_RST 140 This is still wrong. I gave you exactly what has to be used: 0 1 2 ... It's a decimal number incremented by one. > + > #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ > diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h > index a26bccc8b957..a3226f40779c 100644 > --- a/include/dt-bindings/reset/mt8195-resets.h > +++ b/include/dt-bindings/reset/mt8195-resets.h > @@ -7,6 +7,7 @@ > #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 > #define _DT_BINDINGS_RESET_CONTROLLER_MT8195 > > +/* TOPRGU resets */ > #define MT8195_TOPRGU_CONN_MCU_SW_RST 0 > #define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 > #define MT8195_TOPRGU_APU_SW_RST 2 > @@ -26,4 +27,9 @@ > > #define MT8195_TOPRGU_SW_RST_NUM 16 > > +/* INFRA resets */ > +#define MT8195_INFRA_THERMAL_AP_RST 0 > +#define MT8195_INFRA_PTP_RST 101 > +#define MT8195_INFRA_THERMAL_MCU_RST 138 Same issue. Best regards, Krzysztof