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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH 2/9] riscv: dts: starfive: jh7110: add dc&hdmi controller node Content-Language: en-US To: Keith Zhao , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org Cc: David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Paul Walmsley , Palmer Dabbelt , Albert Ou , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Philipp Zabel , Sumit Semwal , christian.koenig@amd.com, Bjorn Andersson , Heiko Stuebner , Shawn Guo , Jagan Teki , Chris Morgan , Jack Zhu , Shengyang Chen , Changhuang Liang References: <20230602074043.33872-1-keith.zhao@starfivetech.com> <20230602074043.33872-3-keith.zhao@starfivetech.com> From: Krzysztof Kozlowski In-Reply-To: <20230602074043.33872-3-keith.zhao@starfivetech.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 02/06/2023 09:40, Keith Zhao wrote: > Add the dc controller and hdmi node for the Starfive JH7110 SoC. > > Signed-off-by: Keith Zhao > --- > .../jh7110-starfive-visionfive-2.dtsi | 87 +++++++++++++++++++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 46 ++++++++++ > 2 files changed, 133 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index 1155b97b593d..8dc6c8a15c59 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -31,6 +31,21 @@ memory@40000000 { > reg = <0x0 0x40000000 0x1 0x0>; > }; > > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + linux,cma { > + compatible = "shared-dma-pool"; > + reusable; > + size = <0x0 0x20000000>; > + alignment = <0x0 0x1000>; > + alloc-ranges = <0x0 0x80000000 0x0 0x20000000>; > + linux,cma-default; > + }; > + }; > + > gpio-restart { > compatible = "gpio-restart"; > gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>; > @@ -214,6 +229,41 @@ GPOEN_DISABLE, > slew-rate = <0>; > }; > }; > + > + hdmi_pins: hdmi-0 { > + hdmi-scl-pins { > + pinmux = + GPOEN_SYS_HDMI_DDC_SCL, > + GPI_SYS_HDMI_DDC_SCL)>; > + input-enable; > + bias-pull-up; > + }; > + > + hdmi-sda-pins { > + pinmux = + GPOEN_SYS_HDMI_DDC_SDA, > + GPI_SYS_HDMI_DDC_SDA)>; > + input-enable; > + bias-pull-up; > + }; > + > + hdmi-cec-pins { > + pinmux = + GPOEN_SYS_HDMI_CEC_SDA, > + GPI_SYS_HDMI_CEC_SDA)>; > + input-enable; > + bias-pull-up; > + }; > + > + hdmi-hpd-pins { > + pinmux = + GPOEN_ENABLE, > + GPI_SYS_HDMI_HPD)>; > + input-enable; > + bias-disable; /* external pull-up */ > + }; > + }; > + > }; > > &uart0 { > @@ -221,3 +271,40 @@ &uart0 { > pinctrl-0 = <&uart0_pins>; > status = "okay"; > }; > + > +&voutcrg { > + status = "okay"; > +}; > + > +&display { > + status = "okay"; > +}; > + > +&hdmi { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&hdmi_pins>; > + > + hdmi_in: port { > + #address-cells = <1>; > + #size-cells = <0>; > + hdmi_input: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&dc_out_dpi0>; This does not make any sense. You wrote in bindings that this is display output, but you call it HDMI input. If this is input, where is your output? > + }; > + }; > +}; > + > +&dc8200 { > + status = "okay"; > + > + dc_out: port { > + #address-cells = <1>; > + #size-cells = <0>; > + dc_out_dpi0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&hdmi_input>; > + }; > + Stray blank line. > + }; > +}; > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index 9acb5fb1716d..66be6e65a066 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -249,6 +249,11 @@ tdm_ext: tdm-ext-clock { > #clock-cells = <0>; > }; > > + display: display-subsystem { > + compatible = "verisilicon,display-subsystem"; Drop fake nodes which do not represent hardware. Instead, DTS and bindings should describe real hardware. > + ports = <&dc_out>; > + }; > + > soc { > compatible = "simple-bus"; > interrupt-parent = <&plic>; > @@ -570,5 +575,46 @@ voutcrg: clock-controller@295c0000 { > #reset-cells = <1>; > power-domains = <&pwrc JH7110_PD_VOUT>; > }; > + > + dc8200: dc8200@29400000 { Node names should be generic. See also explanation and list of examples in DT specification: https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation > + compatible = "verisilicon,dc8200"; > + reg = <0x0 0x29400000 0x0 0x100>, > + <0x0 0x29400800 0x0 0x2000>, > + <0x0 0x295B0000 0x0 0x90>; > + interrupts = <95>; > + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>, > + <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>, > + <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>, > + <&voutcrg JH7110_VOUTCLK_DC8200_AXI>, > + <&voutcrg JH7110_VOUTCLK_DC8200_CORE>, > + <&voutcrg JH7110_VOUTCLK_DC8200_AHB>, > + <&hdmitx0_pixelclk>, > + <&voutcrg JH7110_VOUTCLK_DC8200_PIX>; > + clock-names = "clk_vout_noc_disp", > + "clk_vout_pix0","clk_vout_pix1", Fix alignment > + "clk_vout_axi","clk_vout_core", > + "clk_vout_vout_ahb","hdmitx0_pixel", > + "clk_vout_dc8200"; > + resets = <&voutcrg JH7110_VOUTRST_DC8200_AXI>, > + <&voutcrg JH7110_VOUTRST_DC8200_AHB>, > + <&voutcrg JH7110_VOUTRST_DC8200_CORE>; > + reset-names = "rst_vout_axi","rst_vout_ahb", > + "rst_vout_core"; Fix alignment. Best regards, Krzysztof