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[2003:f6:ef1c:c500:ee59:d953:f148:40ba]) by smtp.gmail.com with ESMTPSA id qy47-20020a17090768af00b00a517995c070sm4143172ejc.33.2024.04.08.01.48.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Apr 2024 01:48:10 -0700 (PDT) Message-ID: Subject: Re: [PATCH v2 11/11] iio: dac: support the ad9739a RF DAC From: Nuno =?ISO-8859-1?Q?S=E1?= To: Jonathan Cameron , Nuno Sa Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Dragos Bogdan , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan Date: Mon, 08 Apr 2024 10:51:43 +0200 In-Reply-To: <20240406174119.38b821ff@jic23-huawei> References: <20240405-iio-backend-axi-dac-v2-0-293bab7d5552@analog.com> <20240405-iio-backend-axi-dac-v2-11-293bab7d5552@analog.com> <20240406174119.38b821ff@jic23-huawei> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Sat, 2024-04-06 at 17:41 +0100, Jonathan Cameron wrote: > On Fri, 5 Apr 2024 17:00:09 +0200 > Nuno Sa wrote: >=20 > > The AD9739A is a 14-bit, 2.5 GSPS high performance RF DACs that are cap= able > > of synthesizing wideband signals from DC up to 3 GHz. > >=20 > > A dual-port, source synchronous, LVDS interface simplifies the digital > > interface with existing FGPA/ASIC technology. On-chip controllers are u= sed > > to manage external and internal clock domain variations over temperatur= e to > > ensure reliable data transfer from the host to the DAC core. > >=20 > > Co-developed-by: Dragos Bogdan > > Signed-off-by: Dragos Bogdan > > Signed-off-by: Nuno Sa >=20 > The only thing I really have remaining questions on is the choice > of chan_spec with altvoltage and voltage channels.=C2=A0 Why does that > split make sense?=C2=A0 It's odd enough that some comments in the code wo= uld > be a good thing to add. >=20 > Jonathan >=20 > > new file mode 100644 > > index 000000000000..9b91d66f826c > > --- /dev/null > > +++ b/drivers/iio/dac/ad9739a.c > > @@ -0,0 +1,454 @@ >=20 > > + > > +static struct iio_chan_spec ad9739a_channels[] =3D { > > + { > > + .type =3D IIO_ALTVOLTAGE, >=20 > So this looks a little unusual. Perhaps some comments on why it > is appropriate to have this channel. >=20 > In reality there is only one channel I think? Yeah, I had this same discussion internally and was also thinking in having= one channel (just ALTVOLTAGE). I ended up doing it as we have done it internall= y so far. The reasoning is that we have two sources of data: ALTVOLTAGE: It's the internally continuous wave the backend can generate. T= hat is in fact alternate voltage. VOLTAGE: Is kind of what I call external source where we assume is just typ= ical DAC data and that typically is VOLTAGE (but for a dac like this, I think it= may very well be, if not most of the time, also alternate - the thing is, we ca= n't know for sure as we should be able to have both) - Nuno S=C3=A1=20