From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37D69C433EF for ; Thu, 31 Mar 2022 10:10:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234509AbiCaKMU (ORCPT ); Thu, 31 Mar 2022 06:12:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233269AbiCaKMS (ORCPT ); Thu, 31 Mar 2022 06:12:18 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B6DD4B841 for ; Thu, 31 Mar 2022 03:10:31 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id h7so40602337lfl.2 for ; Thu, 31 Mar 2022 03:10:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=DkPFTvrQEeskfvBTqfSOajTcre8fVDqFYzIN3B6dTsI=; b=KItC8IMn5rncXU6DjNFWlsw2ttC3GaaAEUbxCnBOR7T/9Tfj6lRHHFcT2drBRA225/ dk71o9m/4VllMnJRSsHw7LpJ9ASmXszD3qY5Zz+5TfhYdsRg38C3XtGxx2w1jGsQWBY8 ih5uzDcudKl79At3nt5SsfB64kDTfNMDqHWXP07DhGCY1vsGKCPn+LukasFPljTlUHJI fP10i7MwzuQBxdQAzpmwtCsOshjAuwnIOjprbAKbJ1Yy6ciMxquv4ewcAaNOedjPDwYA nOxsNYnOLJ6pOXJnjlR2ncJeheVQ923O6vmgq2BTKrYI1rCvcolTwFfgDgtF5Fn0MUui Bdyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=DkPFTvrQEeskfvBTqfSOajTcre8fVDqFYzIN3B6dTsI=; b=EOE7qFETmCFL9GBDckBDwiTbdqtJuWQZlg3igskP8ZZPMOSa96MRjxc6/xlWhY7lHH LqqW0+td6zL27qgh2wgd7XU+EeM3qZNPl9AsfVxgPxtX2nggckPwQOPRIZav0DW98/8o GAcmlJ21x8qV9w4lCDIjNKGHQeDjvUIwzHwc05wxLNzIcwdN8hRpvwKTDIfU4CeTGIR4 9espNakX92+8yj8oj4dVqIw+1ObDILon2iFpn06Qoa+3Q+NJsyxfFGln9NgMnab/kkkS n6f829XS7d7bTk8ftw05Asq7om4kz+qIvcoWVCKwFhZUtfBByFP7NP4Sk0Dw7cYN1vDi pUfw== X-Gm-Message-State: AOAM533a9ZFXNw39d/8W/AWEG4uJINqZlf14+SkQuaNUIxPs1Lvgsxzc EGPoY2AFVv6gzva2+WrW5nx6XA== X-Google-Smtp-Source: ABdhPJwtAJyMy0EoY+rrG6bKX7082NXgD8paVU/49U2dxYES7x6TI8M54x7s0LTqdnwet5PnHMXT9w== X-Received: by 2002:ac2:485b:0:b0:44a:23d5:d4bd with SMTP id 27-20020ac2485b000000b0044a23d5d4bdmr10216994lfy.214.1648721428984; Thu, 31 Mar 2022 03:10:28 -0700 (PDT) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id a26-20020a19fc1a000000b0044ab4920887sm805769lfi.57.2022.03.31.03.10.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 31 Mar 2022 03:10:28 -0700 (PDT) Message-ID: Date: Thu, 31 Mar 2022 13:10:27 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v6 4/8] drm/msm/dp: avoid handling masked interrupts Content-Language: en-GB To: "Sankeerth Billakanti (QUIC)" Cc: "dri-devel@lists.freedesktop.org" , "linux-arm-msm@vger.kernel.org" , "freedreno@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "robdclark@gmail.com" , "seanpaul@chromium.org" , "swboyd@chromium.org" , quic_kalyant , "Abhinav Kumar (QUIC)" , "dianders@chromium.org" , "Kuogee Hsieh (QUIC)" , "bjorn.andersson@linaro.org" , "sean@poorly.run" , "airlied@linux.ie" , "daniel@ffwll.ch" , quic_vproddut , "Aravind Venkateswaran (QUIC)" References: <1648656179-10347-1-git-send-email-quic_sbillaka@quicinc.com> <1648656179-10347-5-git-send-email-quic_sbillaka@quicinc.com> From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 31/03/2022 08:53, Sankeerth Billakanti (QUIC) wrote: > Hi Dmitry, > >> On Wed, 30 Mar 2022 at 19:03, Sankeerth Billakanti >> wrote: >>> >>> The interrupt register will still reflect the connect and disconnect >>> interrupt status without generating an actual HW interrupt. >>> The controller driver should not handle those masked interrupts. >>> >>> Signed-off-by: Sankeerth Billakanti >>> --- >>> drivers/gpu/drm/msm/dp/dp_catalog.c | 5 +++-- >>> 1 file changed, 3 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c >>> b/drivers/gpu/drm/msm/dp/dp_catalog.c >>> index 3c16f95..1809ce2 100644 >>> --- a/drivers/gpu/drm/msm/dp/dp_catalog.c >>> +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c >>> @@ -608,13 +608,14 @@ u32 dp_catalog_hpd_get_intr_status(struct >>> dp_catalog *dp_catalog) { >>> struct dp_catalog_private *catalog = container_of(dp_catalog, >>> struct dp_catalog_private, dp_catalog); >>> - int isr = 0; >>> + int isr, mask; >>> >>> isr = dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); >>> dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK, >>> (isr & DP_DP_HPD_INT_MASK)); >>> + mask = dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK); >>> >>> - return isr; >>> + return isr & (DP_DP_HPD_STATE_STATUS_MASK | mask); >> >> I suspect that the logic is inverted here. Shouldn't it be: >> >> return isr & DP_DP_HPD_STATE_STATUS_MASK & mask; >> >> ? >> > > The value of DP_DP_HPD_STATE_STATUS_MASK is 0xE0000000 and the value of the read > interrupt mask variable could be is 0xF. > > The mask value is indicated via the register, REG_DP_DP_HPD_INT_MASK, bits 3:0. > The HPD status is indicated via a different read-only register REG_DP_DP_HPD_INT_STATUS, bits 31:29. I see. Maybe the following expression would be better? return isr & (mask & ~DP_DP_HPD_INT_MASK); > > isr & DP_DP_HPD_STATE_STATUS_MASK & mask, will return 0 always. > >>> } >>> >>> int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog) >>> -- >>> 2.7.4 >>> >> >> >> -- >> With best wishes >> Dmitry > > Thank you, > Sankeerth -- With best wishes Dmitry