From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 868BE31A07F; Wed, 15 Oct 2025 08:59:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760518769; cv=none; b=VcwNnOXJ0cy/x03LbdOukgtq3D1z+VZbKFVZQwDhmihzMCs3Fk1Ga/ptbW9nm686ty/tO5b8MWOp7C9qZXVZLh4QaUgTCp1lEwbYEuj9gjqHeYKmlaiEtWrp2pj7l4bVoxoY4nt/vdOnwiUVLMriV7Rn3aDTt9Aro9c0YeI0dME= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760518769; c=relaxed/simple; bh=XCOa6UKMhp1ANTY93PkNLWmuW4ZzjeRtQ3m+yYFujDQ=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=pD+0Svu1HFVT9aKxa3rqNmRytfnrkWXqgUAH1K77td4HRLF+Nn7hxLHkQSAwp05wusFosaaWyb2qXKMuXRDwBr/m409pc2DB6/5L7xE0jtkF2JUdu/4JxJXW6yLf8oISAxHgXoi1PSW+g833eXMeWWHz76iRR155hbpjOxjyL94= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=fiHu5AEM; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="fiHu5AEM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1760518763; bh=XCOa6UKMhp1ANTY93PkNLWmuW4ZzjeRtQ3m+yYFujDQ=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=fiHu5AEM86zk+RnqhjIILNMO66Za6N7CHFpcg1o4H5JZ70pcbus27J6Hk7uv1BV0r pdK+20Ruz9ynZp9ZviI7augpG2ZJk2avc1+DiwyC2dYrrzHOPlx3VBod5e/NyNhusR eJJ5DtlBV4KrutK2/E7ckvjnsMMF2U1b/e0vVb4/hSPWUTwGhR03M/S/Tqm7zNB8El 6LQjk/5UswIBswaDAaEZaiO2QflDq36Ibkv6VaSno5ZYSel72NsLp3lwZ/RI/werdw oPT/D6rGLLskHGoFMOAIkn2FKeZZmyL5WGq7/lUjCCRiKFAdxX47tccjXhiBxxmTSJ gBXIwzR7Lg2vg== Received: from [192.168.1.100] (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id CE5B017E12EB; Wed, 15 Oct 2025 10:59:22 +0200 (CEST) Message-ID: Date: Wed, 15 Oct 2025 10:59:22 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 5/5] pmdomain: mediatek: Add support for MFlexGraphics To: Nicolas Frattaroli , Boris Brezillon , Jassi Brar , Chia-I Wu , Chen-Yu Tsai , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-hardening@vger.kernel.org, linux-pm@vger.kernel.org References: <20251015-mt8196-gpufreq-v7-0-0a6435da2080@collabora.com> <20251015-mt8196-gpufreq-v7-5-0a6435da2080@collabora.com> From: AngeloGioacchino Del Regno Content-Language: en-US In-Reply-To: <20251015-mt8196-gpufreq-v7-5-0a6435da2080@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Il 15/10/25 10:50, Nicolas Frattaroli ha scritto: > Various MediaTek SoCs use GPU integration silicon named "MFlexGraphics" > by MediaTek. On the MT8196 and MT6991 SoCs, interacting with this > integration silicon is required to power on the GPU. > > This glue silicon is in the form of an embedded microcontroller running > special-purpose firmware, which autonomously adjusts clocks and > regulators. > > Implement a driver, modelled as a pmdomain driver with a > set_performance_state operation, to support these SoCs. > > The driver also exposes the actual achieved clock rate, as read back > from the MCU, as common clock framework clocks, by acting as a clock > provider as well. > > Signed-off-by: Nicolas Frattaroli Reviewed-by: AngeloGioacchino Del Regno