* [PATCH v2 0/5] Add R8A77980/Condor board support
@ 2018-02-16 18:25 Sergei Shtylyov
[not found] ` <ae31804b-969b-9b20-16d0-50f5dea42f08-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Sergei Shtylyov @ 2018-02-16 18:25 UTC (permalink / raw)
To: Rob Herring, Catalin Marinas, Will Deacon, Simon Horman,
devicetree, linux-renesas-soc
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
Hello!
Here's the set of 11 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20180216-v4.16-rc1' tag. I'm adding the device tree support
for the R8A77980-based Condor board (note that NFS root would only work on
the Condor boards [re]wired for booting from EtherAVB -- we haven't been
able to get the 'sh_eth' driver working in either U-Boot or Linux so far).
The necessary SYS-DMAC, [H]SCIF, and EtherAVB bindings updates have been
posted, the clock driver has been reposted yesterday, and the merged patches
have been dropped from this respin of the series...
[1/5] soc: renesas: rcar-sysc: add R8A77980 support
[2/5] arm64: dts: renesas: r8a77980: add [H]SCIF support
[3/5] arm64: dts: renesas: r8a77980: add EtherAVB support
[4/5] arm64: dts: renesas: initial Condor board device tree
[5/5] arm64: dts: renesas: condor: add EtherAVB support
WBR, Sergei
^ permalink raw reply [flat|nested] 12+ messages in thread[parent not found: <ae31804b-969b-9b20-16d0-50f5dea42f08-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>]
* [PATCH v2 1/5] soc: renesas: rcar-sysc: add R8A77980 support [not found] ` <ae31804b-969b-9b20-16d0-50f5dea42f08-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> @ 2018-02-16 18:28 ` Sergei Shtylyov 2018-02-16 18:30 ` [PATCH v2 2/5] arm64: dts: renesas: r8a77980: add [H]SCIF support Sergei Shtylyov 2018-02-16 18:35 ` [PATCH v2 4/5] arm64: dts: renesas: initial Condor board device tree Sergei Shtylyov 2 siblings, 0 replies; 12+ messages in thread From: Sergei Shtylyov @ 2018-02-16 18:28 UTC (permalink / raw) To: Rob Herring, Simon Horman, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA Cc: Mark Rutland, Magnus Damm Add support for R-Car V3H (R8A77980) SoC power areas to the R-Car SYSC driver. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org> Reviewed-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org> --- Changes in version 2: - fixed the parents of the A2Rn, A2SCn, A2PDn, and A2CN power domains; - added Simon's and Geert's tags. Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt | 1 drivers/soc/renesas/Kconfig | 5 drivers/soc/renesas/Makefile | 1 drivers/soc/renesas/r8a77980-sysc.c | 52 ++++++++++ drivers/soc/renesas/rcar-sysc.c | 3 drivers/soc/renesas/rcar-sysc.h | 1 6 files changed, 63 insertions(+) Index: renesas/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt =================================================================== --- renesas.orig/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt +++ renesas/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt @@ -18,6 +18,7 @@ Required properties: - "renesas,r8a7795-sysc" (R-Car H3) - "renesas,r8a7796-sysc" (R-Car M3-W) - "renesas,r8a77970-sysc" (R-Car V3M) + - "renesas,r8a77980-sysc" (R-Car V3H) - "renesas,r8a77995-sysc" (R-Car D3) - reg: Address start and address range for the device. - #power-domain-cells: Must be 1. Index: renesas/drivers/soc/renesas/Kconfig =================================================================== --- renesas.orig/drivers/soc/renesas/Kconfig +++ renesas/drivers/soc/renesas/Kconfig @@ -15,6 +15,7 @@ config SOC_RENESAS select SYSC_R8A7795 if ARCH_R8A7795 select SYSC_R8A7796 if ARCH_R8A7796 select SYSC_R8A77970 if ARCH_R8A77970 + select SYSC_R8A77980 if ARCH_R8A77980 select SYSC_R8A77995 if ARCH_R8A77995 if SOC_RENESAS @@ -60,6 +61,10 @@ config SYSC_R8A77970 bool "R-Car V3M System Controller support" if COMPILE_TEST select SYSC_RCAR +config SYSC_R8A77980 + bool "R-Car V3H System Controller support" if COMPILE_TEST + select SYSC_RCAR + config SYSC_R8A77995 bool "R-Car D3 System Controller support" if COMPILE_TEST select SYSC_RCAR Index: renesas/drivers/soc/renesas/Makefile =================================================================== --- renesas.orig/drivers/soc/renesas/Makefile +++ renesas/drivers/soc/renesas/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_SYSC_R8A7794) += r8a7794-sy obj-$(CONFIG_SYSC_R8A7795) += r8a7795-sysc.o obj-$(CONFIG_SYSC_R8A7796) += r8a7796-sysc.o obj-$(CONFIG_SYSC_R8A77970) += r8a77970-sysc.o +obj-$(CONFIG_SYSC_R8A77980) += r8a77980-sysc.o obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o # Family Index: renesas/drivers/soc/renesas/r8a77980-sysc.c =================================================================== --- /dev/null +++ renesas/drivers/soc/renesas/r8a77980-sysc.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas R-Car V3H System Controller + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ + +#include <linux/bug.h> +#include <linux/kernel.h> + +#include <dt-bindings/power/r8a77980-sysc.h> + +#include "rcar-sysc.h" + +static const struct rcar_sysc_area r8a77980_areas[] __initconst = { + { "always-on", 0, 0, R8A77980_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, + { "ca53-scu", 0x140, 0, R8A77980_PD_CA53_SCU, R8A77980_PD_ALWAYS_ON, + PD_SCU }, + { "ca53-cpu0", 0x200, 0, R8A77980_PD_CA53_CPU0, R8A77980_PD_CA53_SCU, + PD_CPU_NOCR }, + { "ca53-cpu1", 0x200, 1, R8A77980_PD_CA53_CPU1, R8A77980_PD_CA53_SCU, + PD_CPU_NOCR }, + { "ca53-cpu2", 0x200, 2, R8A77980_PD_CA53_CPU2, R8A77980_PD_CA53_SCU, + PD_CPU_NOCR }, + { "ca53-cpu3", 0x200, 3, R8A77980_PD_CA53_CPU3, R8A77980_PD_CA53_SCU, + PD_CPU_NOCR }, + { "cr7", 0x240, 0, R8A77980_PD_CR7, R8A77980_PD_ALWAYS_ON }, + { "a3ir", 0x180, 0, R8A77980_PD_A3IR, R8A77980_PD_ALWAYS_ON }, + { "a2ir0", 0x400, 0, R8A77980_PD_A2IR0, R8A77980_PD_A3IR }, + { "a2ir1", 0x400, 1, R8A77980_PD_A2IR1, R8A77980_PD_A3IR }, + { "a2ir2", 0x400, 2, R8A77980_PD_A2IR2, R8A77980_PD_A3IR }, + { "a2ir3", 0x400, 3, R8A77980_PD_A2IR3, R8A77980_PD_A3IR }, + { "a2ir4", 0x400, 4, R8A77980_PD_A2IR4, R8A77980_PD_A3IR }, + { "a2ir5", 0x400, 5, R8A77980_PD_A2IR5, R8A77980_PD_A3IR }, + { "a2sc0", 0x400, 6, R8A77980_PD_A2SC0, R8A77980_PD_A3IR }, + { "a2sc1", 0x400, 7, R8A77980_PD_A2SC1, R8A77980_PD_A3IR }, + { "a2sc2", 0x400, 8, R8A77980_PD_A2SC2, R8A77980_PD_A3IR }, + { "a2sc3", 0x400, 9, R8A77980_PD_A2SC3, R8A77980_PD_A3IR }, + { "a2sc4", 0x400, 10, R8A77980_PD_A2SC4, R8A77980_PD_A3IR }, + { "a2pd0", 0x400, 11, R8A77980_PD_A2PD0, R8A77980_PD_A3IR }, + { "a2pd1", 0x400, 12, R8A77980_PD_A2PD1, R8A77980_PD_A3IR }, + { "a2cn", 0x400, 13, R8A77980_PD_A2CN, R8A77980_PD_A3IR }, + { "a3vip", 0x2c0, 0, R8A77980_PD_A3VIP, R8A77980_PD_ALWAYS_ON }, + { "a3vip1", 0x300, 0, R8A77980_PD_A3VIP1, R8A77980_PD_A3VIP }, + { "a3vip2", 0x280, 0, R8A77980_PD_A3VIP2, R8A77980_PD_A3VIP }, +}; + +const struct rcar_sysc_info r8a77980_sysc_info __initconst = { + .areas = r8a77980_areas, + .num_areas = ARRAY_SIZE(r8a77980_areas), +}; Index: renesas/drivers/soc/renesas/rcar-sysc.c =================================================================== --- renesas.orig/drivers/soc/renesas/rcar-sysc.c +++ renesas/drivers/soc/renesas/rcar-sysc.c @@ -287,6 +287,9 @@ static const struct of_device_id rcar_sy #ifdef CONFIG_SYSC_R8A77970 { .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info }, #endif +#ifdef CONFIG_SYSC_R8A77980 + { .compatible = "renesas,r8a77980-sysc", .data = &r8a77980_sysc_info }, +#endif #ifdef CONFIG_SYSC_R8A77995 { .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info }, #endif Index: renesas/drivers/soc/renesas/rcar-sysc.h =================================================================== --- renesas.orig/drivers/soc/renesas/rcar-sysc.h +++ renesas/drivers/soc/renesas/rcar-sysc.h @@ -59,6 +59,7 @@ extern const struct rcar_sysc_info r8a77 extern const struct rcar_sysc_info r8a7795_sysc_info; extern const struct rcar_sysc_info r8a7796_sysc_info; extern const struct rcar_sysc_info r8a77970_sysc_info; +extern const struct rcar_sysc_info r8a77980_sysc_info; extern const struct rcar_sysc_info r8a77995_sysc_info; -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 2/5] arm64: dts: renesas: r8a77980: add [H]SCIF support [not found] ` <ae31804b-969b-9b20-16d0-50f5dea42f08-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> 2018-02-16 18:28 ` [PATCH v2 1/5] soc: renesas: rcar-sysc: add R8A77980 support Sergei Shtylyov @ 2018-02-16 18:30 ` Sergei Shtylyov 2018-02-16 18:35 ` [PATCH v2 4/5] arm64: dts: renesas: initial Condor board device tree Sergei Shtylyov 2 siblings, 0 replies; 12+ messages in thread From: Sergei Shtylyov @ 2018-02-16 18:30 UTC (permalink / raw) To: Rob Herring, Catalin Marinas, Will Deacon, Simon Horman, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA Cc: Mark Rutland, Magnus Damm, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Describe [H]SCIF ports in the R8A77980 device tree. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org> --- Changes in version 2: - fixed the internal BRG clock to S3D1 for all ports; - added Geert's tag. arch/arm64/boot/dts/renesas/r8a77980.dtsi | 151 ++++++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi =================================================================== --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -56,6 +56,13 @@ method = "smc"; }; + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -85,6 +92,150 @@ #power-domain-cells = <1>; }; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a77980", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE 19>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a77980", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE 19>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a77980", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE 19>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a77980", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE 19>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x37>, <&dmac1 0x36>, + <&dmac2 0x37>, <&dmac2 0x36>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 517>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77980", + "renesas,rcar-gen3-scif", + "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE 19>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a77980", + "renesas,rcar-gen3-scif", + "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE 19>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a77980", + "renesas,rcar-gen3-scif", + "renesas,scif"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE 19>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x57>, <&dmac1 0x56>, + <&dmac2 0x57>, <&dmac2 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a77980", + "renesas,rcar-gen3-scif", + "renesas,scif"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE 19>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x59>, <&dmac1 0x58>, + <&dmac2 0x59>, <&dmac2 0x58>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc 32>; + resets = <&cpg 203>; + status = "disabled"; + }; + dmac1: dma-controller@e7300000 { compatible = "renesas,dmac-r8a77980", "renesas,rcar-dmac"; -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 4/5] arm64: dts: renesas: initial Condor board device tree [not found] ` <ae31804b-969b-9b20-16d0-50f5dea42f08-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> 2018-02-16 18:28 ` [PATCH v2 1/5] soc: renesas: rcar-sysc: add R8A77980 support Sergei Shtylyov 2018-02-16 18:30 ` [PATCH v2 2/5] arm64: dts: renesas: r8a77980: add [H]SCIF support Sergei Shtylyov @ 2018-02-16 18:35 ` Sergei Shtylyov 2018-02-19 8:30 ` Geert Uytterhoeven 2 siblings, 1 reply; 12+ messages in thread From: Sergei Shtylyov @ 2018-02-16 18:35 UTC (permalink / raw) To: Rob Herring, Catalin Marinas, Will Deacon, Simon Horman, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA Cc: Mark Rutland, Magnus Damm, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Add the initial device tree for the R8A77980 SoC based Condor board. The board has 1 debug serial port (SCIF0); include support for it, so that the serial console can work. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org> --- Changes in version 2: - removed the useless "status" property from the SCIF_CLK node; - fixed the memory size; - added Geert's tag. arch/arm64/boot/dts/renesas/Makefile | 1 arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 45 ++++++++++++++++++++++++ 2 files changed, 46 insertions(+) Index: renesas/arch/arm64/boot/dts/renesas/Makefile =================================================================== --- renesas.orig/arch/arm64/boot/dts/renesas/Makefile +++ renesas/arch/arm64/boot/dts/renesas/Makefile @@ -8,4 +8,5 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-sa dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb +dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts =================================================================== --- /dev/null +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Condor board + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ + +/dts-v1/; +#include "r8a77980.dtsi" + +/ { + model = "Renesas Condor board based on r8a77980"; + compatible = "renesas,condor", "renesas,r8a77980"; + + aliases { + serial0 = &scif0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0 0x48000000 0 0xb8000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&scif0 { + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 4/5] arm64: dts: renesas: initial Condor board device tree 2018-02-16 18:35 ` [PATCH v2 4/5] arm64: dts: renesas: initial Condor board device tree Sergei Shtylyov @ 2018-02-19 8:30 ` Geert Uytterhoeven 2018-02-19 8:34 ` Sergei Shtylyov 0 siblings, 1 reply; 12+ messages in thread From: Geert Uytterhoeven @ 2018-02-19 8:30 UTC (permalink / raw) To: Sergei Shtylyov Cc: Mark Rutland, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Magnus Damm, Simon Horman, Catalin Marinas, Will Deacon, Linux-Renesas, Rob Herring, linux-arm-kernel Hi Sergei, On Fri, Feb 16, 2018 at 7:35 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Add the initial device tree for the R8A77980 SoC based Condor board. > The board has 1 debug serial port (SCIF0); include support for it, so > that the serial console can work. > > Based on the original (and large) patch by Vladimir Barinov. > > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > --- > Changes in version 2: > - removed the useless "status" property from the SCIF_CLK node; > - fixed the memory size; > - added Geert's tag. > --- /dev/null > +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts > @@ -0,0 +1,45 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for the Condor board > + * > + * Copyright (C) 2018 Renesas Electronics Corp. > + * Copyright (C) 2018 Cogent Embedded, Inc. > + */ > + > +/dts-v1/; > +#include "r8a77980.dtsi" > + > +/ { > + model = "Renesas Condor board based on r8a77980"; > + compatible = "renesas,condor", "renesas,r8a77980"; > + > + aliases { > + serial0 = &scif0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory@48000000 { > + device_type = "memory"; > + /* first 128MB is reserved for secure area. */ > + reg = <0 0x48000000 0 0xb8000000>; Shouldn't the size be 0x78000000, or is there really 3 GiB of RAM? oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 4/5] arm64: dts: renesas: initial Condor board device tree 2018-02-19 8:30 ` Geert Uytterhoeven @ 2018-02-19 8:34 ` Sergei Shtylyov 2018-02-19 9:12 ` Simon Horman 0 siblings, 1 reply; 12+ messages in thread From: Sergei Shtylyov @ 2018-02-19 8:34 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Mark Rutland, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Magnus Damm, Simon Horman, Catalin Marinas, Will Deacon, Linux-Renesas, Rob Herring, linux-arm-kernel Hello! On 2/19/2018 11:30 AM, Geert Uytterhoeven wrote: >> Add the initial device tree for the R8A77980 SoC based Condor board. >> The board has 1 debug serial port (SCIF0); include support for it, so >> that the serial console can work. >> >> Based on the original (and large) patch by Vladimir Barinov. >> >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> >> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> >> >> --- >> Changes in version 2: >> - removed the useless "status" property from the SCIF_CLK node; >> - fixed the memory size; >> - added Geert's tag. > >> --- /dev/null >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts >> @@ -0,0 +1,45 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Device Tree Source for the Condor board >> + * >> + * Copyright (C) 2018 Renesas Electronics Corp. >> + * Copyright (C) 2018 Cogent Embedded, Inc. >> + */ >> + >> +/dts-v1/; >> +#include "r8a77980.dtsi" >> + >> +/ { >> + model = "Renesas Condor board based on r8a77980"; >> + compatible = "renesas,condor", "renesas,r8a77980"; >> + >> + aliases { >> + serial0 = &scif0; >> + }; >> + >> + chosen { >> + stdout-path = "serial0:115200n8"; >> + }; >> + >> + memory@48000000 { >> + device_type = "memory"; >> + /* first 128MB is reserved for secure area. */ >> + reg = <0 0x48000000 0 0xb8000000>; > > Shouldn't the size be 0x78000000, or is there really 3 GiB of RAM? Ugh, so I finally mixed up limit and size... :-/ > oetje,eeting}s, > > Geert MBR, Sergei ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 4/5] arm64: dts: renesas: initial Condor board device tree 2018-02-19 8:34 ` Sergei Shtylyov @ 2018-02-19 9:12 ` Simon Horman 2018-02-19 19:18 ` Sergei Shtylyov 0 siblings, 1 reply; 12+ messages in thread From: Simon Horman @ 2018-02-19 9:12 UTC (permalink / raw) To: Sergei Shtylyov Cc: Mark Rutland, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Magnus Damm, Catalin Marinas, Will Deacon, Linux-Renesas, Rob Herring, Geert Uytterhoeven, linux-arm-kernel On Mon, Feb 19, 2018 at 11:34:41AM +0300, Sergei Shtylyov wrote: > Hello! > > On 2/19/2018 11:30 AM, Geert Uytterhoeven wrote: > > > > Add the initial device tree for the R8A77980 SoC based Condor board. > > > The board has 1 debug serial port (SCIF0); include support for it, so > > > that the serial console can work. > > > > > > Based on the original (and large) patch by Vladimir Barinov. > > > > > > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> > > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > > > > --- > > > Changes in version 2: > > > - removed the useless "status" property from the SCIF_CLK node; > > > - fixed the memory size; > > > - added Geert's tag. > > > > > --- /dev/null > > > +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts > > > @@ -0,0 +1,45 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +/* > > > + * Device Tree Source for the Condor board > > > + * > > > + * Copyright (C) 2018 Renesas Electronics Corp. > > > + * Copyright (C) 2018 Cogent Embedded, Inc. > > > + */ > > > + > > > +/dts-v1/; > > > +#include "r8a77980.dtsi" > > > + > > > +/ { > > > + model = "Renesas Condor board based on r8a77980"; > > > + compatible = "renesas,condor", "renesas,r8a77980"; > > > + > > > + aliases { > > > + serial0 = &scif0; > > > + }; > > > + > > > + chosen { > > > + stdout-path = "serial0:115200n8"; > > > + }; > > > + > > > + memory@48000000 { > > > + device_type = "memory"; > > > + /* first 128MB is reserved for secure area. */ > > > + reg = <0 0x48000000 0 0xb8000000>; > > > > Shouldn't the size be 0x78000000, or is there really 3 GiB of RAM? > > Ugh, so I finally mixed up limit and size... :-/ Thanks, I will apply the following, with the memory corrected to 2 GiB. From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Subject: [PATCH] arm64: dts: renesas: initial Condor board device tree Add the initial device tree for the R8A77980 SoC based Condor board. The board has 1 debug serial port (SCIF0); include support for it, so that the serial console can work. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> [simon: correct memory size to 0x78000000 (2GiB)] Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- arch/arm64/boot/dts/renesas/Makefile | 1 + arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 45 +++++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a77980-condor.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 2186d0193b73..c885eef4e660 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -8,4 +8,5 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb +dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts new file mode 100644 index 000000000000..daf2957d3504 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Condor board + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ + +/dts-v1/; +#include "r8a77980.dtsi" + +/ { + model = "Renesas Condor board based on r8a77980"; + compatible = "renesas,condor", "renesas,r8a77980"; + + aliases { + serial0 = &scif0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0 0x48000000 0 0x78000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&scif0 { + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; -- 2.11.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 4/5] arm64: dts: renesas: initial Condor board device tree 2018-02-19 9:12 ` Simon Horman @ 2018-02-19 19:18 ` Sergei Shtylyov 0 siblings, 0 replies; 12+ messages in thread From: Sergei Shtylyov @ 2018-02-19 19:18 UTC (permalink / raw) To: Simon Horman Cc: Mark Rutland, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Magnus Damm, Catalin Marinas, Will Deacon, Linux-Renesas, Rob Herring, Geert Uytterhoeven, linux-arm-kernel On 02/19/2018 12:12 PM, Simon Horman wrote: >>>> Add the initial device tree for the R8A77980 SoC based Condor board. >>>> The board has 1 debug serial port (SCIF0); include support for it, so >>>> that the serial console can work. >>>> >>>> Based on the original (and large) patch by Vladimir Barinov. >>>> >>>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> >>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> >>>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> >>>> >>>> --- >>>> Changes in version 2: >>>> - removed the useless "status" property from the SCIF_CLK node; >>>> - fixed the memory size; >>>> - added Geert's tag. >>> >>>> --- /dev/null >>>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts >>>> @@ -0,0 +1,45 @@ >>>> +// SPDX-License-Identifier: GPL-2.0 >>>> +/* >>>> + * Device Tree Source for the Condor board >>>> + * >>>> + * Copyright (C) 2018 Renesas Electronics Corp. >>>> + * Copyright (C) 2018 Cogent Embedded, Inc. >>>> + */ >>>> + >>>> +/dts-v1/; >>>> +#include "r8a77980.dtsi" >>>> + >>>> +/ { >>>> + model = "Renesas Condor board based on r8a77980"; >>>> + compatible = "renesas,condor", "renesas,r8a77980"; >>>> + >>>> + aliases { >>>> + serial0 = &scif0; >>>> + }; >>>> + >>>> + chosen { >>>> + stdout-path = "serial0:115200n8"; >>>> + }; >>>> + >>>> + memory@48000000 { >>>> + device_type = "memory"; >>>> + /* first 128MB is reserved for secure area. */ >>>> + reg = <0 0x48000000 0 0xb8000000>; >>> >>> Shouldn't the size be 0x78000000, or is there really 3 GiB of RAM? >> >> Ugh, so I finally mixed up limit and size... :-/ > > Thanks, I will apply the following, with the memory corrected to 2 GiB. Thank you! Just made sure that whatever is in this node in .dts, the RAM size ends up being 0x78000000. Probably U-Boot is too smart. :-) MBR, Sergei ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 3/5] arm64: dts: renesas: r8a77980: add EtherAVB support 2018-02-16 18:25 [PATCH v2 0/5] Add R8A77980/Condor board support Sergei Shtylyov [not found] ` <ae31804b-969b-9b20-16d0-50f5dea42f08-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> @ 2018-02-16 18:32 ` Sergei Shtylyov 2018-02-19 8:35 ` Geert Uytterhoeven 2018-02-16 18:38 ` [PATCH v2 5/5] arm64: dts: renesas: condor: " Sergei Shtylyov 2018-02-19 9:13 ` [PATCH v2 0/5] Add R8A77980/Condor board support Simon Horman 3 siblings, 1 reply; 12+ messages in thread From: Sergei Shtylyov @ 2018-02-16 18:32 UTC (permalink / raw) To: Rob Herring, Catalin Marinas, Will Deacon, Simon Horman, devicetree, linux-renesas-soc Cc: Mark Rutland, Magnus Damm, linux-arm-kernel Define the generic R8A77980 part of the EtherAVB device node. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- Changes in version 2: - removed the 2nd address/size tuple from the "reg" property; - changed the "phy-mode" property to the RGMII by default. arch/arm64/boot/dts/renesas/r8a77980.dtsi | 44 ++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi =================================================================== --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -164,6 +164,50 @@ status = "disabled"; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a77980", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc 32>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a77980", "renesas,rcar-gen3-scif", ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 3/5] arm64: dts: renesas: r8a77980: add EtherAVB support 2018-02-16 18:32 ` [PATCH v2 3/5] arm64: dts: renesas: r8a77980: add EtherAVB support Sergei Shtylyov @ 2018-02-19 8:35 ` Geert Uytterhoeven 0 siblings, 0 replies; 12+ messages in thread From: Geert Uytterhoeven @ 2018-02-19 8:35 UTC (permalink / raw) To: Sergei Shtylyov Cc: Mark Rutland, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Magnus Damm, Simon Horman, Catalin Marinas, Will Deacon, Linux-Renesas, Rob Herring, linux-arm-kernel On Fri, Feb 16, 2018 at 7:32 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Define the generic R8A77980 part of the EtherAVB device node. > > Based on the original (and large) patch by Vladimir Barinov. > > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 5/5] arm64: dts: renesas: condor: add EtherAVB support 2018-02-16 18:25 [PATCH v2 0/5] Add R8A77980/Condor board support Sergei Shtylyov [not found] ` <ae31804b-969b-9b20-16d0-50f5dea42f08-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> 2018-02-16 18:32 ` [PATCH v2 3/5] arm64: dts: renesas: r8a77980: add EtherAVB support Sergei Shtylyov @ 2018-02-16 18:38 ` Sergei Shtylyov 2018-02-19 9:13 ` [PATCH v2 0/5] Add R8A77980/Condor board support Simon Horman 3 siblings, 0 replies; 12+ messages in thread From: Sergei Shtylyov @ 2018-02-16 18:38 UTC (permalink / raw) To: Rob Herring, Catalin Marinas, Will Deacon, Simon Horman, devicetree, linux-renesas-soc Cc: Mark Rutland, Magnus Damm, linux-arm-kernel Define the Condor board dependent part of the EtherAVB device node. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- Changes in version 2: - added the "renesas,no-ether-link" property; - overrode the "phy-mode" property. arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts =================================================================== --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -15,6 +15,7 @@ aliases { serial0 = &scif0; + ethernet0 = &avb; }; chosen { @@ -28,6 +29,18 @@ }; }; +&avb { + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + renesas,no-ether-link; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + }; +}; + &extal_clk { clock-frequency = <16666666>; }; ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 0/5] Add R8A77980/Condor board support 2018-02-16 18:25 [PATCH v2 0/5] Add R8A77980/Condor board support Sergei Shtylyov ` (2 preceding siblings ...) 2018-02-16 18:38 ` [PATCH v2 5/5] arm64: dts: renesas: condor: " Sergei Shtylyov @ 2018-02-19 9:13 ` Simon Horman 3 siblings, 0 replies; 12+ messages in thread From: Simon Horman @ 2018-02-19 9:13 UTC (permalink / raw) To: Sergei Shtylyov Cc: Mark Rutland, devicetree, Magnus Damm, Catalin Marinas, Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel On Fri, Feb 16, 2018 at 09:25:30PM +0300, Sergei Shtylyov wrote: > Hello! > > Here's the set of 11 patches against Simon Horman's 'renesas.git' repo's > 'renesas-devel-20180216-v4.16-rc1' tag. I'm adding the device tree support > for the R8A77980-based Condor board (note that NFS root would only work on > the Condor boards [re]wired for booting from EtherAVB -- we haven't been > able to get the 'sh_eth' driver working in either U-Boot or Linux so far). > The necessary SYS-DMAC, [H]SCIF, and EtherAVB bindings updates have been > posted, the clock driver has been reposted yesterday, and the merged patches > have been dropped from this respin of the series... > > [1/5] soc: renesas: rcar-sysc: add R8A77980 support > [2/5] arm64: dts: renesas: r8a77980: add [H]SCIF support > [3/5] arm64: dts: renesas: r8a77980: add EtherAVB support > [4/5] arm64: dts: renesas: initial Condor board device tree > [5/5] arm64: dts: renesas: condor: add EtherAVB support Thanks, applied. ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2018-02-19 19:18 UTC | newest]
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2018-02-16 18:25 [PATCH v2 0/5] Add R8A77980/Condor board support Sergei Shtylyov
[not found] ` <ae31804b-969b-9b20-16d0-50f5dea42f08-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
2018-02-16 18:28 ` [PATCH v2 1/5] soc: renesas: rcar-sysc: add R8A77980 support Sergei Shtylyov
2018-02-16 18:30 ` [PATCH v2 2/5] arm64: dts: renesas: r8a77980: add [H]SCIF support Sergei Shtylyov
2018-02-16 18:35 ` [PATCH v2 4/5] arm64: dts: renesas: initial Condor board device tree Sergei Shtylyov
2018-02-19 8:30 ` Geert Uytterhoeven
2018-02-19 8:34 ` Sergei Shtylyov
2018-02-19 9:12 ` Simon Horman
2018-02-19 19:18 ` Sergei Shtylyov
2018-02-16 18:32 ` [PATCH v2 3/5] arm64: dts: renesas: r8a77980: add EtherAVB support Sergei Shtylyov
2018-02-19 8:35 ` Geert Uytterhoeven
2018-02-16 18:38 ` [PATCH v2 5/5] arm64: dts: renesas: condor: " Sergei Shtylyov
2018-02-19 9:13 ` [PATCH v2 0/5] Add R8A77980/Condor board support Simon Horman
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