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Thu, 13 Mar 2025 11:38:45 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52DBcifs007648 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Mar 2025 11:38:44 GMT Received: from [10.217.216.178] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 13 Mar 2025 04:38:40 -0700 Message-ID: Date: Thu, 13 Mar 2025 17:08:38 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/2] arm64: dts: qcom: sm8550: camcc: Manage MMCX and MXC To: Vladimir Zapolskiy , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jagadeesh Kona CC: Bryan O'Donoghue , Michael Turquette , Stephen Boyd , Conor Dooley , Dmitry Baryshkov , , , References: <20250303225521.1780611-1-vladimir.zapolskiy@linaro.org> Content-Language: en-US From: Taniya Das In-Reply-To: <20250303225521.1780611-1-vladimir.zapolskiy@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5qIQE2Tk5-s1TETCF_of3rF44pNV0l16 X-Authority-Analysis: v=2.4 cv=Q4XS452a c=1 sm=1 tr=0 ts=67d2c3c5 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=CqDDRk0MYutMoWn3TPMA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 5qIQE2Tk5-s1TETCF_of3rF44pNV0l16 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_05,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=947 adultscore=0 lowpriorityscore=0 mlxscore=0 clxscore=1015 phishscore=0 malwarescore=0 spamscore=0 impostorscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503130092 On 3/4/2025 4:25 AM, Vladimir Zapolskiy wrote: > It was discovered that on SM8550 platform Camera Clock controller shall > manage MMCX and MXC power domains, otherwise MMIO access to CCI or CAMSS > breaks the execution, the problem has been discussed with Jagadeesh at > https://lore.kernel.org/all/a5540676-9402-45c4-b647-02fdc2b92233@quicinc.com/ > > Since 'power-domains' property becomes generalized, Rob asked to remove > its description, which is done in the first patch of the series, see > https://lore.kernel.org/all/20240927224833.GA159707-robh@kernel.org/ > > Vladimir Zapolskiy (2): > dt-bindings: clock: qcom: sm8450-camcc: Allow to specify two power domains > arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camcc > Hi Vladimir, as we are preparing to submit the code for multi-power domain support for the clock controller in our series (https://lore.kernel.org/all/20250306-videocc-pll-multi-pd-voting-v2-0-0cd00612bc0e@quicinc.com), there has been a request to incorporate the CAMCC-related changes as well. If you are okay with us including this series changes(maintaining your authorship) in our series, then we can integrate them and address any comments in our next submission. > .../devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 4 +--- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 ++- > 2 files changed, 3 insertions(+), 4 deletions(-) >