[PATCH v5 0/3] Add lpass pin control support for audio on sc7280 based targets

[PATCH v5 0/3] Add lpass pin control support for audio on sc7280 based targets

[Srinivasa Rao Mandadapu]

This patch set is to add lpass pin control support for Audio over I2S,
wcd codec and digital mics.
This patch set depends on:
	-- Lpass-lpi pinctrl patches [https://patchwork.kernel.org/project/alsa-devel/list/?series=623951&archive=both&state=*]

Changes Since V4:
    -- Add primary and secondary I2S pinmux nodes for herobrine specific targets.
Changes Since V3:
    -- Add pinctrl nodes for wcd codec reset and CTIA/OMTP headset selection.
Changes Since V2:
    -- Move lpass pin control node to main dtsi file.
    -- Sort nodes alphabetically.
    -- Remove redundant wcd reset gpio nodes.
    -- Remove redundant input-enable field in dmic pin control nodes.
    -- Update amp_en node. 
    -- Fix typo errors.
    -- Modify node names.
    -- Create patches on latest kernel.    
Changes Since V1:
    -- Merge pinmux and pinconf properties in amp_en and wcd pin reset node.
    -- Split common i2s pin control nodes to functionality specific nodes.
    -- Move board specific properties to board specific dtsi file.
    -- Update dmic pin control node name.
Srinivasa Rao Mandadapu (3):
  arm64: dts: qcom: sc7280: Add pinctrl for wcd938x codec reset and
    CTIA/OMTP headset selection
  arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset
  arm64: dts: qcom: sc7280: add lpass lpi pin controller node

 arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi |  34 +++++
 arch/arm64/boot/dts/qcom/sc7280-idp.dtsi       |  43 ++++++
 arch/arm64/boot/dts/qcom/sc7280.dtsi           | 188 +++++++++++++++++++++++++
 3 files changed, 265 insertions(+)

-- 
2.7.4

[PATCH v5 1/3] arm64: dts: qcom: sc7280: Add pinctrl for wcd938x codec reset and CTIA/OMTP headset selection

[Srinivasa Rao Mandadapu]

Add pinctrl nodes for wcd codec reset and CTIA/OMTP headset type selection.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index ecbf2b8..688fa95 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -545,5 +545,27 @@
 		function = "gpio";
 		bias-pull-down;
 	};
+
+	us_euro_select: us-euro-select {
+		pins = "gpio81";
+		function = "gpio";
+		bias-pull-down;
+		drive-strength = <2>;
+	};
+
+	wcd938x_reset_active: wcd938x-reset-active {
+		pins = "gpio83";
+		function = "gpio";
+		drive-strength = <16>;
+		output-high;
+	};
+
+	wcd938x_reset_sleep: wcd938x-reset-sleep {
+		pins = "gpio83";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
 };
 
-- 
2.7.4

Re: [PATCH v5 1/3] arm64: dts: qcom: sc7280: Add pinctrl for wcd938x codec reset and CTIA/OMTP headset selection

[Stephen Boyd]

Quoting Srinivasa Rao Mandadapu (2022-03-21 04:59:17)
> Add pinctrl nodes for wcd codec reset and CTIA/OMTP headset type selection.
>
> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)

Please combine this patch with the consumer that uses the pinctrl nodes.
Otherwise it is too hard to review the contents of this patch.

Re: [PATCH v5 1/3] arm64: dts: qcom: sc7280: Add pinctrl for wcd938x codec reset and CTIA/OMTP headset selection

[Srinivasa Rao Mandadapu]

On 3/22/2022 1:57 AM, Stephen Boyd wrote:
Thanks for your time Stephen!!!
> Quoting Srinivasa Rao Mandadapu (2022-03-21 04:59:17)
>> Add pinctrl nodes for wcd codec reset and CTIA/OMTP headset type selection.
>>
>> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
>> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
>> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 22 ++++++++++++++++++++++
>>   1 file changed, 22 insertions(+)
> Please combine this patch with the consumer that uses the pinctrl nodes.
> Otherwise it is too hard to review the contents of this patch.
Okay. Will do accordingly.

[PATCH v5 2/3] arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset

[Srinivasa Rao Mandadapu]

Add AMP enable node and pinmux for primary and secondary I2S
for SC7280 based platforms.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 34 +++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sc7280-idp.dtsi       | 21 +++++++++++++
 arch/arm64/boot/dts/qcom/sc7280.dtsi           | 41 ++++++++++++++++++++++++++
 3 files changed, 96 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
index dc17f20..de646d9 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
@@ -530,6 +530,26 @@ ap_ec_spi: &spi10 {
 	drive-strength = <2>;
 };
 
+&pri_mi2s_data0 {
+	drive-strength = <6>;
+};
+
+&pri_mi2s_data1 {
+	drive-strength = <6>;
+};
+
+&pri_mi2s_mclk {
+	drive-strength = <6>;
+};
+
+&pri_mi2s_sclk {
+	drive-strength = <6>;
+};
+
+&pri_mi2s_ws {
+	drive-strength = <6>;
+};
+
 &qspi_cs0 {
 	bias-disable;
 	drive-strength = <8>;
@@ -610,6 +630,20 @@ ap_ec_spi: &spi10 {
 	drive-strength = <10>;
 };
 
+&sec_mi2s_data0 {
+	drive-strength = <6>;
+	bias-disable;
+};
+
+&sec_mi2s_sclk {
+	drive-strength = <6>;
+	bias-disable;
+};
+
+&sec_mi2s_ws {
+	drive-strength = <6>;
+};
+
 /* PINCTRL - board-specific pinctrl */
 
 &pm7325_gpios {
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 688fa95..4a7b18a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -462,7 +462,28 @@
 	drive-strength = <10>;
 };
 
+&sec_mi2s_data0 {
+	drive-strength = <6>;
+	bias-disable;
+};
+
+&sec_mi2s_sclk {
+	drive-strength = <6>;
+	bias-disable;
+};
+
+&sec_mi2s_ws {
+	drive-strength = <6>;
+};
+
 &tlmm {
+	amp_en: amp-en {
+		pins = "gpio63";
+		function = "gpio";
+		bias-pull-down;
+		drive-strength = <2>;
+	};
+
 	bt_en: bt-en {
 		pins = "gpio85";
 		function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index f0b64be..8d8cec5 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3527,6 +3527,31 @@
 				function = "pcie1_clkreqn";
 			};
 
+			pri_mi2s_data0: pri-mi2s-data0 {
+				pins = "gpio98";
+				function = "mi2s0_data0";
+			};
+
+			pri_mi2s_data1: pri-mi2s-data1 {
+				pins = "gpio99";
+				function = "mi2s0_data1";
+			};
+
+			pri_mi2s_mclk: pri-mi2s-mclk {
+				pins = "gpio96";
+				function = "pri_mi2s";
+			};
+
+			pri_mi2s_sclk: pri-mi2s-sclk {
+				pins = "gpio97";
+				function = "mi2s0_sck";
+			};
+
+			pri_mi2s_ws: pri-mi2s-ws {
+				pins = "gpio100";
+				function = "mi2s0_ws";
+			};
+
 			qspi_clk: qspi-clk {
 				pins = "gpio14";
 				function = "qspi_clk";
@@ -4261,6 +4286,22 @@
 				drive-strength = <2>;
 				bias-bus-hold;
 			};
+
+			sec_mi2s_data0: sec-mi2s-data0 {
+				pins = "gpio107";
+				function = "mi2s1_data0";
+			};
+
+			sec_mi2s_sclk: sec-mi2s-sclk {
+				pins = "gpio106";
+				function = "mi2s1_sck";
+			};
+
+			sec_mi2s_ws: sec-mi2s-ws {
+				pins = "gpio108";
+				function = "mi2s1_ws";
+			};
+
 		};
 
 		imem@146a5000 {
-- 
2.7.4

Re: [PATCH v5 2/3] arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset

[Stephen Boyd]

Quoting Srinivasa Rao Mandadapu (2022-03-21 04:59:18)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> index 688fa95..4a7b18a 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> @@ -462,7 +462,28 @@
>         drive-strength = <10>;
>  };
>
> +&sec_mi2s_data0 {
> +       drive-strength = <6>;
> +       bias-disable;
> +};
> +
> +&sec_mi2s_sclk {
> +       drive-strength = <6>;
> +       bias-disable;
> +};
> +
> +&sec_mi2s_ws {
> +       drive-strength = <6>;
> +};
> +
>  &tlmm {
> +       amp_en: amp-en {
> +               pins = "gpio63";
> +               function = "gpio";

I'm pretty sure 'function = "gpio"' isn't needed. When a gpio is
requested with gpio functions it gets muxed to gpio function
automatically. See commit 1de7ddb3a15c ("pinctrl: msm: Mux out gpio
function with gpio_request()").

> +               bias-pull-down;
> +               drive-strength = <2>;
> +       };
> +
>         bt_en: bt-en {
>                 pins = "gpio85";
>                 function = "gpio";

Re: [PATCH v5 2/3] arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset

[Srinivasa Rao Mandadapu]

On 3/22/2022 2:00 AM, Stephen Boyd wrote:
Thanks for your time Stephen!!!
> Quoting Srinivasa Rao Mandadapu (2022-03-21 04:59:18)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
>> index 688fa95..4a7b18a 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
>> @@ -462,7 +462,28 @@
>>          drive-strength = <10>;
>>   };
>>
>> +&sec_mi2s_data0 {
>> +       drive-strength = <6>;
>> +       bias-disable;
>> +};
>> +
>> +&sec_mi2s_sclk {
>> +       drive-strength = <6>;
>> +       bias-disable;
>> +};
>> +
>> +&sec_mi2s_ws {
>> +       drive-strength = <6>;
>> +};
>> +
>>   &tlmm {
>> +       amp_en: amp-en {
>> +               pins = "gpio63";
>> +               function = "gpio";
> I'm pretty sure 'function = "gpio"' isn't needed. When a gpio is
> requested with gpio functions it gets muxed to gpio function
> automatically. See commit 1de7ddb3a15c ("pinctrl: msm: Mux out gpio
> function with gpio_request()").
Okay. Will remove it.
>
>> +               bias-pull-down;
>> +               drive-strength = <2>;
>> +       };
>> +
>>          bt_en: bt-en {
>>                  pins = "gpio85";
>>                  function = "gpio";

[PATCH v5 3/3] arm64: dts: qcom: sc7280: add lpass lpi pin controller node

[Srinivasa Rao Mandadapu]

Add LPASS LPI pinctrl node required for Audio functionality on sc7280
based platforms.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 147 +++++++++++++++++++++++++++++++++++
 1 file changed, 147 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 8d8cec5..499299a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1987,6 +1987,153 @@
 			qcom,bcm-voters = <&apps_bcm_voter>;
 		};
 
+		lpass_tlmm: pinctrl@33c0000 {
+			compatible = "qcom,sc7280-lpass-lpi-pinctrl";
+			reg = <0 0x33c0000 0x0 0x20000>,
+				<0 0x3550000 0x0 0x10000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&lpass_tlmm 0 0 15>;
+
+			#clock-cells = <1>;
+
+			dmic01_active: dmic01-active {
+				clk {
+					pins = "gpio6";
+					function = "dmic1_clk";
+					drive-strength = <8>;
+					output-high;
+				};
+
+				data {
+					pins = "gpio7";
+					function = "dmic1_data";
+					drive-strength = <8>;
+				};
+			};
+
+			dmic01_sleep: dmic01-sleep {
+				clk {
+					pins = "gpio6";
+					function = "dmic1_clk";
+					drive-strength = <2>;
+					bias-disable;
+					output-low;
+				};
+
+				data {
+					pins = "gpio7";
+					function = "dmic1_data";
+					drive-strength = <2>;
+					pull-down;
+				};
+			};
+
+			dmic23_active: dmic02-active {
+				clk {
+					pins = "gpio8";
+					function = "dmic2_clk";
+					drive-strength = <8>;
+					output-high;
+				};
+
+				data {
+					pins = "gpio9";
+					function = "dmic2_data";
+					drive-strength = <8>;
+				};
+			};
+
+			dmic23_sleep: dmic02-sleep {
+				clk {
+					pins = "gpio8";
+					function = "dmic2_clk";
+					drive-strength = <2>;
+					bias-disable;
+					output-low;
+				};
+
+				data {
+					pins = "gpio9";
+					function = "dmic2_data";
+					drive-strength = <2>;
+					pull-down;
+				};
+			};
+
+			rx_swr_active: rx-swr-active {
+				clk {
+					pins = "gpio3";
+					function = "swr_rx_clk";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-disable;
+				};
+
+				data {
+					pins = "gpio4", "gpio5";
+					function = "swr_rx_data";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-bus-hold;
+				};
+			};
+
+			rx_swr_sleep: rx-swr-sleep {
+				clk {
+					pins = "gpio3";
+					function = "swr_rx_clk";
+					drive-strength = <2>;
+					input-enable;
+					bias-pull-down;
+				};
+
+				data {
+					pins = "gpio4", "gpio5";
+					function = "swr_rx_data";
+					drive-strength = <2>;
+					input-enable;
+					bias-pull-down;
+				};
+			};
+
+			tx_swr_active: tx-swr-active {
+				clk {
+					pins = "gpio0";
+					function = "swr_tx_clk";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-disable;
+				};
+
+				data {
+					pins = "gpio1", "gpio2", "gpio14";
+					function = "swr_tx_data";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-bus-hold;
+				};
+			};
+
+			tx_swr_sleep: tx-swr-sleep {
+				clk {
+					pins = "gpio0";
+					function = "swr_tx_clk";
+					drive-strength = <2>;
+					input-enable;
+					bias-pull-down;
+				};
+
+				data {
+					pins = "gpio1", "gpio2", "gpio14";
+					function = "swr_tx_data";
+					drive-strength = <2>;
+					input-enable;
+					bias-bus-hold;
+				};
+			};
+		};
+
 		gpu: gpu@3d00000 {
 			compatible = "qcom,adreno-635.0", "qcom,adreno";
 			reg = <0 0x03d00000 0 0x40000>,
-- 
2.7.4

Re: [PATCH v5 3/3] arm64: dts: qcom: sc7280: add lpass lpi pin controller node

[Stephen Boyd]

Quoting Srinivasa Rao Mandadapu (2022-03-21 04:59:19)
> Add LPASS LPI pinctrl node required for Audio functionality on sc7280
> based platforms.
>
> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 147 +++++++++++++++++++++++++++++++++++
>  1 file changed, 147 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 8d8cec5..499299a 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1987,6 +1987,153 @@
>                         qcom,bcm-voters = <&apps_bcm_voter>;
>                 };
>
> +               lpass_tlmm: pinctrl@33c0000 {
> +                       compatible = "qcom,sc7280-lpass-lpi-pinctrl";
> +                       reg = <0 0x33c0000 0x0 0x20000>,
> +                               <0 0x3550000 0x0 0x10000>;
> +                       gpio-controller;
> +                       #gpio-cells = <2>;
> +                       gpio-ranges = <&lpass_tlmm 0 0 15>;
> +
> +                       #clock-cells = <1>;
> +
> +                       dmic01_active: dmic01-active {
> +                               clk {
> +                                       pins = "gpio6";
> +                                       function = "dmic1_clk";
> +                                       drive-strength = <8>;
> +                                       output-high;

The rule of thumb is that drive strength, output/input, and bias
properties should be in the board file, because the board layout decides
the drive strength, the output level could be inverted on the board, and
the biasing could be done externally (or not) via pullup/pulldowns on
the net. The gpio driver should be able to make pins into inputs
automatically when the gpio is requested and used so having input or
output is typically wrong and should be handled by the consumer driver.

> +                               };
> +
> +                               data {
> +                                       pins = "gpio7";
> +                                       function = "dmic1_data";

So in the end I'd expect to only see pins and function properties in the
SoC dtsi file.

> +                                       drive-strength = <8>;
> +                               };
> +                       };
> +
> +                       dmic01_sleep: dmic01-sleep {
> +                               clk {
> +                                       pins = "gpio6";
> +                                       function = "dmic1_clk";

Re: [PATCH v5 3/3] arm64: dts: qcom: sc7280: add lpass lpi pin controller node

[Srinivasa Rao Mandadapu]

On 3/22/2022 1:56 AM, Stephen Boyd wrote:
> Quoting Srinivasa Rao Mandadapu (2022-03-21 04:59:19)
>> Add LPASS LPI pinctrl node required for Audio functionality on sc7280
>> based platforms.
>>
>> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
>> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
>> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 147 +++++++++++++++++++++++++++++++++++
>>   1 file changed, 147 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 8d8cec5..499299a 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -1987,6 +1987,153 @@
>>                          qcom,bcm-voters = <&apps_bcm_voter>;
>>                  };
>>
>> +               lpass_tlmm: pinctrl@33c0000 {
>> +                       compatible = "qcom,sc7280-lpass-lpi-pinctrl";
>> +                       reg = <0 0x33c0000 0x0 0x20000>,
>> +                               <0 0x3550000 0x0 0x10000>;
>> +                       gpio-controller;
>> +                       #gpio-cells = <2>;
>> +                       gpio-ranges = <&lpass_tlmm 0 0 15>;
>> +
>> +                       #clock-cells = <1>;
>> +
>> +                       dmic01_active: dmic01-active {
>> +                               clk {
>> +                                       pins = "gpio6";
>> +                                       function = "dmic1_clk";
>> +                                       drive-strength = <8>;
>> +                                       output-high;
> The rule of thumb is that drive strength, output/input, and bias
> properties should be in the board file, because the board layout decides
> the drive strength, the output level could be inverted on the board, and
> the biasing could be done externally (or not) via pullup/pulldowns on
> the net. The gpio driver should be able to make pins into inputs
> automatically when the gpio is requested and used so having input or
> output is typically wrong and should be handled by the consumer driver.
Okay. will re arrange accordingly and remove output-high property.
>
>> +                               };
>> +
>> +                               data {
>> +                                       pins = "gpio7";
>> +                                       function = "dmic1_data";
> So in the end I'd expect to only see pins and function properties in the
> SoC dtsi file.
Okay.
>
>> +                                       drive-strength = <8>;
>> +                               };
>> +                       };
>> +
>> +                       dmic01_sleep: dmic01-sleep {
>> +                               clk {
>> +                                       pins = "gpio6";
>> +                                       function = "dmic1_clk";