From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9ED21C433E0 for ; Mon, 22 Jun 2020 06:46:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7E52D22B39 for ; Mon, 22 Jun 2020 06:46:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="TV4xGCpF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726601AbgFVGq0 (ORCPT ); Mon, 22 Jun 2020 02:46:26 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:50250 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725933AbgFVGq0 (ORCPT ); Mon, 22 Jun 2020 02:46:26 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05M6juET037132; Mon, 22 Jun 2020 01:45:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1592808356; bh=CzFkttaRhi3JTEfc3yW2lucwElCU+YQ+OtTKPFDbd+8=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=TV4xGCpFnjxAd54nxcfg4xS7anK+kfMrUtfOPCWALgU8JXq75pmRXgFuxQbfkvnjc 0MJEkYepa+lk5Y+ay80qE201tbRvG79jkntXoVPsLE0AeXFYCqtlw66vakucwOaXZ/ 1hVt52vzIVOVj0OggFbofvOoRUc2MH8qlreXQ1BA= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 05M6juZ7102986 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 22 Jun 2020 01:45:56 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 22 Jun 2020 01:45:56 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 22 Jun 2020 01:45:56 -0500 Received: from [127.0.0.1] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05M6jrhJ049545; Mon, 22 Jun 2020 01:45:54 -0500 Subject: Re: [PATCHv4 1/4] dt-bindings: watchdog: Add support for TI K3 RTI watchdog To: Jan Kiszka , , , CC: , Rob Herring , References: <20200312095808.19907-1-t-kristo@ti.com> <20200312095808.19907-2-t-kristo@ti.com> From: Tero Kristo Message-ID: Date: Mon, 22 Jun 2020 09:45:53 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 18/06/2020 19:09, Jan Kiszka wrote: > On 12.03.20 10:58, Tero Kristo wrote: >> TI K3 SoCs contain an RTI (Real Time Interrupt) module which can be >> used to implement a windowed watchdog functionality. Windowed watchdog >> will generate an error if it is petted outside the time window, either >> too early or too late. >> >> Cc: Rob Herring >> Cc: devicetree@vger.kernel.org >> Signed-off-by: Tero Kristo >> --- >> v4: >> * changed license to dual >> * added documentation for missing properties >> * added ref to watchdog.yaml >> * renamed main_rti0 to watchdog0 in example >> >> .../bindings/watchdog/ti,rti-wdt.yaml | 65 +++++++++++++++++++ >> 1 file changed, 65 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml >> >> diff --git a/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml b/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml >> new file mode 100644 >> index 000000000000..e83026fef2e9 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml >> @@ -0,0 +1,65 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/watchdog/ti,rti-wdt.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Texas Instruments K3 SoC Watchdog Timer >> + >> +maintainers: >> + - Tero Kristo >> + >> +description: >> + The TI K3 SoC watchdog timer is implemented via the RTI (Real Time >> + Interrupt) IP module. This timer adds a support for windowed watchdog >> + mode, which will signal an error if it is pinged outside the watchdog >> + time window, meaning either too early or too late. The error signal >> + generated can be routed to either interrupt a safety controller or >> + to directly reset the SoC. >> + >> +allOf: >> + - $ref: "watchdog.yaml#" >> + >> +properties: >> + compatible: >> + enum: >> + - ti,j7-rti-wdt >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + maxItems: 1 >> + >> + power-domains: >> + maxItems: 1 >> + >> + assigned-clocks: >> + maxItems: 1 >> + >> + assigned-clocks-parents: >> + maxItems: 1 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - power-domains >> + >> +examples: >> + - | >> + /* >> + * RTI WDT in main domain on J721e SoC. Assigned clocks are used to >> + * select the source clock for the watchdog, forcing it to tick with >> + * a 32kHz clock in this case. >> + */ >> + #include >> + >> + watchdog0: rti@2200000 { >> + compatible = "ti,rti-wdt"; > > At some stage, you changed the compatible string to something > J721e-specific. This one wasn't updated. Hmm nice catch, this should be fixed. I wonder why the DT test tools did not catch this when I changed the compatible... >> + reg = <0x0 0x2200000 0x0 0x100>; >> + clocks = <&k3_clks 252 1>; >> + power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; >> + assigned-clocks = <&k3_clks 252 1>; >> + assigned-clock-parents = <&k3_clks 252 5>; >> + }; >> > > And where is the binding for the AM65x? I know that PG1 has nice > erratum, but I would expect PG2 to be fine and register-wise compatible, no? ti,am65-rti-wdt should be added as a new compatible to this binding once we have a board where we can actually support this. Right now TI AM65x boards depend on firmware for the ESM side support; there has been some internal discussion about how to get this done and I believe you are aware of that. -Tero -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki