From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AB46C433FE for ; Mon, 21 Nov 2022 17:13:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231344AbiKURNo (ORCPT ); Mon, 21 Nov 2022 12:13:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231349AbiKURNX (ORCPT ); Mon, 21 Nov 2022 12:13:23 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1629B9488; Mon, 21 Nov 2022 09:12:36 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2ALHCKte036107; Mon, 21 Nov 2022 11:12:20 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1669050740; bh=d2yjy4E3Cau/LM3GEWxS0TIWJTajMDUqGXONkImtaAI=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=PqZuyRAXD0ozhV67WM2uGpruJDOPcZrhLjzHRKqUbMic0eu9DdH0El1rTk3Fn612n dE+j4kS0s6F9zstCOAIhhj2MoYGlWvTRcvBVIKRC6eWgBPuqn2lpEEmEzWO3fNnr3m v90T3XRsgfMNx2FXc3zzOfp2+bhUNu/3eOxCUZzU= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2ALHCKE1128330 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 21 Nov 2022 11:12:20 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Mon, 21 Nov 2022 11:12:20 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Mon, 21 Nov 2022 11:12:20 -0600 Received: from [10.250.38.44] (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2ALHCJpq004140; Mon, 21 Nov 2022 11:12:19 -0600 Message-ID: Date: Mon, 21 Nov 2022 11:12:18 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v6 7/8] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node Content-Language: en-US To: Matt Ranostay , , , , , , , CC: , , References: <20221119040906.9495-1-mranostay@ti.com> <20221119040906.9495-8-mranostay@ti.com> From: Andrew Davis In-Reply-To: <20221119040906.9495-8-mranostay@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 11/18/22 10:09 PM, Matt Ranostay wrote: > From: Aswath Govindraju > > Add PCIe device tree node (both RC and EP) for the single PCIe > instance present in j721s2. > So which is it, you have two nodes but this is one device. It can switch between the two modes, a property should have been used to select the mode for the device. Making two nodes for the same device as examples of what they could look like, then only enabling one of the two in the board level DT is not how this is done anywhere else. Take the common parts and make one node here with those. Then at the board level .dts where we select what mode this driver will act in, add the specific bits for the chosen mode. Andrew > Reviewed-by: Siddharth Vadapalli > Signed-off-by: Aswath Govindraju > Signed-off-by: Vignesh Raghavendra > Signed-off-by: Matt Ranostay > --- > arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 61 ++++++++++++++++++++++ > 1 file changed, 61 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > index adbb172658b9..04294e25d587 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > @@ -841,6 +841,67 @@ serdes0: serdes@5060000 { > }; > }; > > + pcie1_rc: pcie@2910000 { > + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; > + reg = <0x00 0x02910000 0x00 0x1000>, > + <0x00 0x02917000 0x00 0x400>, > + <0x00 0x0d800000 0x00 0x00800000>, > + <0x00 0x18000000 0x00 0x00001000>; > + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; > + interrupt-names = "link_state"; > + interrupts = ; > + device_type = "pci"; > + ti,syscon-pcie-ctrl = <&scm_conf 0x074>; > + max-link-speed = <3>; > + num-lanes = <4>; > + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 276 41>; > + clock-names = "fck"; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x0 0xff>; > + vendor-id = <0x104c>; > + device-id = <0xb013>; > + msi-map = <0x0 &gic_its 0x0 0x10000>; > + dma-coherent; > + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, > + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; > + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ > + <0 0 0 2 &pcie1_intc 0>, /* INT B */ > + <0 0 0 3 &pcie1_intc 0>, /* INT C */ > + <0 0 0 4 &pcie1_intc 0>; /* INT D */ > + > + pcie1_intc: interrupt-controller { > + interrupt-controller; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic500>; > + interrupts = ; > + }; > + }; > + > + pcie1_ep: pcie-ep@2910000 { > + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; > + reg = <0x00 0x02910000 0x00 0x1000>, > + <0x00 0x02917000 0x00 0x400>, > + <0x00 0x0d800000 0x00 0x00800000>, > + <0x00 0x18000000 0x00 0x08000000>; > + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; > + interrupt-names = "link_state"; > + interrupts = ; > + ti,syscon-pcie-ctrl = <&scm_conf 0x074>; > + max-link-speed = <3>; > + num-lanes = <4>; > + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 276 41>; > + clock-names = "fck"; > + max-functions = /bits/ 8 <6>; > + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; > + dma-coherent; > + }; > + > main_mcan0: can@2701000 { > compatible = "bosch,m_can"; > reg = <0x00 0x02701000 0x00 0x200>,