From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A9861D52B; Tue, 12 Aug 2025 08:16:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754986603; cv=none; b=XuyksSDU2Iq62BwHz6QV38+/iBT+MY2atnVSsPRVfrdKRkH908KO/2ecLfjn97WG/D9Cmli+d6KvdxCG1ebbiaZZWtX58FVomD824WHnV/wgIdf4kUMM2QJh/toyz8XfkwD+QV/BjVdRvMXK93Bx8TSYTlAMCFCG6GBxsRM0alw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754986603; c=relaxed/simple; bh=P/4iHug9aWMJUEbfqYNlF4Q9hMiKkkjLX3Wk1MYqj+E=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=QRN1tsYaj1q5r5jrOUXRYKkfFGXWNpy2hsB0aTI+9sLlNhNbJJKS4cBa2gO7NwYYzDLnn30OIDgv1TZk/sc0OPOnf7TwndWYu73HxTqstcl4uUOC/IiozIWj0+B/jlmebcqJ2/HC7cpbTpITl+Q9a8QuJByaRMZCNhA3qaLzI24= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fJQFV4Wx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fJQFV4Wx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7400FC4CEF0; Tue, 12 Aug 2025 08:16:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754986602; bh=P/4iHug9aWMJUEbfqYNlF4Q9hMiKkkjLX3Wk1MYqj+E=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=fJQFV4WxW1ldsuOPyZ4PgSM1LHloFHo9u8dEP0cFlKN2klN+QMyZUCUG7lnAK+Cb1 L7tCJmDqnrCmSjzyNwT5Oz1khEfKX0+DrIH0Rp1K6yBnKPBse5TB3wy8yV9PrssE1J eu6qzwN/aS4UfPURh7PvZgwLliSLHfgofRi/P9WhbKqjizDmSqgKAPuJS9vrMQkg7r n/uqQpZbf9tlrw2wPv/pvkNaFfJ+ynpNtTKm2Mmq8b6SzU0Hart74QPU3xQ3SKOdN2 pNk5m0te5xuqrQhQvgLtNYio1UkLWYc2aljKvRl5RoOw1VsWn1tvJHSfoBhXKHPlBb QPy3oliDy7eoQ== Message-ID: Date: Tue, 12 Aug 2025 10:16:37 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/3] media: iris: Add support for SM8750 (VPU v3.5) To: Dikshita Agarwal , Krzysztof Kozlowski , Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250804-sm8750-iris-v2-0-6d78407f8078@linaro.org> <20250804-sm8750-iris-v2-3-6d78407f8078@linaro.org> <83205cad-14f5-65a1-1818-677335a1ab91@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 12/08/2025 10:05, Dikshita Agarwal wrote: >> >> struct platform_clk_data { >> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c >> index d3026b2bcb708c7ec31f134f628df7e57b54af4f..c7c384fce2332255ea96da69ef4dc0bc1a24771c 100644 >> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c >> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c >> @@ -1,6 +1,7 @@ >> // SPDX-License-Identifier: GPL-2.0-only >> /* >> * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. >> + * Copyright (c) 2025 Linaro Ltd > > > I don't see a need to add a copyright here. And I see the need, I added there quite a lot of lines. Look at your commit bb8a95aa038e099f5ec82c466e996b006e05abd7 https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bb8a95aa038e099f5ec82c466e996b006e05abd7 and this hunk: drivers/media/platform/qcom/iris/iris_resources.h which adds 7 (!) declarations and a copyright. If you claim you copyright 7 lines of such declarations: +struct iris_core; + +int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev); +int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev); +int iris_unset_icc_bw(struct iris_core *core); +int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw); +int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type); +int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type); then me adding here 68 lines of NEW CREATIVE WORK is copyrightable as well. Anyway, you cannot reject someone's copyrights. The work is copyrightable regardless if you see a need. > >> + >> + iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); >> + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); >> +} >> + >> +static int iris_vpu35_power_off_controller(struct iris_core *core) >> +{ >> + u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size; >> + u32 val = 0; >> + int ret; >> + >> + writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH); >> + >> + writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL); >> + >> + ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS, >> + val, val & BIT(0), 200, 2000); >> + if (ret) >> + goto disable_power; >> + >> + writel(0x0, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL); >> + >> + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL); > > > Read initial status of AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS > > based on value, run the retry loop. > This loop runs till the desired LPI state is reached i.e. BIT(0) is set, > and hardware is idle i.e. BIT(1) or BIT(2) are unset. This suggests a > situation where the hardware might be stuck or slow to transition. > > This sequence was not needed for SM8650 since it doesn't have > AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL/STATUS registers. > But required for SM8750, so please add. Sure > > >> + ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS, >> + val, val & (BIT(0) | BIT(1) | BIT(2)), 15, 1000); >> + if (ret) >> + goto disable_power> + >> + writel(0x0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL); >> + >> + writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL); >> + >> + ret = readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS, >> + val, val == 0, 200, 2000); >> + if (ret) >> + goto disable_power; >> + >> +disable_power: >> + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); >> + iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); >> + iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); >> + >> + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); >> + >> + reset_control_bulk_reset(clk_rst_tbl_size, core->resets); >> + >> + return 0; >> +} >> + >> +static int iris_vpu35_power_on_controller(struct iris_core *core) >> +{ >> + u32 rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size; >> + int ret; >> + >> + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); >> + if (ret) >> + return ret; >> + >> + ret = reset_control_bulk_reset(rst_tbl_size, core->resets); >> + if (ret) >> + goto err_disable_power; > > > this reset is not needed to power-on this SOC. Hm, I will trust you on that, thanks. Best regards, Krzysztof