[PATCH V2] arm64: dts: qcom: sc7280: Update lpassaudio clock controller for resets

[PATCH V2] arm64: dts: qcom: sc7280: Update lpassaudio clock controller for resets

[Satya Priya]

From: Taniya Das <quic_tdas@quicinc.com>

The lpass audio supports TX/RX/WSA block resets. Disable the LPASS PIL
clock by default, boards can enable it if needed.

Also to keep consistency update lpasscore to lpass_core.

Fixes: 9499240d15f2 ("arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com>
---
Changes since V1:
 - Updated the phandle reference in lpass_aon node.
 - As per Matthias' comment updated the commit text.

 arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 40e700c..73dddca 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2174,6 +2174,7 @@
 			clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
 			clock-names = "iface";
 			#clock-cells = <1>;
+			status = "disabled";
 		};
 
 		lpass_audiocc: clock-controller@3300000 {
@@ -2185,6 +2186,7 @@
 			power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
 			#clock-cells = <1>;
 			#power-domain-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		lpass_aon: clock-controller@3380000 {
@@ -2192,13 +2194,13 @@
 			reg = <0 0x03380000 0 0x30000>;
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 			       <&rpmhcc RPMH_CXO_CLK_A>,
-			       <&lpasscore LPASS_CORE_CC_CORE_CLK>;
+			       <&lpass_core LPASS_CORE_CC_CORE_CLK>;
 			clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
 			#clock-cells = <1>;
 			#power-domain-cells = <1>;
 		};
 
-		lpasscore: clock-controller@3900000 {
+		lpass_core: clock-controller@3900000 {
 			compatible = "qcom,sc7280-lpasscorecc";
 			reg = <0 0x03900000 0 0x50000>;
 			clocks = <&rpmhcc RPMH_CXO_CLK>;
-- 
2.7.4

Re: [PATCH V2] arm64: dts: qcom: sc7280: Update lpassaudio clock controller for resets

[Krzysztof Kozlowski]

On 07/07/2022 10:15, Satya Priya wrote:
> From: Taniya Das <quic_tdas@quicinc.com>
> 
> The lpass audio supports TX/RX/WSA block resets. Disable the LPASS PIL
> clock by default, boards can enable it if needed.

You made here few different changes at once but I fail to see why. The
most important message in commit msg is "why?". Why are you disabling
LPASS PIL by default?

> 
> Also to keep consistency update lpasscore to lpass_core.

This definitely should not be backported to stable.

> 
> Fixes: 9499240d15f2 ("arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers")

This does not look right or I did not understand where the bug is.
Please describe what is the error/issue/bug being fixed (which would
explain the need of backporting).

More over, the patch alone brings regression - disables the LPASS PIL
while before it was enabled. For sure it should not be backported.

> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com>
> ---
> Changes since V1:
>  - Updated the phandle reference in lpass_aon node.
>  - As per Matthias' comment updated the commit text.
> 
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)


Best regards,
Krzysztof