From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 169051FF7C7; Tue, 7 Apr 2026 07:37:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775547450; cv=none; b=iDHcSGTiu26B2mudofOLMRIpS7eVIQRYgT7AilQWQvPSuWbdU9Gg+puzqcM2rYLFPtrYhqO3XIL+Wx6tjQOwo0+qVMjQqls8vUyELkJIVRQF8Yg3lX58UElfpEP5NTjg+L4EFdD5naHquElWbz2dHvjbrQCpMF+ZJf6NKPTImOU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775547450; c=relaxed/simple; bh=BFFsI3LeN7f2LzSaom7luMGiKHZgnhrFdc4/ppxffj4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=EUhjCWncWmu6vkpCyGCpwnLWnufq8CivlPC1AikQB1/6fQJ8X4WXs829p9fP36s6VIYM2wBO4cj1eKuHWEcmInbCsQxI2YcLZlvL5pqszVhzxoFphs4ApGZr1QgZ4gSAKWpWNt0VV5nSDC8IecvYNQYy7SZPpZTTbbKSP91TfYo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fdS4v3Kx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fdS4v3Kx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E8BECC116C6; Tue, 7 Apr 2026 07:37:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775547449; bh=BFFsI3LeN7f2LzSaom7luMGiKHZgnhrFdc4/ppxffj4=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=fdS4v3Kx90ZiW1zfPnNzjMVvSi2ExUDPHP4ccdjpazBkUmlr3Luso1vA0xZDeqGGL VwIj2PC+2MPQeJs2aaxAcrk12QcFE+Fh/i0hNE6MrQHrIyobd0vbcU6batS1/dccI/ UrULAUUVd61OZr9svWmE4R3lYxcnF32EUUnaXRiYlxuOV+aqe2YZEtScKWD4kcnZ8F aJZscF0dJqH8mSyipLMrWNKkTFN1VsQUleM1Prk1ZeAoyKZ2AEpYV/TR9hOZ46Mkv6 7+ENnniFLo7LifiM52eEv2Hl4f97OgkFoQjmEomNX1hP385tKdtTEfiSY5Zs4/7pvI i48vzIc5INIPw== Message-ID: Date: Tue, 7 Apr 2026 09:37:22 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 01/13] dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules To: Changhuang Liang Cc: Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Philipp Zabel , Emil Renner Berthing , Chen Wang , Inochi Amaoto , Alexey Charkov , Thomas Bogendoerfer , Keguang Zhang , "linux-clk@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-riscv@lists.infradead.org" , Leyfoon Tan References: <20260403054945.467700-1-changhuang.liang@starfivetech.com> <20260403054945.467700-2-changhuang.liang@starfivetech.com> <20260405-nocturnal-mighty-pegasus-eff399@quoll> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 07/04/2026 09:34, Changhuang Liang wrote: > Hi, Krzysztof > > Thanks for the review. > >> On Thu, Apr 02, 2026 at 10:49:33PM -0700, Changhuang Liang wrote: >>> Add documentation to describe StarFive JHB100 SoC System Controller >>> Registers. >>> >>> Signed-off-by: Changhuang Liang >>> --- >>> .../soc/starfive/starfive,jhb100-syscon.yaml | 140 >> ++++++++++++++++++ >>> MAINTAINERS | 5 + >>> 2 files changed, 145 insertions(+) >>> create mode 100644 >>> Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon. >>> yaml >>> >>> diff --git >>> a/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-sysco >>> n.yaml >>> b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-sysco >>> n.yaml >>> new file mode 100644 >>> index 000000000000..c0e1f6f68fa2 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-s >>> +++ yscon.yaml >>> @@ -0,0 +1,140 @@ >>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 >>> +--- >>> +$id: >>> +http://devicetree.org/schemas/soc/starfive/starfive,jhb100-syscon.yam >>> +l# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: StarFive JHB100 SoC system controller >>> + >>> +maintainers: >>> + - Kevin Xie >>> + - Changhuang Liang >>> + >>> +description: >>> + The StarFive JHB100 SoC system controller provides register >>> +information such >>> + as offset, mask and shift to configure related modules such as PLL and >> PCIe. >> >> How a MMIO based device can provide a MMIO information? What exactly >> does it provide? Register where the value is the offset of other register? > > For example: > in per1 syscon: > offset 0x4 is the register configuration for implementing eMMC extended functions, > and offsets 0x40–0x4c are used for PLL7 register configuration. > > In sys0 syscon: > offsets 0x0–0x2c are used for register configuration of PLL2 to PLL5, > and offset 0x38 is used for register configuration to provide the product ID. That's not what the text said. You wrote the device, in MMIO registers, provides information: offset, mask and shift. Best regards, Krzysztof