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Fri, 25 Oct 2024 05:26:31 -0700 (PDT) Message-ID: Subject: Re: [PATCH RFC v4 08/15] spi: dt-bindings: axi-spi-engine: add SPI offload properties From: Nuno =?ISO-8859-1?Q?S=E1?= To: David Lechner , Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nuno =?ISO-8859-1?Q?S=E1?= , Uwe =?ISO-8859-1?Q?Kleine-K=F6nig?= Cc: Michael Hennerich , Lars-Peter Clausen , David Jander , Martin Sperl , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org Date: Fri, 25 Oct 2024 14:26:31 +0200 In-Reply-To: <20241023-dlech-mainline-spi-engine-offload-2-v4-8-f8125b99f5a1@baylibre.com> References: <20241023-dlech-mainline-spi-engine-offload-2-v4-0-f8125b99f5a1@baylibre.com> <20241023-dlech-mainline-spi-engine-offload-2-v4-8-f8125b99f5a1@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 (3.52.4-1.fc40) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2024-10-23 at 15:59 -0500, David Lechner wrote: > The AXI SPI Engine has support for hardware offloading capabilities. > This includes a connection to a DMA controller for streaming RX data > and a trigger input for starting execution of the SPI message programmed > in the offload. >=20 > Signed-off-by: David Lechner > --- > v4 changes: > * Dropped #spi-offload-cells property. > * Changed subject line. >=20 > v3 changes: > * Added #spi-offload-cells property. > * Added properties for triggers and RX data stream connected to DMA. >=20 > v2 changes: >=20 > This is basically a new patch. It partially replaces "dt-bindings: iio: > offload: add binding for PWM/DMA triggered buffer". >=20 > The controller no longer has an offloads object node and the > spi-offloads property is now a standard SPI peripheral property. > --- > =C2=A0.../bindings/spi/adi,axi-spi-engine.yaml=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 22 ++++++++++++++++++++++ > =C2=A01 file changed, 22 insertions(+) >=20 > diff --git a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yam= l > b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml > index d48faa42d025..5281b4871209 100644 > --- a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml > +++ b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml > @@ -41,6 +41,24 @@ properties: > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - const: s_axi_aclk > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - const: spi_clk > =C2=A0 > +=C2=A0 trigger-sources: > +=C2=A0=C2=A0=C2=A0 description: > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 An array of trigger source phandles for o= ffload instances. The index in > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 the array corresponds to the offload inst= ance number. > +=C2=A0=C2=A0=C2=A0 $ref: /schemas/types.yaml#/definitions/phandle-array > + > +=C2=A0 dmas: > +=C2=A0=C2=A0=C2=A0 description: > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 DMA channels connected to the output stre= am interface of an offload > instance. > +=C2=A0=C2=A0=C2=A0 minItems: 1 > +=C2=A0=C2=A0=C2=A0 maxItems: 32 > + > +=C2=A0 dma-names: > +=C2=A0=C2=A0=C2=A0 minItems: 1 > +=C2=A0=C2=A0=C2=A0 maxItems: 32 > +=C2=A0=C2=A0=C2=A0 items: > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pattern: "^offload(?:[12]?[0-9]|3[01])-rx= $" I think the core is already capable of tx offload? If so, we could already = have that in the bindings. - Nuno S=C3=A1