[PATCH 0/3] X1E GCC USB4 clock fix-ups

[PATCH 0/3] X1E GCC USB4 clock fix-ups

[Konrad Dybcio]

Some of the USB4 clock infrastructure has been left undescribed.

Following the example of Glymur, add all the required muxes and resets.

These changes have passed a smoke test with their intended usecase.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
Konrad Dybcio (3):
      dt-bindings: clock: qcom,x1e80100-gcc: Add missing USB4 clocks/resets
      clk: qcom: gcc-x1e80100: Add missing USB4 clocks/resets
      arm64: dts: qcom: x1e80100: Extend the gcc input clock list

 .../bindings/clock/qcom,x1e80100-gcc.yaml          |  62 +-
 arch/arm64/boot/dts/qcom/x1e80100.dtsi             |  29 +-
 drivers/clk/qcom/gcc-x1e80100.c                    | 803 ++++++++++++++++++++-
 include/dt-bindings/clock/qcom,x1e80100-gcc.h      |  61 ++
 4 files changed, 933 insertions(+), 22 deletions(-)
---
base-commit: 8e2755d7779a95dd61d8997ebce33ff8b1efd3fb
change-id: 20250926-topic-hamoa_gcc_usb4-35eb6741b141

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

[PATCH 1/3] dt-bindings: clock: qcom,x1e80100-gcc: Add missing USB4 clocks/resets

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Some of the USB4 muxes, RCGs and resets were not initially described.

Add indices for them to allow extending the driver.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 .../bindings/clock/qcom,x1e80100-gcc.yaml          | 62 ++++++++++++++++++++--
 include/dt-bindings/clock/qcom,x1e80100-gcc.h      | 61 +++++++++++++++++++++
 2 files changed, 119 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
index 68dde0720c711320aa0e7c74040cf3c4422dda72..1b15b507095455c93b1ba39404cafbb6f96be5a9 100644
--- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
@@ -32,9 +32,36 @@ properties:
       - description: PCIe 5 pipe clock
       - description: PCIe 6a pipe clock
       - description: PCIe 6b pipe clock
-      - description: USB QMP Phy 0 clock source
-      - description: USB QMP Phy 1 clock source
-      - description: USB QMP Phy 2 clock source
+      - description: USB4_0 QMPPHY clock source
+      - description: USB4_1 QMPPHY clock source
+      - description: USB4_2 QMPPHY clock source
+      - description: USB4_0 PHY DP0 GMUX clock source
+      - description: USB4_0 PHY DP1 GMUX clock source
+      - description: USB4_0 PHY PCIE PIPEGMUX clock source
+      - description: USB4_0 PHY PIPEGMUX clock source
+      - description: USB4_0 PHY SYS PCIE PIPEGMUX clock source
+      - description: USB4_1 PHY DP0 GMUX 2 clock source
+      - description: USB4_1 PHY DP1 GMUX 2 clock source
+      - description: USB4_1 PHY PCIE PIPEGMUX clock source
+      - description: USB4_1 PHY PIPEGMUX clock source
+      - description: USB4_1 PHY SYS PCIE PIPEGMUX clock source
+      - description: USB4_2 PHY DP0 GMUX 2 clock source
+      - description: USB4_2 PHY DP1 GMUX 2 clock source
+      - description: USB4_2 PHY PCIE PIPEGMUX clock source
+      - description: USB4_2 PHY PIPEGMUX clock source
+      - description: USB4_2 PHY SYS PCIE PIPEGMUX clock source
+      - description: USB4_0 PHY RX 0 clock source
+      - description: USB4_0 PHY RX 1 clock source
+      - description: USB4_1 PHY RX 0 clock source
+      - description: USB4_1 PHY RX 1 clock source
+      - description: USB4_2 PHY RX 0 clock source
+      - description: USB4_2 PHY RX 1 clock source
+      - description: USB4_0 PHY PCIE PIPE clock source
+      - description: USB4_0 PHY max PIPE clock source
+      - description: USB4_1 PHY PCIE PIPE clock source
+      - description: USB4_1 PHY max PIPE clock source
+      - description: USB4_2 PHY PCIE PIPE clock source
+      - description: USB4_2 PHY max PIPE clock source
 
   power-domains:
     description:
@@ -67,7 +94,34 @@ examples:
                <&pcie6b_phy>,
                <&usb_1_ss0_qmpphy 0>,
                <&usb_1_ss1_qmpphy 1>,
-               <&usb_1_ss2_qmpphy 2>;
+               <&usb_1_ss2_qmpphy 2>,
+               <&usb4_0_phy_dp0_gmux_clk>,
+               <&usb4_0_phy_dp1_gmux_clk>,
+               <&usb4_0_phy_pcie_pipegmux_clk>,
+               <&usb4_0_phy_pipegmux_clk>,
+               <&usb4_0_phy_sys_pcie_pipegmux_clk>,
+               <&usb4_1_phy_dp0_gmux_2_clk>,
+               <&usb4_1_phy_dp1_gmux_2_clk>,
+               <&usb4_1_phy_pcie_pipegmux_clk>,
+               <&usb4_1_phy_pipegmux_clk>,
+               <&usb4_1_phy_sys_pcie_pipegmux_clk>,
+               <&usb4_2_phy_dp0_gmux_2_clk>,
+               <&usb4_2_phy_dp1_gmux_2_clk>,
+               <&usb4_2_phy_pcie_pipegmux_clk>,
+               <&usb4_2_phy_pipegmux_clk>,
+               <&usb4_2_phy_sys_pcie_pipegmux_clk>,
+               <&usb4_0_phy_rx_0_clk>,
+               <&usb4_0_phy_rx_1_clk>,
+               <&usb4_1_phy_rx_0_clk>,
+               <&usb4_1_phy_rx_1_clk>,
+               <&usb4_2_phy_rx_0_clk>,
+               <&usb4_2_phy_rx_1_clk>,
+               <&usb4_0_phy_pcie_pipe_clk>,
+               <&usb4_0_phy_max_pipe_clk>,
+               <&usb4_1_phy_pcie_pipe_clk>,
+               <&usb4_1_phy_max_pipe_clk>,
+               <&usb4_2_phy_pcie_pipe_clk>,
+               <&usb4_2_phy_max_pipe_clk>;
       power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
diff --git a/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
index 710c340f24a57d799ac04650fbe9d4ea0f294bde..62aa1242559270dd3bd31cd10322ee265468b8e4 100644
--- a/include/dt-bindings/clock/qcom,x1e80100-gcc.h
+++ b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
@@ -363,6 +363,30 @@
 #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				353
 #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC				354
 #define GCC_USB3_TERT_PHY_PIPE_CLK_SRC				355
+#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC				356
+#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC				357
+#define GCC_USB34_TERT_PHY_PIPE_CLK_SRC				358
+#define GCC_USB4_0_PHY_DP0_CLK_SRC				359
+#define GCC_USB4_0_PHY_DP1_CLK_SRC				360
+#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC			361
+#define GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC			362
+#define GCC_USB4_0_PHY_RX0_CLK_SRC				363
+#define GCC_USB4_0_PHY_RX1_CLK_SRC				364
+#define GCC_USB4_0_PHY_SYS_CLK_SRC				365
+#define GCC_USB4_1_PHY_DP0_CLK_SRC				366
+#define GCC_USB4_1_PHY_DP1_CLK_SRC				367
+#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC			368
+#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC			369
+#define GCC_USB4_1_PHY_RX0_CLK_SRC				370
+#define GCC_USB4_1_PHY_RX1_CLK_SRC				371
+#define GCC_USB4_1_PHY_SYS_CLK_SRC				372
+#define GCC_USB4_2_PHY_DP0_CLK_SRC				373
+#define GCC_USB4_2_PHY_DP1_CLK_SRC				374
+#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC			375
+#define GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC			376
+#define GCC_USB4_2_PHY_RX0_CLK_SRC				377
+#define GCC_USB4_2_PHY_RX1_CLK_SRC				378
+#define GCC_USB4_2_PHY_SYS_CLK_SRC				379
 
 /* GCC power domains */
 #define GCC_PCIE_0_TUNNEL_GDSC					0
@@ -484,4 +508,41 @@
 #define GCC_VIDEO_BCR						87
 #define GCC_VIDEO_AXI0_CLK_ARES					88
 #define GCC_VIDEO_AXI1_CLK_ARES					89
+#define GCC_USB4_0_MISC_USB4_SYS_BCR				90
+#define GCC_USB4_0_MISC_RX_CLK_0_BCR				91
+#define GCC_USB4_0_MISC_RX_CLK_1_BCR				92
+#define GCC_USB4_0_MISC_USB_PIPE_BCR				93
+#define GCC_USB4_0_MISC_PCIE_PIPE_BCR				94
+#define GCC_USB4_0_MISC_TMU_BCR					95
+#define GCC_USB4_0_MISC_SB_IF_BCR				96
+#define GCC_USB4_0_MISC_HIA_MSTR_BCR				97
+#define GCC_USB4_0_MISC_AHB_BCR					98
+#define GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR			99
+#define GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR			100
+#define GCC_USB4_1_MISC_USB4_SYS_BCR				101
+#define GCC_USB4_1_MISC_RX_CLK_0_BCR				102
+#define GCC_USB4_1_MISC_RX_CLK_1_BCR				103
+#define GCC_USB4_1_MISC_USB_PIPE_BCR				104
+#define GCC_USB4_1_MISC_PCIE_PIPE_BCR				105
+#define GCC_USB4_1_MISC_TMU_BCR					106
+#define GCC_USB4_1_MISC_SB_IF_BCR				107
+#define GCC_USB4_1_MISC_HIA_MSTR_BCR				108
+#define GCC_USB4_1_MISC_AHB_BCR					109
+#define GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR			110
+#define GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR			111
+#define GCC_USB4_2_MISC_USB4_SYS_BCR				112
+#define GCC_USB4_2_MISC_RX_CLK_0_BCR				113
+#define GCC_USB4_2_MISC_RX_CLK_1_BCR				114
+#define GCC_USB4_2_MISC_USB_PIPE_BCR				115
+#define GCC_USB4_2_MISC_PCIE_PIPE_BCR				116
+#define GCC_USB4_2_MISC_TMU_BCR					117
+#define GCC_USB4_2_MISC_SB_IF_BCR				118
+#define GCC_USB4_2_MISC_HIA_MSTR_BCR				119
+#define GCC_USB4_2_MISC_AHB_BCR					120
+#define GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR			121
+#define GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR			122
+#define GCC_USB4PHY_PHY_PRIM_BCR				123
+#define GCC_USB4PHY_PHY_SEC_BCR					124
+#define GCC_USB4PHY_PHY_TERT_BCR				125
+
 #endif

-- 
2.51.0

[PATCH 2/3] clk: qcom: gcc-x1e80100: Add missing USB4 clocks/resets

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Currently, some of the USB4 clocks/resets are described, but not all
of the back-end muxes are present. Configuring them properly is
necessary for proper operation of the hardware.

Add all the resets & muxes and wire up any unaccounted USB4 clock paths.

Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-x1e80100.c | 803 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 786 insertions(+), 17 deletions(-)

diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
index 301fc9fc32d8e6e1ddf59c1d3350d84f6c06e4b6..1f866fb4a53ad4cca51d586e92aa96acab58ef0b 100644
--- a/drivers/clk/qcom/gcc-x1e80100.c
+++ b/drivers/clk/qcom/gcc-x1e80100.c
@@ -32,6 +32,33 @@ enum {
 	DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE,
 	DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE,
 	DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE,
+	DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC,
+	DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC,
+	DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC,
+	DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC,
+	DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC,
+	DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC,
+	DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC,
+	DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
+	DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
+	DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
+	DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC,
+	DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC,
+	DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC,
+	DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC,
+	DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC,
+	DT_QUSB4PHY_0_GCC_USB4_RX0_CLK,
+	DT_QUSB4PHY_0_GCC_USB4_RX1_CLK,
+	DT_QUSB4PHY_1_GCC_USB4_RX0_CLK,
+	DT_QUSB4PHY_1_GCC_USB4_RX1_CLK,
+	DT_QUSB4PHY_2_GCC_USB4_RX0_CLK,
+	DT_QUSB4PHY_2_GCC_USB4_RX1_CLK,
+	DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK,
+	DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
+	DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
+	DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
+	DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
+	DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
 };
 
 enum {
@@ -42,10 +69,40 @@ enum {
 	P_GCC_GPLL7_OUT_MAIN,
 	P_GCC_GPLL8_OUT_MAIN,
 	P_GCC_GPLL9_OUT_MAIN,
+	P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC,
+	P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC,
+	P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC,
+	P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC,
+	P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC,
+	P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC,
+	P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC,
+	P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC,
+	P_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC,
+	P_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC,
+	P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
+	P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
+	P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
+	P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC,
+	P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC,
+	P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC,
+	P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC,
+	P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC,
+	P_QUSB4PHY_0_GCC_USB4_RX0_CLK,
+	P_QUSB4PHY_0_GCC_USB4_RX1_CLK,
+	P_QUSB4PHY_1_GCC_USB4_RX0_CLK,
+	P_QUSB4PHY_1_GCC_USB4_RX1_CLK,
+	P_QUSB4PHY_2_GCC_USB4_RX0_CLK,
+	P_QUSB4PHY_2_GCC_USB4_RX1_CLK,
 	P_SLEEP_CLK,
 	P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK,
 	P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK,
 	P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK,
+	P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK,
+	P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
+	P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
+	P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
+	P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
+	P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
 };
 
 static struct clk_alpha_pll gcc_gpll0 = {
@@ -320,6 +377,447 @@ static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 	{ }
 };
 
+static const struct parent_map gcc_parent_map_13[] = {
+	{ P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC, 0 },
+	{ P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_13[] = {
+	{ .index = DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC },
+	{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
+};
+
+static const struct parent_map gcc_parent_map_14[] = {
+	{ P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC, 0 },
+	{ P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_14[] = {
+	{ .index = DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC },
+	{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
+};
+
+static const struct parent_map gcc_parent_map_15[] = {
+	{ P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
+	{ P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_15[] = {
+	{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
+	{ .index = DT_BI_TCXO },
+};
+
+static const struct parent_map gcc_parent_map_16[] = {
+	{ P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
+	{ P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 },
+};
+
+static const struct clk_parent_data gcc_parent_data_16[] = {
+	{ .index = DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC },
+	{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
+};
+
+static const struct parent_map gcc_parent_map_17[] = {
+	{ P_QUSB4PHY_0_GCC_USB4_RX0_CLK, 0 },
+	{ P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_17[] = {
+	{ .index = DT_QUSB4PHY_0_GCC_USB4_RX0_CLK },
+	{ .index = DT_BI_TCXO },
+};
+
+static const struct parent_map gcc_parent_map_18[] = {
+	{ P_QUSB4PHY_0_GCC_USB4_RX1_CLK, 0 },
+	{ P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_18[] = {
+	{ .index = DT_QUSB4PHY_0_GCC_USB4_RX1_CLK },
+	{ .index = DT_BI_TCXO },
+};
+
+static const struct parent_map gcc_parent_map_19[] = {
+	{ P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
+	{ P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_19[] = {
+	{ .index = DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC },
+	{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
+};
+
+static const struct parent_map gcc_parent_map_20[] = {
+	{ P_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC, 0 },
+	{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_20[] = {
+	{ .index = DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC },
+	{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
+};
+
+static const struct parent_map gcc_parent_map_21[] = {
+	{ P_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC, 0 },
+	{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_21[] = {
+	{ .index = DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC },
+	{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
+};
+
+static const struct parent_map gcc_parent_map_22[] = {
+	{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
+	{ P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_22[] = {
+	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
+	{ .index = DT_BI_TCXO },
+};
+
+static const struct parent_map gcc_parent_map_23[] = {
+	{ P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
+	{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 },
+};
+
+static const struct clk_parent_data gcc_parent_data_23[] = {
+	{ .index = DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC },
+	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
+};
+
+static const struct parent_map gcc_parent_map_24[] = {
+	{ P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 0 },
+	{ P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_24[] = {
+	{ .index = DT_QUSB4PHY_1_GCC_USB4_RX0_CLK },
+	{ .index = DT_BI_TCXO },
+};
+
+static const struct parent_map gcc_parent_map_25[] = {
+	{ P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 0 },
+	{ P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_25[] = {
+	{ .index = DT_QUSB4PHY_1_GCC_USB4_RX1_CLK },
+	{ .index = DT_BI_TCXO },
+};
+
+static const struct parent_map gcc_parent_map_26[] = {
+	{ P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
+	{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_26[] = {
+	{ .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC },
+	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
+};
+
+static const struct parent_map gcc_parent_map_27[] = {
+	{ P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC, 0 },
+	{ P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_27[] = {
+	{ .index = DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC },
+	{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
+};
+
+static const struct parent_map gcc_parent_map_28[] = {
+	{ P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC, 0 },
+	{ P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_28[] = {
+	{ .index = DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC },
+	{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
+};
+
+static const struct parent_map gcc_parent_map_29[] = {
+	{ P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
+	{ P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_29[] = {
+	{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
+	{ .index = DT_BI_TCXO },
+};
+
+static const struct parent_map gcc_parent_map_30[] = {
+	{ P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
+	{ P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 },
+};
+
+static const struct clk_parent_data gcc_parent_data_30[] = {
+	{ .index = DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC },
+	{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
+};
+
+static const struct parent_map gcc_parent_map_31[] = {
+	{ P_QUSB4PHY_2_GCC_USB4_RX0_CLK, 0 },
+	{ P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_31[] = {
+	{ .index = DT_QUSB4PHY_2_GCC_USB4_RX0_CLK },
+	{ .index = DT_BI_TCXO },
+};
+
+static const struct parent_map gcc_parent_map_32[] = {
+	{ P_QUSB4PHY_2_GCC_USB4_RX1_CLK, 0 },
+	{ P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_32[] = {
+	{ .index = DT_QUSB4PHY_2_GCC_USB4_RX1_CLK },
+	{ .index = DT_BI_TCXO },
+};
+
+static const struct parent_map gcc_parent_map_33[] = {
+	{ P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
+	{ P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_33[] = {
+	{ .index = DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC },
+	{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp0_clk_src = {
+	.reg = 0x9f06c,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_0_phy_dp0_clk_src",
+			.parent_data = gcc_parent_data_13,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp1_clk_src = {
+	.reg = 0x9f114,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_0_phy_dp1_clk_src",
+			.parent_data = gcc_parent_data_14,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_0_phy_p2rr2p_pipe_clk_src = {
+	.reg = 0x9f0d4,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_0_phy_p2rr2p_pipe_clk_src",
+			.parent_data = gcc_parent_data_15,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_0_phy_pcie_pipe_mux_clk_src = {
+	.reg = 0x9f104,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_0_phy_pcie_pipe_mux_clk_src",
+			.parent_data = gcc_parent_data_16,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_0_phy_rx0_clk_src = {
+	.reg = 0x9f0ac,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_0_phy_rx0_clk_src",
+			.parent_data = gcc_parent_data_17,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_0_phy_rx1_clk_src = {
+	.reg = 0x9f0bc,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_0_phy_rx1_clk_src",
+			.parent_data = gcc_parent_data_18,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_0_phy_sys_clk_src = {
+	.reg = 0x9f0e4,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_0_phy_sys_clk_src",
+			.parent_data = gcc_parent_data_19,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_1_phy_dp0_clk_src = {
+	.reg = 0x2b06c,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_1_phy_dp0_clk_src",
+			.parent_data = gcc_parent_data_20,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_1_phy_dp1_clk_src = {
+	.reg = 0x2b114,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_1_phy_dp1_clk_src",
+			.parent_data = gcc_parent_data_21,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_1_phy_p2rr2p_pipe_clk_src = {
+	.reg = 0x2b0d4,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk_src",
+			.parent_data = gcc_parent_data_22,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_1_phy_pcie_pipe_mux_clk_src = {
+	.reg = 0x2b104,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_1_phy_pcie_pipe_mux_clk_src",
+			.parent_data = gcc_parent_data_23,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_1_phy_rx0_clk_src = {
+	.reg = 0x2b0ac,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_1_phy_rx0_clk_src",
+			.parent_data = gcc_parent_data_24,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_1_phy_rx1_clk_src = {
+	.reg = 0x2b0bc,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_1_phy_rx1_clk_src",
+			.parent_data = gcc_parent_data_25,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_1_phy_sys_clk_src = {
+	.reg = 0x2b0e4,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_1_phy_sys_clk_src",
+			.parent_data = gcc_parent_data_26,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_2_phy_dp0_clk_src = {
+	.reg = 0x1106c,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_2_phy_dp0_clk_src",
+			.parent_data = gcc_parent_data_27,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_2_phy_dp1_clk_src = {
+	.reg = 0x11114,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_2_phy_dp1_clk_src",
+			.parent_data = gcc_parent_data_28,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_2_phy_p2rr2p_pipe_clk_src = {
+	.reg = 0x110d4,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_2_phy_p2rr2p_pipe_clk_src",
+			.parent_data = gcc_parent_data_29,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_2_phy_pcie_pipe_mux_clk_src = {
+	.reg = 0x11104,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_2_phy_pcie_pipe_mux_clk_src",
+			.parent_data = gcc_parent_data_30,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_2_phy_rx0_clk_src = {
+	.reg = 0x110ac,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_2_phy_rx0_clk_src",
+			.parent_data = gcc_parent_data_31,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_2_phy_rx1_clk_src = {
+	.reg = 0x110bc,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_2_phy_rx1_clk_src",
+			.parent_data = gcc_parent_data_32,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_usb4_2_phy_sys_clk_src = {
+	.reg = 0x110e4,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb4_2_phy_sys_clk_src",
+			.parent_data = gcc_parent_data_33,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
 static struct clk_rcg2 gcc_gp1_clk_src = {
 	.cmd_rcgr = 0x64004,
 	.mnd_width = 16,
@@ -2790,6 +3288,11 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
 		.enable_mask = BIT(25),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_pcie_0_pipe_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -2879,6 +3382,11 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
 		.enable_mask = BIT(30),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_pcie_1_pipe_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -2968,6 +3476,11 @@ static struct clk_branch gcc_pcie_2_pipe_clk = {
 		.enable_mask = BIT(23),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_pcie_2_pipe_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5156,6 +5669,33 @@ static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
 	},
 };
 
+static const struct parent_map gcc_parent_map_34[] = {
+	{ P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 },
+	{ P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
+	{ P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 3 },
+};
+
+static const struct clk_parent_data gcc_parent_data_34[] = {
+	{ .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw },
+	{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
+	{ .index = DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC },
+};
+
+static struct clk_regmap_mux gcc_usb34_prim_phy_pipe_clk_src = {
+	.reg = 0x39070,
+	.shift = 0,
+	.width = 2,
+	.parent_map = gcc_parent_map_34,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb34_prim_phy_pipe_clk_src",
+			.parent_data = gcc_parent_data_34,
+			.num_parents = ARRAY_SIZE(gcc_parent_data_34),
+			.ops = &clk_regmap_mux_closest_ops,
+		},
+	},
+};
+
 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
 	.halt_reg = 0x39068,
 	.halt_check = BRANCH_HALT_SKIP,
@@ -5167,7 +5707,7 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb3_prim_phy_pipe_clk",
 			.parent_hws = (const struct clk_hw*[]) {
-				&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
+				&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -5227,6 +5767,33 @@ static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
 	},
 };
 
+static const struct parent_map gcc_parent_map_35[] = {
+	{ P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 },
+	{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
+	{ P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 3 },
+};
+
+static const struct clk_parent_data gcc_parent_data_35[] = {
+	{ .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw },
+	{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
+	{ .index = DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC },
+};
+
+static struct clk_regmap_mux gcc_usb34_sec_phy_pipe_clk_src = {
+	.reg = 0xa1070,
+	.shift = 0,
+	.width = 2,
+	.parent_map = gcc_parent_map_35,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb34_sec_phy_pipe_clk_src",
+			.parent_data = gcc_parent_data_35,
+			.num_parents = ARRAY_SIZE(gcc_parent_data_35),
+			.ops = &clk_regmap_mux_closest_ops,
+		},
+	},
+};
+
 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
 	.halt_reg = 0xa1068,
 	.halt_check = BRANCH_HALT_SKIP,
@@ -5238,7 +5805,7 @@ static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb3_sec_phy_pipe_clk",
 			.parent_hws = (const struct clk_hw*[]) {
-				&gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
+				&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -5298,6 +5865,33 @@ static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src = {
 	},
 };
 
+static const struct parent_map gcc_parent_map_36[] = {
+	{ P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, 0 },
+	{ P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
+	{ P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 3 },
+};
+
+static const struct clk_parent_data gcc_parent_data_36[] = {
+	{ .hw = &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw },
+	{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
+	{ .index = DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC },
+};
+
+static struct clk_regmap_mux gcc_usb34_tert_phy_pipe_clk_src = {
+	.reg = 0xa2070,
+	.shift = 0,
+	.width = 2,
+	.parent_map = gcc_parent_map_36,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_usb34_tert_phy_pipe_clk_src",
+			.parent_data = gcc_parent_data_36,
+			.num_parents = ARRAY_SIZE(gcc_parent_data_36),
+			.ops = &clk_regmap_mux_closest_ops,
+		},
+	},
+};
+
 static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
 	.halt_reg = 0xa2068,
 	.halt_check = BRANCH_HALT_SKIP,
@@ -5309,7 +5903,7 @@ static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb3_tert_phy_pipe_clk",
 			.parent_hws = (const struct clk_hw*[]) {
-				&gcc_usb3_tert_phy_pipe_clk_src.clkr.hw,
+				&gcc_usb34_tert_phy_pipe_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -5335,12 +5929,17 @@ static struct clk_branch gcc_usb4_0_cfg_ahb_clk = {
 
 static struct clk_branch gcc_usb4_0_dp0_clk = {
 	.halt_reg = 0x9f060,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x9f060,
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_0_dp0_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_0_phy_dp0_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5348,12 +5947,17 @@ static struct clk_branch gcc_usb4_0_dp0_clk = {
 
 static struct clk_branch gcc_usb4_0_dp1_clk = {
 	.halt_reg = 0x9f108,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x9f108,
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_0_dp1_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_0_phy_dp1_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5385,6 +5989,11 @@ static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_0_phy_p2rr2p_pipe_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5398,6 +6007,11 @@ static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = {
 		.enable_mask = BIT(19),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_0_phy_pcie_pipe_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5405,12 +6019,17 @@ static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = {
 
 static struct clk_branch gcc_usb4_0_phy_rx0_clk = {
 	.halt_reg = 0x9f0b0,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x9f0b0,
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_0_phy_rx0_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_0_phy_rx0_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5418,12 +6037,17 @@ static struct clk_branch gcc_usb4_0_phy_rx0_clk = {
 
 static struct clk_branch gcc_usb4_0_phy_rx1_clk = {
 	.halt_reg = 0x9f0c0,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x9f0c0,
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_0_phy_rx1_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_0_phy_rx1_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5439,6 +6063,11 @@ static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_0_phy_usb_pipe_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5470,6 +6099,11 @@ static struct clk_branch gcc_usb4_0_sys_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_0_sys_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_0_phy_sys_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5512,12 +6146,17 @@ static struct clk_branch gcc_usb4_1_cfg_ahb_clk = {
 
 static struct clk_branch gcc_usb4_1_dp0_clk = {
 	.halt_reg = 0x2b060,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x2b060,
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_1_dp0_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_1_phy_dp0_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5525,12 +6164,17 @@ static struct clk_branch gcc_usb4_1_dp0_clk = {
 
 static struct clk_branch gcc_usb4_1_dp1_clk = {
 	.halt_reg = 0x2b108,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x2b108,
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_1_dp1_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_1_phy_dp1_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5562,6 +6206,11 @@ static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5575,6 +6224,11 @@ static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_1_phy_pcie_pipe_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5582,12 +6236,17 @@ static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {
 
 static struct clk_branch gcc_usb4_1_phy_rx0_clk = {
 	.halt_reg = 0x2b0b0,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x2b0b0,
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_1_phy_rx0_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_1_phy_rx0_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5595,12 +6254,17 @@ static struct clk_branch gcc_usb4_1_phy_rx0_clk = {
 
 static struct clk_branch gcc_usb4_1_phy_rx1_clk = {
 	.halt_reg = 0x2b0c0,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x2b0c0,
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_1_phy_rx1_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_1_phy_rx1_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5616,6 +6280,11 @@ static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_1_phy_usb_pipe_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5647,6 +6316,11 @@ static struct clk_branch gcc_usb4_1_sys_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_1_sys_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_1_phy_sys_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5689,12 +6363,17 @@ static struct clk_branch gcc_usb4_2_cfg_ahb_clk = {
 
 static struct clk_branch gcc_usb4_2_dp0_clk = {
 	.halt_reg = 0x11060,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x11060,
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_2_dp0_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_2_phy_dp0_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5702,12 +6381,17 @@ static struct clk_branch gcc_usb4_2_dp0_clk = {
 
 static struct clk_branch gcc_usb4_2_dp1_clk = {
 	.halt_reg = 0x11108,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x11108,
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_2_dp1_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_2_phy_dp1_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5739,6 +6423,11 @@ static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_2_phy_p2rr2p_pipe_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5752,6 +6441,11 @@ static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = {
 		.enable_mask = BIT(1),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_2_phy_pcie_pipe_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5759,12 +6453,17 @@ static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = {
 
 static struct clk_branch gcc_usb4_2_phy_rx0_clk = {
 	.halt_reg = 0x110b0,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x110b0,
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_2_phy_rx0_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_2_phy_rx0_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5772,12 +6471,17 @@ static struct clk_branch gcc_usb4_2_phy_rx0_clk = {
 
 static struct clk_branch gcc_usb4_2_phy_rx1_clk = {
 	.halt_reg = 0x110c0,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x110c0,
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_2_phy_rx1_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb4_2_phy_rx1_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5793,6 +6497,11 @@ static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_usb4_2_phy_usb_pipe_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_usb34_tert_phy_pipe_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -6483,6 +7192,9 @@ static struct clk_regmap *gcc_x1e80100_clocks[] = {
 	[GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] = &gcc_usb30_tert_mock_utmi_clk_src.clkr,
 	[GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr,
 	[GCC_USB30_TERT_SLEEP_CLK] = &gcc_usb30_tert_sleep_clk.clkr,
+	[GCC_USB34_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb34_prim_phy_pipe_clk_src.clkr,
+	[GCC_USB34_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb34_sec_phy_pipe_clk_src.clkr,
+	[GCC_USB34_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb34_tert_phy_pipe_clk_src.clkr,
 	[GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,
 	[GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,
 	[GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,
@@ -6508,11 +7220,18 @@ static struct clk_regmap *gcc_x1e80100_clocks[] = {
 	[GCC_USB4_0_DP1_CLK] = &gcc_usb4_0_dp1_clk.clkr,
 	[GCC_USB4_0_MASTER_CLK] = &gcc_usb4_0_master_clk.clkr,
 	[GCC_USB4_0_MASTER_CLK_SRC] = &gcc_usb4_0_master_clk_src.clkr,
+	[GCC_USB4_0_PHY_DP0_CLK_SRC] = &gcc_usb4_0_phy_dp0_clk_src.clkr,
+	[GCC_USB4_0_PHY_DP1_CLK_SRC] = &gcc_usb4_0_phy_dp1_clk_src.clkr,
 	[GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr,
+	[GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr,
 	[GCC_USB4_0_PHY_PCIE_PIPE_CLK] = &gcc_usb4_0_phy_pcie_pipe_clk.clkr,
 	[GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_clk_src.clkr,
+	[GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr,
 	[GCC_USB4_0_PHY_RX0_CLK] = &gcc_usb4_0_phy_rx0_clk.clkr,
+	[GCC_USB4_0_PHY_RX0_CLK_SRC] = &gcc_usb4_0_phy_rx0_clk_src.clkr,
 	[GCC_USB4_0_PHY_RX1_CLK] = &gcc_usb4_0_phy_rx1_clk.clkr,
+	[GCC_USB4_0_PHY_RX1_CLK_SRC] = &gcc_usb4_0_phy_rx1_clk_src.clkr,
+	[GCC_USB4_0_PHY_SYS_CLK_SRC] = &gcc_usb4_0_phy_sys_clk_src.clkr,
 	[GCC_USB4_0_PHY_USB_PIPE_CLK] = &gcc_usb4_0_phy_usb_pipe_clk.clkr,
 	[GCC_USB4_0_SB_IF_CLK] = &gcc_usb4_0_sb_if_clk.clkr,
 	[GCC_USB4_0_SB_IF_CLK_SRC] = &gcc_usb4_0_sb_if_clk_src.clkr,
@@ -6524,11 +7243,18 @@ static struct clk_regmap *gcc_x1e80100_clocks[] = {
 	[GCC_USB4_1_DP1_CLK] = &gcc_usb4_1_dp1_clk.clkr,
 	[GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr,
 	[GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr,
+	[GCC_USB4_1_PHY_DP0_CLK_SRC] = &gcc_usb4_1_phy_dp0_clk_src.clkr,
+	[GCC_USB4_1_PHY_DP1_CLK_SRC] = &gcc_usb4_1_phy_dp1_clk_src.clkr,
 	[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr,
+	[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr,
 	[GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr,
 	[GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr,
+	[GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr,
 	[GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr,
+	[GCC_USB4_1_PHY_RX0_CLK_SRC] = &gcc_usb4_1_phy_rx0_clk_src.clkr,
 	[GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr,
+	[GCC_USB4_1_PHY_RX1_CLK_SRC] = &gcc_usb4_1_phy_rx1_clk_src.clkr,
+	[GCC_USB4_1_PHY_SYS_CLK_SRC] = &gcc_usb4_1_phy_sys_clk_src.clkr,
 	[GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr,
 	[GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr,
 	[GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr,
@@ -6540,11 +7266,18 @@ static struct clk_regmap *gcc_x1e80100_clocks[] = {
 	[GCC_USB4_2_DP1_CLK] = &gcc_usb4_2_dp1_clk.clkr,
 	[GCC_USB4_2_MASTER_CLK] = &gcc_usb4_2_master_clk.clkr,
 	[GCC_USB4_2_MASTER_CLK_SRC] = &gcc_usb4_2_master_clk_src.clkr,
+	[GCC_USB4_2_PHY_DP0_CLK_SRC] = &gcc_usb4_2_phy_dp0_clk_src.clkr,
+	[GCC_USB4_2_PHY_DP1_CLK_SRC] = &gcc_usb4_2_phy_dp1_clk_src.clkr,
 	[GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr,
+	[GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr,
 	[GCC_USB4_2_PHY_PCIE_PIPE_CLK] = &gcc_usb4_2_phy_pcie_pipe_clk.clkr,
 	[GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_clk_src.clkr,
+	[GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr,
 	[GCC_USB4_2_PHY_RX0_CLK] = &gcc_usb4_2_phy_rx0_clk.clkr,
+	[GCC_USB4_2_PHY_RX0_CLK_SRC] = &gcc_usb4_2_phy_rx0_clk_src.clkr,
 	[GCC_USB4_2_PHY_RX1_CLK] = &gcc_usb4_2_phy_rx1_clk.clkr,
+	[GCC_USB4_2_PHY_RX1_CLK_SRC] = &gcc_usb4_2_phy_rx1_clk_src.clkr,
+	[GCC_USB4_2_PHY_SYS_CLK_SRC] = &gcc_usb4_2_phy_sys_clk_src.clkr,
 	[GCC_USB4_2_PHY_USB_PIPE_CLK] = &gcc_usb4_2_phy_usb_pipe_clk.clkr,
 	[GCC_USB4_2_SB_IF_CLK] = &gcc_usb4_2_sb_if_clk.clkr,
 	[GCC_USB4_2_SB_IF_CLK_SRC] = &gcc_usb4_2_sb_if_clk_src.clkr,
@@ -6660,16 +7393,52 @@ static const struct qcom_reset_map gcc_x1e80100_resets[] = {
 	[GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 },
 	[GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 },
 	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
+	[GCC_USB4PHY_PHY_PRIM_BCR] = { 0x5000c },
 	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 },
+	[GCC_USB4PHY_PHY_SEC_BCR] = { 0x2a00c },
 	[GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 },
+	[GCC_USB4PHY_PHY_TERT_BCR] = { 0xa300c },
 	[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 },
 	[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 },
 	[GCC_USB4_0_BCR] = { 0x9f000 },
 	[GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 },
-	[GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },
-	[GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },
+	[GCC_USB4_0_MISC_USB4_SYS_BCR] = { .reg = 0xad0f8, .bit = 0 },
+	[GCC_USB4_0_MISC_RX_CLK_0_BCR] = { .reg = 0xad0f8, .bit = 1 },
+	[GCC_USB4_0_MISC_RX_CLK_1_BCR] = { .reg = 0xad0f8, .bit = 2 },
+	[GCC_USB4_0_MISC_USB_PIPE_BCR] = { .reg = 0xad0f8, .bit = 3 },
+	[GCC_USB4_0_MISC_PCIE_PIPE_BCR] = { .reg = 0xad0f8, .bit = 4 },
+	[GCC_USB4_0_MISC_TMU_BCR] = { .reg = 0xad0f8, .bit = 5 },
+	[GCC_USB4_0_MISC_SB_IF_BCR] = { .reg = 0xad0f8, .bit = 6 },
+	[GCC_USB4_0_MISC_HIA_MSTR_BCR] = { .reg = 0xad0f8, .bit = 7 },
+	[GCC_USB4_0_MISC_AHB_BCR] = { .reg = 0xad0f8, .bit = 8 },
+	[GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xad0f8, .bit = 9 },
+	[GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xad0f8, .bit = 10 },
 	[GCC_USB4_1_BCR] = { 0x2b000 },
+	[GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },
+	[GCC_USB4_1_MISC_USB4_SYS_BCR] = { .reg = 0xae0f8, .bit = 0 },
+	[GCC_USB4_1_MISC_RX_CLK_0_BCR] = { .reg = 0xae0f8, .bit = 1 },
+	[GCC_USB4_1_MISC_RX_CLK_1_BCR] = { .reg = 0xae0f8, .bit = 2 },
+	[GCC_USB4_1_MISC_USB_PIPE_BCR] = { .reg = 0xae0f8, .bit = 3 },
+	[GCC_USB4_1_MISC_PCIE_PIPE_BCR] = { .reg = 0xae0f8, .bit = 4 },
+	[GCC_USB4_1_MISC_TMU_BCR] = { .reg = 0xae0f8, .bit = 5 },
+	[GCC_USB4_1_MISC_SB_IF_BCR] = { .reg = 0xae0f8, .bit = 6 },
+	[GCC_USB4_1_MISC_HIA_MSTR_BCR] = { .reg = 0xae0f8, .bit = 7 },
+	[GCC_USB4_1_MISC_AHB_BCR] = { .reg = 0xae0f8, .bit = 8 },
+	[GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xae0f8, .bit = 9 },
+	[GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xae0f8, .bit = 10 },
 	[GCC_USB4_2_BCR] = { 0x11000 },
+	[GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },
+	[GCC_USB4_2_MISC_USB4_SYS_BCR] = { .reg = 0xaf0f8, .bit = 0 },
+	[GCC_USB4_2_MISC_RX_CLK_0_BCR] = { .reg = 0xaf0f8, .bit = 1 },
+	[GCC_USB4_2_MISC_RX_CLK_1_BCR] = { .reg = 0xaf0f8, .bit = 2 },
+	[GCC_USB4_2_MISC_USB_PIPE_BCR] = { .reg = 0xaf0f8, .bit = 3 },
+	[GCC_USB4_2_MISC_PCIE_PIPE_BCR] = { .reg = 0xaf0f8, .bit = 4 },
+	[GCC_USB4_2_MISC_TMU_BCR] = { .reg = 0xaf0f8, .bit = 5 },
+	[GCC_USB4_2_MISC_SB_IF_BCR] = { .reg = 0xaf0f8, .bit = 6 },
+	[GCC_USB4_2_MISC_HIA_MSTR_BCR] = { .reg = 0xaf0f8, .bit = 7 },
+	[GCC_USB4_2_MISC_AHB_BCR] = { .reg = 0xaf0f8, .bit = 8 },
+	[GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xaf0f8, .bit = 9 },
+	[GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xaf0f8, .bit = 10 },
 	[GCC_USB_0_PHY_BCR] = { 0x50020 },
 	[GCC_USB_1_PHY_BCR] = { 0x2a020 },
 	[GCC_USB_2_PHY_BCR] = { 0xa3020 },

-- 
2.51.0

[PATCH 3/3] arm64: dts: qcom: x1e80100: Extend the gcc input clock list

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

With the recent dt-bindings update, the missing USB4 clocks have been
added.

Extend the existing list to make sure the DT contains the expected
amount of 'clocks' entries.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 51576d9c935decbc61a8e4200de83e739f7da814..cc76b9933a9bbff396ec4739f4a1dd3d2cc81f0f 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -807,7 +807,34 @@ gcc: clock-controller@100000 {
 				 <0>,
 				 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 				 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
-				 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
+				 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>;
 
 			power-domains = <&rpmhpd RPMHPD_CX>;
 			#clock-cells = <1>;

-- 
2.51.0

Re: [PATCH 1/3] dt-bindings: clock: qcom,x1e80100-gcc: Add missing USB4 clocks/resets

[Bryan O'Donoghue]

On 26/09/2025 13:03, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Some of the USB4 muxes, RCGs and resets were not initially described.
> 
> Add indices for them to allow extending the driver.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
>   .../bindings/clock/qcom,x1e80100-gcc.yaml          | 62 ++++++++++++++++++++--
>   include/dt-bindings/clock/qcom,x1e80100-gcc.h      | 61 +++++++++++++++++++++
>   2 files changed, 119 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
> index 68dde0720c711320aa0e7c74040cf3c4422dda72..1b15b507095455c93b1ba39404cafbb6f96be5a9 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
> @@ -32,9 +32,36 @@ properties:
>         - description: PCIe 5 pipe clock
>         - description: PCIe 6a pipe clock
>         - description: PCIe 6b pipe clock
> -      - description: USB QMP Phy 0 clock source
> -      - description: USB QMP Phy 1 clock source
> -      - description: USB QMP Phy 2 clock source
> +      - description: USB4_0 QMPPHY clock source
> +      - description: USB4_1 QMPPHY clock source
> +      - description: USB4_2 QMPPHY clock source
> +      - description: USB4_0 PHY DP0 GMUX clock source
> +      - description: USB4_0 PHY DP1 GMUX clock source
> +      - description: USB4_0 PHY PCIE PIPEGMUX clock source
> +      - description: USB4_0 PHY PIPEGMUX clock source
> +      - description: USB4_0 PHY SYS PCIE PIPEGMUX clock source
> +      - description: USB4_1 PHY DP0 GMUX 2 clock source
> +      - description: USB4_1 PHY DP1 GMUX 2 clock source
> +      - description: USB4_1 PHY PCIE PIPEGMUX clock source
> +      - description: USB4_1 PHY PIPEGMUX clock source
> +      - description: USB4_1 PHY SYS PCIE PIPEGMUX clock source
> +      - description: USB4_2 PHY DP0 GMUX 2 clock source
> +      - description: USB4_2 PHY DP1 GMUX 2 clock source
> +      - description: USB4_2 PHY PCIE PIPEGMUX clock source
> +      - description: USB4_2 PHY PIPEGMUX clock source
> +      - description: USB4_2 PHY SYS PCIE PIPEGMUX clock source
> +      - description: USB4_0 PHY RX 0 clock source
> +      - description: USB4_0 PHY RX 1 clock source
> +      - description: USB4_1 PHY RX 0 clock source
> +      - description: USB4_1 PHY RX 1 clock source
> +      - description: USB4_2 PHY RX 0 clock source
> +      - description: USB4_2 PHY RX 1 clock source
> +      - description: USB4_0 PHY PCIE PIPE clock source
> +      - description: USB4_0 PHY max PIPE clock source
> +      - description: USB4_1 PHY PCIE PIPE clock source
> +      - description: USB4_1 PHY max PIPE clock source
> +      - description: USB4_2 PHY PCIE PIPE clock source
> +      - description: USB4_2 PHY max PIPE clock source
>   
>     power-domains:
>       description:
> @@ -67,7 +94,34 @@ examples:
>                  <&pcie6b_phy>,
>                  <&usb_1_ss0_qmpphy 0>,
>                  <&usb_1_ss1_qmpphy 1>,
> -               <&usb_1_ss2_qmpphy 2>;
> +               <&usb_1_ss2_qmpphy 2>,
> +               <&usb4_0_phy_dp0_gmux_clk>,
> +               <&usb4_0_phy_dp1_gmux_clk>,
> +               <&usb4_0_phy_pcie_pipegmux_clk>,
> +               <&usb4_0_phy_pipegmux_clk>,
> +               <&usb4_0_phy_sys_pcie_pipegmux_clk>,
> +               <&usb4_1_phy_dp0_gmux_2_clk>,
> +               <&usb4_1_phy_dp1_gmux_2_clk>,
> +               <&usb4_1_phy_pcie_pipegmux_clk>,
> +               <&usb4_1_phy_pipegmux_clk>,
> +               <&usb4_1_phy_sys_pcie_pipegmux_clk>,
> +               <&usb4_2_phy_dp0_gmux_2_clk>,
> +               <&usb4_2_phy_dp1_gmux_2_clk>,
> +               <&usb4_2_phy_pcie_pipegmux_clk>,
> +               <&usb4_2_phy_pipegmux_clk>,
> +               <&usb4_2_phy_sys_pcie_pipegmux_clk>,
> +               <&usb4_0_phy_rx_0_clk>,
> +               <&usb4_0_phy_rx_1_clk>,
> +               <&usb4_1_phy_rx_0_clk>,
> +               <&usb4_1_phy_rx_1_clk>,
> +               <&usb4_2_phy_rx_0_clk>,
> +               <&usb4_2_phy_rx_1_clk>,
> +               <&usb4_0_phy_pcie_pipe_clk>,
> +               <&usb4_0_phy_max_pipe_clk>,
> +               <&usb4_1_phy_pcie_pipe_clk>,
> +               <&usb4_1_phy_max_pipe_clk>,
> +               <&usb4_2_phy_pcie_pipe_clk>,
> +               <&usb4_2_phy_max_pipe_clk>;
>         power-domains = <&rpmhpd RPMHPD_CX>;
>         #clock-cells = <1>;
>         #reset-cells = <1>;
> diff --git a/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
> index 710c340f24a57d799ac04650fbe9d4ea0f294bde..62aa1242559270dd3bd31cd10322ee265468b8e4 100644
> --- a/include/dt-bindings/clock/qcom,x1e80100-gcc.h
> +++ b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
> @@ -363,6 +363,30 @@
>   #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				353
>   #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC				354
>   #define GCC_USB3_TERT_PHY_PIPE_CLK_SRC				355
> +#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC				356
> +#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC				357
> +#define GCC_USB34_TERT_PHY_PIPE_CLK_SRC				358
> +#define GCC_USB4_0_PHY_DP0_CLK_SRC				359
> +#define GCC_USB4_0_PHY_DP1_CLK_SRC				360
> +#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC			361
> +#define GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC			362
> +#define GCC_USB4_0_PHY_RX0_CLK_SRC				363
> +#define GCC_USB4_0_PHY_RX1_CLK_SRC				364
> +#define GCC_USB4_0_PHY_SYS_CLK_SRC				365
> +#define GCC_USB4_1_PHY_DP0_CLK_SRC				366
> +#define GCC_USB4_1_PHY_DP1_CLK_SRC				367
> +#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC			368
> +#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC			369
> +#define GCC_USB4_1_PHY_RX0_CLK_SRC				370
> +#define GCC_USB4_1_PHY_RX1_CLK_SRC				371
> +#define GCC_USB4_1_PHY_SYS_CLK_SRC				372
> +#define GCC_USB4_2_PHY_DP0_CLK_SRC				373
> +#define GCC_USB4_2_PHY_DP1_CLK_SRC				374
> +#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC			375
> +#define GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC			376
> +#define GCC_USB4_2_PHY_RX0_CLK_SRC				377
> +#define GCC_USB4_2_PHY_RX1_CLK_SRC				378
> +#define GCC_USB4_2_PHY_SYS_CLK_SRC				379
>   
>   /* GCC power domains */
>   #define GCC_PCIE_0_TUNNEL_GDSC					0
> @@ -484,4 +508,41 @@
>   #define GCC_VIDEO_BCR						87
>   #define GCC_VIDEO_AXI0_CLK_ARES					88
>   #define GCC_VIDEO_AXI1_CLK_ARES					89
> +#define GCC_USB4_0_MISC_USB4_SYS_BCR				90
> +#define GCC_USB4_0_MISC_RX_CLK_0_BCR				91
> +#define GCC_USB4_0_MISC_RX_CLK_1_BCR				92
> +#define GCC_USB4_0_MISC_USB_PIPE_BCR				93
> +#define GCC_USB4_0_MISC_PCIE_PIPE_BCR				94
> +#define GCC_USB4_0_MISC_TMU_BCR					95
> +#define GCC_USB4_0_MISC_SB_IF_BCR				96
> +#define GCC_USB4_0_MISC_HIA_MSTR_BCR				97
> +#define GCC_USB4_0_MISC_AHB_BCR					98
> +#define GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR			99
> +#define GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR			100
> +#define GCC_USB4_1_MISC_USB4_SYS_BCR				101
> +#define GCC_USB4_1_MISC_RX_CLK_0_BCR				102
> +#define GCC_USB4_1_MISC_RX_CLK_1_BCR				103
> +#define GCC_USB4_1_MISC_USB_PIPE_BCR				104
> +#define GCC_USB4_1_MISC_PCIE_PIPE_BCR				105
> +#define GCC_USB4_1_MISC_TMU_BCR					106
> +#define GCC_USB4_1_MISC_SB_IF_BCR				107
> +#define GCC_USB4_1_MISC_HIA_MSTR_BCR				108
> +#define GCC_USB4_1_MISC_AHB_BCR					109
> +#define GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR			110
> +#define GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR			111
> +#define GCC_USB4_2_MISC_USB4_SYS_BCR				112
> +#define GCC_USB4_2_MISC_RX_CLK_0_BCR				113
> +#define GCC_USB4_2_MISC_RX_CLK_1_BCR				114
> +#define GCC_USB4_2_MISC_USB_PIPE_BCR				115
> +#define GCC_USB4_2_MISC_PCIE_PIPE_BCR				116
> +#define GCC_USB4_2_MISC_TMU_BCR					117
> +#define GCC_USB4_2_MISC_SB_IF_BCR				118
> +#define GCC_USB4_2_MISC_HIA_MSTR_BCR				119
> +#define GCC_USB4_2_MISC_AHB_BCR					120
> +#define GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR			121
> +#define GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR			122
> +#define GCC_USB4PHY_PHY_PRIM_BCR				123
> +#define GCC_USB4PHY_PHY_SEC_BCR					124
> +#define GCC_USB4PHY_PHY_TERT_BCR				125
> +
>   #endif
> 
Reviewed-by: Bryan O'Donoghue <bod@kernel.org>

Re: [PATCH 2/3] clk: qcom: gcc-x1e80100: Add missing USB4 clocks/resets

[Bryan O'Donoghue]

On 26/09/2025 13:03, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Currently, some of the USB4 clocks/resets are described, but not all
> of the back-end muxes are present. Configuring them properly is
> necessary for proper operation of the hardware.
> 
> Add all the resets & muxes and wire up any unaccounted USB4 clock paths.
> 
> Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
>   drivers/clk/qcom/gcc-x1e80100.c | 803 +++++++++++++++++++++++++++++++++++++++-
>   1 file changed, 786 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
> index 301fc9fc32d8e6e1ddf59c1d3350d84f6c06e4b6..1f866fb4a53ad4cca51d586e92aa96acab58ef0b 100644
> --- a/drivers/clk/qcom/gcc-x1e80100.c
> +++ b/drivers/clk/qcom/gcc-x1e80100.c
> @@ -32,6 +32,33 @@ enum {
>   	DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE,
>   	DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE,
>   	DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE,
> +	DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC,
> +	DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC,
> +	DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC,
> +	DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC,
> +	DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC,
> +	DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC,
> +	DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC,
> +	DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
> +	DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
> +	DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
> +	DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC,
> +	DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC,
> +	DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC,
> +	DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC,
> +	DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC,
> +	DT_QUSB4PHY_0_GCC_USB4_RX0_CLK,
> +	DT_QUSB4PHY_0_GCC_USB4_RX1_CLK,
> +	DT_QUSB4PHY_1_GCC_USB4_RX0_CLK,
> +	DT_QUSB4PHY_1_GCC_USB4_RX1_CLK,
> +	DT_QUSB4PHY_2_GCC_USB4_RX0_CLK,
> +	DT_QUSB4PHY_2_GCC_USB4_RX1_CLK,
> +	DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK,
> +	DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
> +	DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
> +	DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
> +	DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
> +	DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
>   };
>   
>   enum {
> @@ -42,10 +69,40 @@ enum {
>   	P_GCC_GPLL7_OUT_MAIN,
>   	P_GCC_GPLL8_OUT_MAIN,
>   	P_GCC_GPLL9_OUT_MAIN,
> +	P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC,
> +	P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC,
> +	P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC,
> +	P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC,
> +	P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC,
> +	P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC,
> +	P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC,
> +	P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC,
> +	P_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC,
> +	P_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC,
> +	P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
> +	P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
> +	P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
> +	P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC,
> +	P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC,
> +	P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC,
> +	P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC,
> +	P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC,
> +	P_QUSB4PHY_0_GCC_USB4_RX0_CLK,
> +	P_QUSB4PHY_0_GCC_USB4_RX1_CLK,
> +	P_QUSB4PHY_1_GCC_USB4_RX0_CLK,
> +	P_QUSB4PHY_1_GCC_USB4_RX1_CLK,
> +	P_QUSB4PHY_2_GCC_USB4_RX0_CLK,
> +	P_QUSB4PHY_2_GCC_USB4_RX1_CLK,
>   	P_SLEEP_CLK,
>   	P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK,
>   	P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK,
>   	P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK,
> +	P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK,
> +	P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
> +	P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
> +	P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
> +	P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
> +	P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
>   };
>   
>   static struct clk_alpha_pll gcc_gpll0 = {
> @@ -320,6 +377,447 @@ static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
>   	{ }
>   };
>   
> +static const struct parent_map gcc_parent_map_13[] = {
> +	{ P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC, 0 },
> +	{ P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_13[] = {
> +	{ .index = DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC },
> +	{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_14[] = {
> +	{ P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC, 0 },
> +	{ P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_14[] = {
> +	{ .index = DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC },
> +	{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_15[] = {
> +	{ P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
> +	{ P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_15[] = {
> +	{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
> +	{ .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_16[] = {
> +	{ P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
> +	{ P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_16[] = {
> +	{ .index = DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC },
> +	{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_17[] = {
> +	{ P_QUSB4PHY_0_GCC_USB4_RX0_CLK, 0 },
> +	{ P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_17[] = {
> +	{ .index = DT_QUSB4PHY_0_GCC_USB4_RX0_CLK },
> +	{ .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_18[] = {
> +	{ P_QUSB4PHY_0_GCC_USB4_RX1_CLK, 0 },
> +	{ P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_18[] = {
> +	{ .index = DT_QUSB4PHY_0_GCC_USB4_RX1_CLK },
> +	{ .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_19[] = {
> +	{ P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
> +	{ P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_19[] = {
> +	{ .index = DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC },
> +	{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_20[] = {
> +	{ P_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC, 0 },
> +	{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_20[] = {
> +	{ .index = DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC },
> +	{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_21[] = {
> +	{ P_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC, 0 },
> +	{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_21[] = {
> +	{ .index = DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC },
> +	{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_22[] = {
> +	{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
> +	{ P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_22[] = {
> +	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
> +	{ .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_23[] = {
> +	{ P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
> +	{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_23[] = {
> +	{ .index = DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC },
> +	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_24[] = {
> +	{ P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 0 },
> +	{ P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_24[] = {
> +	{ .index = DT_QUSB4PHY_1_GCC_USB4_RX0_CLK },
> +	{ .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_25[] = {
> +	{ P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 0 },
> +	{ P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_25[] = {
> +	{ .index = DT_QUSB4PHY_1_GCC_USB4_RX1_CLK },
> +	{ .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_26[] = {
> +	{ P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
> +	{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_26[] = {
> +	{ .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC },
> +	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_27[] = {
> +	{ P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC, 0 },
> +	{ P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_27[] = {
> +	{ .index = DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC },
> +	{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_28[] = {
> +	{ P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC, 0 },
> +	{ P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_28[] = {
> +	{ .index = DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC },
> +	{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_29[] = {
> +	{ P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
> +	{ P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_29[] = {
> +	{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
> +	{ .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_30[] = {
> +	{ P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
> +	{ P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_30[] = {
> +	{ .index = DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC },
> +	{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_31[] = {
> +	{ P_QUSB4PHY_2_GCC_USB4_RX0_CLK, 0 },
> +	{ P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_31[] = {
> +	{ .index = DT_QUSB4PHY_2_GCC_USB4_RX0_CLK },
> +	{ .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_32[] = {
> +	{ P_QUSB4PHY_2_GCC_USB4_RX1_CLK, 0 },
> +	{ P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_32[] = {
> +	{ .index = DT_QUSB4PHY_2_GCC_USB4_RX1_CLK },
> +	{ .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_33[] = {
> +	{ P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
> +	{ P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_33[] = {
> +	{ .index = DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC },
> +	{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp0_clk_src = {
> +	.reg = 0x9f06c,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_0_phy_dp0_clk_src",
> +			.parent_data = gcc_parent_data_13,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp1_clk_src = {
> +	.reg = 0x9f114,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_0_phy_dp1_clk_src",
> +			.parent_data = gcc_parent_data_14,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_0_phy_p2rr2p_pipe_clk_src = {
> +	.reg = 0x9f0d4,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_0_phy_p2rr2p_pipe_clk_src",
> +			.parent_data = gcc_parent_data_15,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_0_phy_pcie_pipe_mux_clk_src = {
> +	.reg = 0x9f104,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_0_phy_pcie_pipe_mux_clk_src",
> +			.parent_data = gcc_parent_data_16,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_0_phy_rx0_clk_src = {
> +	.reg = 0x9f0ac,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_0_phy_rx0_clk_src",
> +			.parent_data = gcc_parent_data_17,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_0_phy_rx1_clk_src = {
> +	.reg = 0x9f0bc,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_0_phy_rx1_clk_src",
> +			.parent_data = gcc_parent_data_18,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_0_phy_sys_clk_src = {
> +	.reg = 0x9f0e4,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_0_phy_sys_clk_src",
> +			.parent_data = gcc_parent_data_19,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_1_phy_dp0_clk_src = {
> +	.reg = 0x2b06c,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_1_phy_dp0_clk_src",
> +			.parent_data = gcc_parent_data_20,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_1_phy_dp1_clk_src = {
> +	.reg = 0x2b114,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_1_phy_dp1_clk_src",
> +			.parent_data = gcc_parent_data_21,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_1_phy_p2rr2p_pipe_clk_src = {
> +	.reg = 0x2b0d4,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk_src",
> +			.parent_data = gcc_parent_data_22,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_1_phy_pcie_pipe_mux_clk_src = {
> +	.reg = 0x2b104,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_1_phy_pcie_pipe_mux_clk_src",
> +			.parent_data = gcc_parent_data_23,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_1_phy_rx0_clk_src = {
> +	.reg = 0x2b0ac,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_1_phy_rx0_clk_src",
> +			.parent_data = gcc_parent_data_24,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_1_phy_rx1_clk_src = {
> +	.reg = 0x2b0bc,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_1_phy_rx1_clk_src",
> +			.parent_data = gcc_parent_data_25,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_1_phy_sys_clk_src = {
> +	.reg = 0x2b0e4,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_1_phy_sys_clk_src",
> +			.parent_data = gcc_parent_data_26,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_2_phy_dp0_clk_src = {
> +	.reg = 0x1106c,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_2_phy_dp0_clk_src",
> +			.parent_data = gcc_parent_data_27,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_2_phy_dp1_clk_src = {
> +	.reg = 0x11114,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_2_phy_dp1_clk_src",
> +			.parent_data = gcc_parent_data_28,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_2_phy_p2rr2p_pipe_clk_src = {
> +	.reg = 0x110d4,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_2_phy_p2rr2p_pipe_clk_src",
> +			.parent_data = gcc_parent_data_29,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_2_phy_pcie_pipe_mux_clk_src = {
> +	.reg = 0x11104,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_2_phy_pcie_pipe_mux_clk_src",
> +			.parent_data = gcc_parent_data_30,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_2_phy_rx0_clk_src = {
> +	.reg = 0x110ac,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_2_phy_rx0_clk_src",
> +			.parent_data = gcc_parent_data_31,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_2_phy_rx1_clk_src = {
> +	.reg = 0x110bc,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_2_phy_rx1_clk_src",
> +			.parent_data = gcc_parent_data_32,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_usb4_2_phy_sys_clk_src = {
> +	.reg = 0x110e4,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb4_2_phy_sys_clk_src",
> +			.parent_data = gcc_parent_data_33,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
>   static struct clk_rcg2 gcc_gp1_clk_src = {
>   	.cmd_rcgr = 0x64004,
>   	.mnd_width = 16,
> @@ -2790,6 +3288,11 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
>   		.enable_mask = BIT(25),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_pcie_0_pipe_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -2879,6 +3382,11 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
>   		.enable_mask = BIT(30),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_pcie_1_pipe_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -2968,6 +3476,11 @@ static struct clk_branch gcc_pcie_2_pipe_clk = {
>   		.enable_mask = BIT(23),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_pcie_2_pipe_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5156,6 +5669,33 @@ static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
>   	},
>   };
>   
> +static const struct parent_map gcc_parent_map_34[] = {
> +	{ P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 },
> +	{ P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
> +	{ P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 3 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_34[] = {
> +	{ .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw },
> +	{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
> +	{ .index = DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC },
> +};
> +
> +static struct clk_regmap_mux gcc_usb34_prim_phy_pipe_clk_src = {
> +	.reg = 0x39070,
> +	.shift = 0,
> +	.width = 2,
> +	.parent_map = gcc_parent_map_34,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb34_prim_phy_pipe_clk_src",
> +			.parent_data = gcc_parent_data_34,
> +			.num_parents = ARRAY_SIZE(gcc_parent_data_34),
> +			.ops = &clk_regmap_mux_closest_ops,
> +		},
> +	},
> +};
> +
>   static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
>   	.halt_reg = 0x39068,
>   	.halt_check = BRANCH_HALT_SKIP,
> @@ -5167,7 +5707,7 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb3_prim_phy_pipe_clk",
>   			.parent_hws = (const struct clk_hw*[]) {
> -				&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
> +				&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
>   			},
>   			.num_parents = 1,
>   			.flags = CLK_SET_RATE_PARENT,
> @@ -5227,6 +5767,33 @@ static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
>   	},
>   };
>   
> +static const struct parent_map gcc_parent_map_35[] = {
> +	{ P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 },
> +	{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
> +	{ P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 3 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_35[] = {
> +	{ .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw },
> +	{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
> +	{ .index = DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC },
> +};
> +
> +static struct clk_regmap_mux gcc_usb34_sec_phy_pipe_clk_src = {
> +	.reg = 0xa1070,
> +	.shift = 0,
> +	.width = 2,
> +	.parent_map = gcc_parent_map_35,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb34_sec_phy_pipe_clk_src",
> +			.parent_data = gcc_parent_data_35,
> +			.num_parents = ARRAY_SIZE(gcc_parent_data_35),
> +			.ops = &clk_regmap_mux_closest_ops,
> +		},
> +	},
> +};
> +
>   static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
>   	.halt_reg = 0xa1068,
>   	.halt_check = BRANCH_HALT_SKIP,
> @@ -5238,7 +5805,7 @@ static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb3_sec_phy_pipe_clk",
>   			.parent_hws = (const struct clk_hw*[]) {
> -				&gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
> +				&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
>   			},
>   			.num_parents = 1,
>   			.flags = CLK_SET_RATE_PARENT,
> @@ -5298,6 +5865,33 @@ static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src = {
>   	},
>   };
>   
> +static const struct parent_map gcc_parent_map_36[] = {
> +	{ P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, 0 },
> +	{ P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
> +	{ P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 3 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_36[] = {
> +	{ .hw = &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw },
> +	{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
> +	{ .index = DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC },
> +};
> +
> +static struct clk_regmap_mux gcc_usb34_tert_phy_pipe_clk_src = {
> +	.reg = 0xa2070,
> +	.shift = 0,
> +	.width = 2,
> +	.parent_map = gcc_parent_map_36,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_usb34_tert_phy_pipe_clk_src",
> +			.parent_data = gcc_parent_data_36,
> +			.num_parents = ARRAY_SIZE(gcc_parent_data_36),
> +			.ops = &clk_regmap_mux_closest_ops,
> +		},
> +	},
> +};
> +
>   static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
>   	.halt_reg = 0xa2068,
>   	.halt_check = BRANCH_HALT_SKIP,
> @@ -5309,7 +5903,7 @@ static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb3_tert_phy_pipe_clk",
>   			.parent_hws = (const struct clk_hw*[]) {
> -				&gcc_usb3_tert_phy_pipe_clk_src.clkr.hw,
> +				&gcc_usb34_tert_phy_pipe_clk_src.clkr.hw,
>   			},
>   			.num_parents = 1,
>   			.flags = CLK_SET_RATE_PARENT,
> @@ -5335,12 +5929,17 @@ static struct clk_branch gcc_usb4_0_cfg_ahb_clk = {
>   
>   static struct clk_branch gcc_usb4_0_dp0_clk = {
>   	.halt_reg = 0x9f060,
> -	.halt_check = BRANCH_HALT,
> +	.halt_check = BRANCH_HALT_SKIP,
>   	.clkr = {
>   		.enable_reg = 0x9f060,
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_0_dp0_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_0_phy_dp0_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5348,12 +5947,17 @@ static struct clk_branch gcc_usb4_0_dp0_clk = {
>   
>   static struct clk_branch gcc_usb4_0_dp1_clk = {
>   	.halt_reg = 0x9f108,
> -	.halt_check = BRANCH_HALT,
> +	.halt_check = BRANCH_HALT_SKIP,
>   	.clkr = {
>   		.enable_reg = 0x9f108,
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_0_dp1_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_0_phy_dp1_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5385,6 +5989,11 @@ static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = {
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_0_phy_p2rr2p_pipe_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5398,6 +6007,11 @@ static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = {
>   		.enable_mask = BIT(19),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_0_phy_pcie_pipe_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5405,12 +6019,17 @@ static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = {
>   
>   static struct clk_branch gcc_usb4_0_phy_rx0_clk = {
>   	.halt_reg = 0x9f0b0,
> -	.halt_check = BRANCH_HALT,
> +	.halt_check = BRANCH_HALT_SKIP,
>   	.clkr = {
>   		.enable_reg = 0x9f0b0,
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_0_phy_rx0_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_0_phy_rx0_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5418,12 +6037,17 @@ static struct clk_branch gcc_usb4_0_phy_rx0_clk = {
>   
>   static struct clk_branch gcc_usb4_0_phy_rx1_clk = {
>   	.halt_reg = 0x9f0c0,
> -	.halt_check = BRANCH_HALT,
> +	.halt_check = BRANCH_HALT_SKIP,
>   	.clkr = {
>   		.enable_reg = 0x9f0c0,
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_0_phy_rx1_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_0_phy_rx1_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5439,6 +6063,11 @@ static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = {
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_0_phy_usb_pipe_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5470,6 +6099,11 @@ static struct clk_branch gcc_usb4_0_sys_clk = {
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_0_sys_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_0_phy_sys_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5512,12 +6146,17 @@ static struct clk_branch gcc_usb4_1_cfg_ahb_clk = {
>   
>   static struct clk_branch gcc_usb4_1_dp0_clk = {
>   	.halt_reg = 0x2b060,
> -	.halt_check = BRANCH_HALT,
> +	.halt_check = BRANCH_HALT_SKIP,
>   	.clkr = {
>   		.enable_reg = 0x2b060,
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_1_dp0_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_1_phy_dp0_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5525,12 +6164,17 @@ static struct clk_branch gcc_usb4_1_dp0_clk = {
>   
>   static struct clk_branch gcc_usb4_1_dp1_clk = {
>   	.halt_reg = 0x2b108,
> -	.halt_check = BRANCH_HALT,
> +	.halt_check = BRANCH_HALT_SKIP,
>   	.clkr = {
>   		.enable_reg = 0x2b108,
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_1_dp1_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_1_phy_dp1_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5562,6 +6206,11 @@ static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5575,6 +6224,11 @@ static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_1_phy_pcie_pipe_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5582,12 +6236,17 @@ static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {
>   
>   static struct clk_branch gcc_usb4_1_phy_rx0_clk = {
>   	.halt_reg = 0x2b0b0,
> -	.halt_check = BRANCH_HALT,
> +	.halt_check = BRANCH_HALT_SKIP,
>   	.clkr = {
>   		.enable_reg = 0x2b0b0,
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_1_phy_rx0_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_1_phy_rx0_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5595,12 +6254,17 @@ static struct clk_branch gcc_usb4_1_phy_rx0_clk = {
>   
>   static struct clk_branch gcc_usb4_1_phy_rx1_clk = {
>   	.halt_reg = 0x2b0c0,
> -	.halt_check = BRANCH_HALT,
> +	.halt_check = BRANCH_HALT_SKIP,
>   	.clkr = {
>   		.enable_reg = 0x2b0c0,
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_1_phy_rx1_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_1_phy_rx1_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5616,6 +6280,11 @@ static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = {
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_1_phy_usb_pipe_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5647,6 +6316,11 @@ static struct clk_branch gcc_usb4_1_sys_clk = {
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_1_sys_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_1_phy_sys_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5689,12 +6363,17 @@ static struct clk_branch gcc_usb4_2_cfg_ahb_clk = {
>   
>   static struct clk_branch gcc_usb4_2_dp0_clk = {
>   	.halt_reg = 0x11060,
> -	.halt_check = BRANCH_HALT,
> +	.halt_check = BRANCH_HALT_SKIP,
>   	.clkr = {
>   		.enable_reg = 0x11060,
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_2_dp0_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_2_phy_dp0_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5702,12 +6381,17 @@ static struct clk_branch gcc_usb4_2_dp0_clk = {
>   
>   static struct clk_branch gcc_usb4_2_dp1_clk = {
>   	.halt_reg = 0x11108,
> -	.halt_check = BRANCH_HALT,
> +	.halt_check = BRANCH_HALT_SKIP,
>   	.clkr = {
>   		.enable_reg = 0x11108,
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_2_dp1_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_2_phy_dp1_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5739,6 +6423,11 @@ static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = {
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_2_phy_p2rr2p_pipe_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5752,6 +6441,11 @@ static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = {
>   		.enable_mask = BIT(1),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_2_phy_pcie_pipe_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5759,12 +6453,17 @@ static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = {
>   
>   static struct clk_branch gcc_usb4_2_phy_rx0_clk = {
>   	.halt_reg = 0x110b0,
> -	.halt_check = BRANCH_HALT,
> +	.halt_check = BRANCH_HALT_SKIP,
>   	.clkr = {
>   		.enable_reg = 0x110b0,
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_2_phy_rx0_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_2_phy_rx0_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5772,12 +6471,17 @@ static struct clk_branch gcc_usb4_2_phy_rx0_clk = {
>   
>   static struct clk_branch gcc_usb4_2_phy_rx1_clk = {
>   	.halt_reg = 0x110c0,
> -	.halt_check = BRANCH_HALT,
> +	.halt_check = BRANCH_HALT_SKIP,
>   	.clkr = {
>   		.enable_reg = 0x110c0,
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_2_phy_rx1_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb4_2_phy_rx1_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -5793,6 +6497,11 @@ static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = {
>   		.enable_mask = BIT(0),
>   		.hw.init = &(const struct clk_init_data) {
>   			.name = "gcc_usb4_2_phy_usb_pipe_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_usb34_tert_phy_pipe_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -6483,6 +7192,9 @@ static struct clk_regmap *gcc_x1e80100_clocks[] = {
>   	[GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] = &gcc_usb30_tert_mock_utmi_clk_src.clkr,
>   	[GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr,
>   	[GCC_USB30_TERT_SLEEP_CLK] = &gcc_usb30_tert_sleep_clk.clkr,
> +	[GCC_USB34_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb34_prim_phy_pipe_clk_src.clkr,
> +	[GCC_USB34_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb34_sec_phy_pipe_clk_src.clkr,
> +	[GCC_USB34_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb34_tert_phy_pipe_clk_src.clkr,
>   	[GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,
>   	[GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,
>   	[GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,
> @@ -6508,11 +7220,18 @@ static struct clk_regmap *gcc_x1e80100_clocks[] = {
>   	[GCC_USB4_0_DP1_CLK] = &gcc_usb4_0_dp1_clk.clkr,
>   	[GCC_USB4_0_MASTER_CLK] = &gcc_usb4_0_master_clk.clkr,
>   	[GCC_USB4_0_MASTER_CLK_SRC] = &gcc_usb4_0_master_clk_src.clkr,
> +	[GCC_USB4_0_PHY_DP0_CLK_SRC] = &gcc_usb4_0_phy_dp0_clk_src.clkr,
> +	[GCC_USB4_0_PHY_DP1_CLK_SRC] = &gcc_usb4_0_phy_dp1_clk_src.clkr,
>   	[GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr,
> +	[GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr,
>   	[GCC_USB4_0_PHY_PCIE_PIPE_CLK] = &gcc_usb4_0_phy_pcie_pipe_clk.clkr,
>   	[GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_clk_src.clkr,
> +	[GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr,
>   	[GCC_USB4_0_PHY_RX0_CLK] = &gcc_usb4_0_phy_rx0_clk.clkr,
> +	[GCC_USB4_0_PHY_RX0_CLK_SRC] = &gcc_usb4_0_phy_rx0_clk_src.clkr,
>   	[GCC_USB4_0_PHY_RX1_CLK] = &gcc_usb4_0_phy_rx1_clk.clkr,
> +	[GCC_USB4_0_PHY_RX1_CLK_SRC] = &gcc_usb4_0_phy_rx1_clk_src.clkr,
> +	[GCC_USB4_0_PHY_SYS_CLK_SRC] = &gcc_usb4_0_phy_sys_clk_src.clkr,
>   	[GCC_USB4_0_PHY_USB_PIPE_CLK] = &gcc_usb4_0_phy_usb_pipe_clk.clkr,
>   	[GCC_USB4_0_SB_IF_CLK] = &gcc_usb4_0_sb_if_clk.clkr,
>   	[GCC_USB4_0_SB_IF_CLK_SRC] = &gcc_usb4_0_sb_if_clk_src.clkr,
> @@ -6524,11 +7243,18 @@ static struct clk_regmap *gcc_x1e80100_clocks[] = {
>   	[GCC_USB4_1_DP1_CLK] = &gcc_usb4_1_dp1_clk.clkr,
>   	[GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr,
>   	[GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr,
> +	[GCC_USB4_1_PHY_DP0_CLK_SRC] = &gcc_usb4_1_phy_dp0_clk_src.clkr,
> +	[GCC_USB4_1_PHY_DP1_CLK_SRC] = &gcc_usb4_1_phy_dp1_clk_src.clkr,
>   	[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr,
> +	[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr,
>   	[GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr,
>   	[GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr,
> +	[GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr,
>   	[GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr,
> +	[GCC_USB4_1_PHY_RX0_CLK_SRC] = &gcc_usb4_1_phy_rx0_clk_src.clkr,
>   	[GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr,
> +	[GCC_USB4_1_PHY_RX1_CLK_SRC] = &gcc_usb4_1_phy_rx1_clk_src.clkr,
> +	[GCC_USB4_1_PHY_SYS_CLK_SRC] = &gcc_usb4_1_phy_sys_clk_src.clkr,
>   	[GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr,
>   	[GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr,
>   	[GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr,
> @@ -6540,11 +7266,18 @@ static struct clk_regmap *gcc_x1e80100_clocks[] = {
>   	[GCC_USB4_2_DP1_CLK] = &gcc_usb4_2_dp1_clk.clkr,
>   	[GCC_USB4_2_MASTER_CLK] = &gcc_usb4_2_master_clk.clkr,
>   	[GCC_USB4_2_MASTER_CLK_SRC] = &gcc_usb4_2_master_clk_src.clkr,
> +	[GCC_USB4_2_PHY_DP0_CLK_SRC] = &gcc_usb4_2_phy_dp0_clk_src.clkr,
> +	[GCC_USB4_2_PHY_DP1_CLK_SRC] = &gcc_usb4_2_phy_dp1_clk_src.clkr,
>   	[GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr,
> +	[GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr,
>   	[GCC_USB4_2_PHY_PCIE_PIPE_CLK] = &gcc_usb4_2_phy_pcie_pipe_clk.clkr,
>   	[GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_clk_src.clkr,
> +	[GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr,
>   	[GCC_USB4_2_PHY_RX0_CLK] = &gcc_usb4_2_phy_rx0_clk.clkr,
> +	[GCC_USB4_2_PHY_RX0_CLK_SRC] = &gcc_usb4_2_phy_rx0_clk_src.clkr,
>   	[GCC_USB4_2_PHY_RX1_CLK] = &gcc_usb4_2_phy_rx1_clk.clkr,
> +	[GCC_USB4_2_PHY_RX1_CLK_SRC] = &gcc_usb4_2_phy_rx1_clk_src.clkr,
> +	[GCC_USB4_2_PHY_SYS_CLK_SRC] = &gcc_usb4_2_phy_sys_clk_src.clkr,
>   	[GCC_USB4_2_PHY_USB_PIPE_CLK] = &gcc_usb4_2_phy_usb_pipe_clk.clkr,
>   	[GCC_USB4_2_SB_IF_CLK] = &gcc_usb4_2_sb_if_clk.clkr,
>   	[GCC_USB4_2_SB_IF_CLK_SRC] = &gcc_usb4_2_sb_if_clk_src.clkr,
> @@ -6660,16 +7393,52 @@ static const struct qcom_reset_map gcc_x1e80100_resets[] = {
>   	[GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 },
>   	[GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 },
>   	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
> +	[GCC_USB4PHY_PHY_PRIM_BCR] = { 0x5000c },
>   	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 },
> +	[GCC_USB4PHY_PHY_SEC_BCR] = { 0x2a00c },
>   	[GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 },
> +	[GCC_USB4PHY_PHY_TERT_BCR] = { 0xa300c },
>   	[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 },
>   	[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 },
>   	[GCC_USB4_0_BCR] = { 0x9f000 },
>   	[GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 },
> -	[GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },
> -	[GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },
> +	[GCC_USB4_0_MISC_USB4_SYS_BCR] = { .reg = 0xad0f8, .bit = 0 },
> +	[GCC_USB4_0_MISC_RX_CLK_0_BCR] = { .reg = 0xad0f8, .bit = 1 },
> +	[GCC_USB4_0_MISC_RX_CLK_1_BCR] = { .reg = 0xad0f8, .bit = 2 },
> +	[GCC_USB4_0_MISC_USB_PIPE_BCR] = { .reg = 0xad0f8, .bit = 3 },
> +	[GCC_USB4_0_MISC_PCIE_PIPE_BCR] = { .reg = 0xad0f8, .bit = 4 },
> +	[GCC_USB4_0_MISC_TMU_BCR] = { .reg = 0xad0f8, .bit = 5 },
> +	[GCC_USB4_0_MISC_SB_IF_BCR] = { .reg = 0xad0f8, .bit = 6 },
> +	[GCC_USB4_0_MISC_HIA_MSTR_BCR] = { .reg = 0xad0f8, .bit = 7 },
> +	[GCC_USB4_0_MISC_AHB_BCR] = { .reg = 0xad0f8, .bit = 8 },
> +	[GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xad0f8, .bit = 9 },
> +	[GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xad0f8, .bit = 10 },
>   	[GCC_USB4_1_BCR] = { 0x2b000 },
> +	[GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },
> +	[GCC_USB4_1_MISC_USB4_SYS_BCR] = { .reg = 0xae0f8, .bit = 0 },
> +	[GCC_USB4_1_MISC_RX_CLK_0_BCR] = { .reg = 0xae0f8, .bit = 1 },
> +	[GCC_USB4_1_MISC_RX_CLK_1_BCR] = { .reg = 0xae0f8, .bit = 2 },
> +	[GCC_USB4_1_MISC_USB_PIPE_BCR] = { .reg = 0xae0f8, .bit = 3 },
> +	[GCC_USB4_1_MISC_PCIE_PIPE_BCR] = { .reg = 0xae0f8, .bit = 4 },
> +	[GCC_USB4_1_MISC_TMU_BCR] = { .reg = 0xae0f8, .bit = 5 },
> +	[GCC_USB4_1_MISC_SB_IF_BCR] = { .reg = 0xae0f8, .bit = 6 },
> +	[GCC_USB4_1_MISC_HIA_MSTR_BCR] = { .reg = 0xae0f8, .bit = 7 },
> +	[GCC_USB4_1_MISC_AHB_BCR] = { .reg = 0xae0f8, .bit = 8 },
> +	[GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xae0f8, .bit = 9 },
> +	[GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xae0f8, .bit = 10 },
>   	[GCC_USB4_2_BCR] = { 0x11000 },
> +	[GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },
> +	[GCC_USB4_2_MISC_USB4_SYS_BCR] = { .reg = 0xaf0f8, .bit = 0 },
> +	[GCC_USB4_2_MISC_RX_CLK_0_BCR] = { .reg = 0xaf0f8, .bit = 1 },
> +	[GCC_USB4_2_MISC_RX_CLK_1_BCR] = { .reg = 0xaf0f8, .bit = 2 },
> +	[GCC_USB4_2_MISC_USB_PIPE_BCR] = { .reg = 0xaf0f8, .bit = 3 },
> +	[GCC_USB4_2_MISC_PCIE_PIPE_BCR] = { .reg = 0xaf0f8, .bit = 4 },
> +	[GCC_USB4_2_MISC_TMU_BCR] = { .reg = 0xaf0f8, .bit = 5 },
> +	[GCC_USB4_2_MISC_SB_IF_BCR] = { .reg = 0xaf0f8, .bit = 6 },
> +	[GCC_USB4_2_MISC_HIA_MSTR_BCR] = { .reg = 0xaf0f8, .bit = 7 },
> +	[GCC_USB4_2_MISC_AHB_BCR] = { .reg = 0xaf0f8, .bit = 8 },
> +	[GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xaf0f8, .bit = 9 },
> +	[GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xaf0f8, .bit = 10 },
>   	[GCC_USB_0_PHY_BCR] = { 0x50020 },
>   	[GCC_USB_1_PHY_BCR] = { 0x2a020 },
>   	[GCC_USB_2_PHY_BCR] = { 0xa3020 },
> 

LGTM

Reviewed-by: Bryan O'Donoghue <bod@kernel.org>

Re: [PATCH 3/3] arm64: dts: qcom: x1e80100: Extend the gcc input clock list

[Bryan O'Donoghue]

On 26/09/2025 13:03, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> With the recent dt-bindings update, the missing USB4 clocks have been
> added.
> 
> Extend the existing list to make sure the DT contains the expected
> amount of 'clocks' entries.

Small nit, "expected number" would be better.

> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
>   arch/arm64/boot/dts/qcom/x1e80100.dtsi | 29 ++++++++++++++++++++++++++++-
>   1 file changed, 28 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 51576d9c935decbc61a8e4200de83e739f7da814..cc76b9933a9bbff396ec4739f4a1dd3d2cc81f0f 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -807,7 +807,34 @@ gcc: clock-controller@100000 {
>   				 <0>,
>   				 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
>   				 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> -				 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
> +				 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>;
>   
>   			power-domains = <&rpmhpd RPMHPD_CX>;
>   			#clock-cells = <1>;
> 

Reviewed-by: Bryan O'Donoghue <bod@kernel.org>

Re: [PATCH 2/3] clk: qcom: gcc-x1e80100: Add missing USB4 clocks/resets

[kernel test robot]

Hi Konrad,

kernel test robot noticed the following build warnings:

[auto build test WARNING on 8e2755d7779a95dd61d8997ebce33ff8b1efd3fb]

url:    https://github.com/intel-lab-lkp/linux/commits/Konrad-Dybcio/dt-bindings-clock-qcom-x1e80100-gcc-Add-missing-USB4-clocks-resets/20250926-200520
base:   8e2755d7779a95dd61d8997ebce33ff8b1efd3fb
patch link:    https://lore.kernel.org/r/20250926-topic-hamoa_gcc_usb4-v1-2-25cad1700829%40oss.qualcomm.com
patch subject: [PATCH 2/3] clk: qcom: gcc-x1e80100: Add missing USB4 clocks/resets
config: riscv-randconfig-002-20250927 (https://download.01.org/0day-ci/archive/20250927/202509272140.wYFpHZfD-lkp@intel.com/config)
compiler: riscv64-linux-gcc (GCC) 15.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250927/202509272140.wYFpHZfD-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202509272140.wYFpHZfD-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/clk/qcom/gcc-x1e80100.c:580:32: warning: 'gcc_parent_map_33' defined but not used [-Wunused-const-variable=]
     580 | static const struct parent_map gcc_parent_map_33[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:570:32: warning: 'gcc_parent_map_32' defined but not used [-Wunused-const-variable=]
     570 | static const struct parent_map gcc_parent_map_32[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:560:32: warning: 'gcc_parent_map_31' defined but not used [-Wunused-const-variable=]
     560 | static const struct parent_map gcc_parent_map_31[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:550:32: warning: 'gcc_parent_map_30' defined but not used [-Wunused-const-variable=]
     550 | static const struct parent_map gcc_parent_map_30[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:540:32: warning: 'gcc_parent_map_29' defined but not used [-Wunused-const-variable=]
     540 | static const struct parent_map gcc_parent_map_29[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:530:32: warning: 'gcc_parent_map_28' defined but not used [-Wunused-const-variable=]
     530 | static const struct parent_map gcc_parent_map_28[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:520:32: warning: 'gcc_parent_map_27' defined but not used [-Wunused-const-variable=]
     520 | static const struct parent_map gcc_parent_map_27[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:510:32: warning: 'gcc_parent_map_26' defined but not used [-Wunused-const-variable=]
     510 | static const struct parent_map gcc_parent_map_26[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:500:32: warning: 'gcc_parent_map_25' defined but not used [-Wunused-const-variable=]
     500 | static const struct parent_map gcc_parent_map_25[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:490:32: warning: 'gcc_parent_map_24' defined but not used [-Wunused-const-variable=]
     490 | static const struct parent_map gcc_parent_map_24[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:480:32: warning: 'gcc_parent_map_23' defined but not used [-Wunused-const-variable=]
     480 | static const struct parent_map gcc_parent_map_23[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:470:32: warning: 'gcc_parent_map_22' defined but not used [-Wunused-const-variable=]
     470 | static const struct parent_map gcc_parent_map_22[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:460:32: warning: 'gcc_parent_map_21' defined but not used [-Wunused-const-variable=]
     460 | static const struct parent_map gcc_parent_map_21[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:450:32: warning: 'gcc_parent_map_20' defined but not used [-Wunused-const-variable=]
     450 | static const struct parent_map gcc_parent_map_20[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:440:32: warning: 'gcc_parent_map_19' defined but not used [-Wunused-const-variable=]
     440 | static const struct parent_map gcc_parent_map_19[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:430:32: warning: 'gcc_parent_map_18' defined but not used [-Wunused-const-variable=]
     430 | static const struct parent_map gcc_parent_map_18[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:420:32: warning: 'gcc_parent_map_17' defined but not used [-Wunused-const-variable=]
     420 | static const struct parent_map gcc_parent_map_17[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:410:32: warning: 'gcc_parent_map_16' defined but not used [-Wunused-const-variable=]
     410 | static const struct parent_map gcc_parent_map_16[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:400:32: warning: 'gcc_parent_map_15' defined but not used [-Wunused-const-variable=]
     400 | static const struct parent_map gcc_parent_map_15[] = {
         |                                ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-x1e80100.c:390:32: warning: 'gcc_parent_map_14' defined but not used [-Wunused-const-variable=]
     390 | static const struct parent_map gcc_parent_map_14[] = {
         |                                ^~~~~~~~~~~~~~~~~
   drivers/clk/qcom/gcc-x1e80100.c:380:32: warning: 'gcc_parent_map_13' defined but not used [-Wunused-const-variable=]
     380 | static const struct parent_map gcc_parent_map_13[] = {
         |                                ^~~~~~~~~~~~~~~~~

Kconfig warnings: (for reference only)
   WARNING: unmet direct dependencies detected for ARCH_HAS_ELF_CORE_EFLAGS
   Depends on [n]: BINFMT_ELF [=n] && ELF_CORE [=y]
   Selected by [y]:
   - RISCV [=y]


vim +/gcc_parent_map_33 +580 drivers/clk/qcom/gcc-x1e80100.c

   389	
 > 390	static const struct parent_map gcc_parent_map_14[] = {
   391		{ P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC, 0 },
   392		{ P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
   393	};
   394	
   395	static const struct clk_parent_data gcc_parent_data_14[] = {
   396		{ .index = DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC },
   397		{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
   398	};
   399	
 > 400	static const struct parent_map gcc_parent_map_15[] = {
   401		{ P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
   402		{ P_BI_TCXO, 2 },
   403	};
   404	
   405	static const struct clk_parent_data gcc_parent_data_15[] = {
   406		{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
   407		{ .index = DT_BI_TCXO },
   408	};
   409	
 > 410	static const struct parent_map gcc_parent_map_16[] = {
   411		{ P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
   412		{ P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 },
   413	};
   414	
   415	static const struct clk_parent_data gcc_parent_data_16[] = {
   416		{ .index = DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC },
   417		{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
   418	};
   419	
 > 420	static const struct parent_map gcc_parent_map_17[] = {
   421		{ P_QUSB4PHY_0_GCC_USB4_RX0_CLK, 0 },
   422		{ P_BI_TCXO, 2 },
   423	};
   424	
   425	static const struct clk_parent_data gcc_parent_data_17[] = {
   426		{ .index = DT_QUSB4PHY_0_GCC_USB4_RX0_CLK },
   427		{ .index = DT_BI_TCXO },
   428	};
   429	
 > 430	static const struct parent_map gcc_parent_map_18[] = {
   431		{ P_QUSB4PHY_0_GCC_USB4_RX1_CLK, 0 },
   432		{ P_BI_TCXO, 2 },
   433	};
   434	
   435	static const struct clk_parent_data gcc_parent_data_18[] = {
   436		{ .index = DT_QUSB4PHY_0_GCC_USB4_RX1_CLK },
   437		{ .index = DT_BI_TCXO },
   438	};
   439	
 > 440	static const struct parent_map gcc_parent_map_19[] = {
   441		{ P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
   442		{ P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
   443	};
   444	
   445	static const struct clk_parent_data gcc_parent_data_19[] = {
   446		{ .index = DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC },
   447		{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
   448	};
   449	
 > 450	static const struct parent_map gcc_parent_map_20[] = {
   451		{ P_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC, 0 },
   452		{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
   453	};
   454	
   455	static const struct clk_parent_data gcc_parent_data_20[] = {
   456		{ .index = DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC },
   457		{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
   458	};
   459	
 > 460	static const struct parent_map gcc_parent_map_21[] = {
   461		{ P_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC, 0 },
   462		{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
   463	};
   464	
   465	static const struct clk_parent_data gcc_parent_data_21[] = {
   466		{ .index = DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC },
   467		{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
   468	};
   469	
 > 470	static const struct parent_map gcc_parent_map_22[] = {
   471		{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
   472		{ P_BI_TCXO, 2 },
   473	};
   474	
   475	static const struct clk_parent_data gcc_parent_data_22[] = {
   476		{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
   477		{ .index = DT_BI_TCXO },
   478	};
   479	
 > 480	static const struct parent_map gcc_parent_map_23[] = {
   481		{ P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
   482		{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 },
   483	};
   484	
   485	static const struct clk_parent_data gcc_parent_data_23[] = {
   486		{ .index = DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC },
   487		{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
   488	};
   489	
 > 490	static const struct parent_map gcc_parent_map_24[] = {
   491		{ P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 0 },
   492		{ P_BI_TCXO, 2 },
   493	};
   494	
   495	static const struct clk_parent_data gcc_parent_data_24[] = {
   496		{ .index = DT_QUSB4PHY_1_GCC_USB4_RX0_CLK },
   497		{ .index = DT_BI_TCXO },
   498	};
   499	
 > 500	static const struct parent_map gcc_parent_map_25[] = {
   501		{ P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 0 },
   502		{ P_BI_TCXO, 2 },
   503	};
   504	
   505	static const struct clk_parent_data gcc_parent_data_25[] = {
   506		{ .index = DT_QUSB4PHY_1_GCC_USB4_RX1_CLK },
   507		{ .index = DT_BI_TCXO },
   508	};
   509	
 > 510	static const struct parent_map gcc_parent_map_26[] = {
   511		{ P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
   512		{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
   513	};
   514	
   515	static const struct clk_parent_data gcc_parent_data_26[] = {
   516		{ .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC },
   517		{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
   518	};
   519	
 > 520	static const struct parent_map gcc_parent_map_27[] = {
   521		{ P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC, 0 },
   522		{ P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
   523	};
   524	
   525	static const struct clk_parent_data gcc_parent_data_27[] = {
   526		{ .index = DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC },
   527		{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
   528	};
   529	
 > 530	static const struct parent_map gcc_parent_map_28[] = {
   531		{ P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC, 0 },
   532		{ P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
   533	};
   534	
   535	static const struct clk_parent_data gcc_parent_data_28[] = {
   536		{ .index = DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC },
   537		{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
   538	};
   539	
 > 540	static const struct parent_map gcc_parent_map_29[] = {
   541		{ P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
   542		{ P_BI_TCXO, 2 },
   543	};
   544	
   545	static const struct clk_parent_data gcc_parent_data_29[] = {
   546		{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
   547		{ .index = DT_BI_TCXO },
   548	};
   549	
 > 550	static const struct parent_map gcc_parent_map_30[] = {
   551		{ P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
   552		{ P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 },
   553	};
   554	
   555	static const struct clk_parent_data gcc_parent_data_30[] = {
   556		{ .index = DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC },
   557		{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
   558	};
   559	
 > 560	static const struct parent_map gcc_parent_map_31[] = {
   561		{ P_QUSB4PHY_2_GCC_USB4_RX0_CLK, 0 },
   562		{ P_BI_TCXO, 2 },
   563	};
   564	
   565	static const struct clk_parent_data gcc_parent_data_31[] = {
   566		{ .index = DT_QUSB4PHY_2_GCC_USB4_RX0_CLK },
   567		{ .index = DT_BI_TCXO },
   568	};
   569	
 > 570	static const struct parent_map gcc_parent_map_32[] = {
   571		{ P_QUSB4PHY_2_GCC_USB4_RX1_CLK, 0 },
   572		{ P_BI_TCXO, 2 },
   573	};
   574	
   575	static const struct clk_parent_data gcc_parent_data_32[] = {
   576		{ .index = DT_QUSB4PHY_2_GCC_USB4_RX1_CLK },
   577		{ .index = DT_BI_TCXO },
   578	};
   579	
 > 580	static const struct parent_map gcc_parent_map_33[] = {
   581		{ P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
   582		{ P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
   583	};
   584	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 1/3] dt-bindings: clock: qcom,x1e80100-gcc: Add missing USB4 clocks/resets

[Rob Herring (Arm)]

On Fri, 26 Sep 2025 14:03:45 +0200, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Some of the USB4 muxes, RCGs and resets were not initially described.
> 
> Add indices for them to allow extending the driver.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
>  .../bindings/clock/qcom,x1e80100-gcc.yaml          | 62 ++++++++++++++++++++--
>  include/dt-bindings/clock/qcom,x1e80100-gcc.h      | 61 +++++++++++++++++++++
>  2 files changed, 119 insertions(+), 4 deletions(-)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 2/3] clk: qcom: gcc-x1e80100: Add missing USB4 clocks/resets

[Konrad Dybcio]

On 9/27/25 4:01 PM, kernel test robot wrote:
> Hi Konrad,
> 
> kernel test robot noticed the following build warnings:
> 
> [auto build test WARNING on 8e2755d7779a95dd61d8997ebce33ff8b1efd3fb]
> 
> url:    https://github.com/intel-lab-lkp/linux/commits/Konrad-Dybcio/dt-bindings-clock-qcom-x1e80100-gcc-Add-missing-USB4-clocks-resets/20250926-200520
> base:   8e2755d7779a95dd61d8997ebce33ff8b1efd3fb
> patch link:    https://lore.kernel.org/r/20250926-topic-hamoa_gcc_usb4-v1-2-25cad1700829%40oss.qualcomm.com
> patch subject: [PATCH 2/3] clk: qcom: gcc-x1e80100: Add missing USB4 clocks/resets
> config: riscv-randconfig-002-20250927 (https://download.01.org/0day-ci/archive/20250927/202509272140.wYFpHZfD-lkp@intel.com/config)
> compiler: riscv64-linux-gcc (GCC) 15.1.0
> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250927/202509272140.wYFpHZfD-lkp@intel.com/reproduce)
> 
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes: https://lore.kernel.org/oe-kbuild-all/202509272140.wYFpHZfD-lkp@intel.com/
> 
> All warnings (new ones prefixed by >>):
> 
>>> drivers/clk/qcom/gcc-x1e80100.c:580:32: warning: 'gcc_parent_map_33' defined but not used [-Wunused-const-variable=]
>      580 | static const struct parent_map gcc_parent_map_33[] = {

I initially used a different magic clock struct, but the current
clk_regmap_phy_mux doesn't need it. I'll resend with that fixed.

Konrad