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[130.180.211.218]) by smtp.googlemail.com with ESMTPSA id k3-20020a056000004300b0033b79d385f6sm21179398wrx.47.2024.02.22.10.44.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Feb 2024 10:44:13 -0800 (PST) Message-ID: Date: Thu, 22 Feb 2024 19:44:12 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 1/7] soc: sunxi: sram: export register 0 for THS on H616 Content-Language: en-US To: =?UTF-8?Q?Jernej_=C5=A0krabec?= , Vasily Khoruzhick , Yangtao Li , Chen-Yu Tsai , Samuel Holland , Andre Przywara Cc: "Rafael J . Wysocki" , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Martin Botka , Maksim Kiselev , Bob McChesney , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev References: <20240219153639.179814-1-andre.przywara@arm.com> <20240219153639.179814-2-andre.przywara@arm.com> <2717467.mvXUDI8C0e@jernej-laptop> From: Daniel Lezcano In-Reply-To: <2717467.mvXUDI8C0e@jernej-laptop> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 22/02/2024 19:26, Jernej Škrabec wrote: > Dne ponedeljek, 19. februar 2024 ob 16:36:33 CET je Andre Przywara napisal(a): >> The Allwinner H616 SoC contains a mysterious bit at register offset 0x0 >> in the SRAM control block. If bit 16 is set (the reset value), the >> temperature readings of the THS are way off, leading to reports about >> 200C, at normal ambient temperatures. Clearing this bits brings the >> reported values down to the expected values. >> The BSP code clears this bit in firmware (U-Boot), and has an explicit >> comment about this, but offers no real explanation. >> >> Experiments in U-Boot show that register 0x0 has no effect on the SRAM C >> visibility: all tested bit settings still allow full read and write >> access by the CPU to the whole of SRAM C. Only bit 24 of the register at >> offset 0x4 makes all of SRAM C inaccessible by the CPU. So modelling >> the THS switch functionality as an SRAM region would not reflect reality. >> >> Since we should not rely on firmware settings, allow other code (the THS >> driver) to access this register, by exporting it through the already >> existing regmap. This mimics what we already do for the LDO control and >> the EMAC register. >> >> To avoid concurrent accesses to the same register at the same time, by >> the SRAM switch code and the regmap code, use the same lock to protect >> the access. The regmap subsystem allows to use an existing lock, so we >> just need to hook in there. >> >> Signed-off-by: Andre Przywara > > Reviewed-by: Jernej Skrabec > > I guess this one goes through sunxi tree, right? I'll pick this patch along with the patch 2-6, so through the thermal tree. The patch 7/7 will go indeed via the sunxi tree -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog