Re: [PATCH v1 1/2] riscv: dts: starfive: jh7110: pciephy0 USB 3.0 configuration registers

[E Shattow <e@freeshell.de>]

Hi Minda,

On 1/15/25 02:58, Minda Chen wrote:
> 
> 
>>
>> On Tue, Jan 14, 2025 at 05:42:28AM +0000, Minda Chen wrote:
>>>
>>>
>>>>
>>>> On Thu, Jan 02, 2025 at 10:37:36AM -0800, E Shattow wrote:
>>>>> StarFive JH7110 contains a Cadence USB2.0+USB3.0 controller IP
>>>>> block that may exclusively use pciephy0 for USB3.0 connectivity.
>>>>> Add the register offsets for the driver to enable/disable USB3.0 on
>> pciephy0.
>>>>>
>>>>> Signed-off-by: E Shattow <e@freeshell.de>
>>>>> ---
>>>>>   arch/riscv/boot/dts/starfive/jh7110.dtsi | 2 ++
>>>>>   1 file changed, 2 insertions(+)
>>>>>
>>>>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>>>>> b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>>>>> index 0d8339357bad..75ff07303e8b 100644
>>>>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>>>>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>>>>> @@ -611,6 +611,8 @@ usbphy0: phy@10200000 {
>>>>>   		pciephy0: phy@10210000 {
>>>>>   			compatible = "starfive,jh7110-pcie-phy";
>>>>>   			reg = <0x0 0x10210000 0x0 0x10000>;
>>>>> +			starfive,sys-syscon = <&sys_syscon 0x18>;
>>>>> +			starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
>>>>
>>>> Why weren't these added in the first place? Minda, do you know?
>>>>
>>> The driver only require to set syscon register while the PHY attach to
>>> Cadence USB.(star64 board case) The PHY default attach to PCIe0, VF2 board
>> do not set any setting. So I don't set it.
>>
>> Does this mean that the change should be made in files where it will only affect
>> non-VF2 boards, or is it harmless if applied to the VF2 also?
> Harmless. The PCIe PHY driver still set the PCIe mode syscon setting.

Sounds good to me. However some tangent topic related to this series:

Our questions and answers in this discussion are a representation of 
what is missing from the documentation.

What do I want to know? :  "pdrstn split sw usbpipe plugen" abbreviation.

What are the full words that is from?

I will guess the words are:

"Power domain reset negative? Split... Switch? USB pipeline plug enable?"

When this is explained for me I will send a patch to add information 
into documentation at dt-bindings/phy/starfive,jh7110-pcie-phy.yaml 
file. I know that the functionality is already said in discussion;  What 
I want are the full words to expand the "pdrstn split sw usbpipe plugen" 
as any abbreviation would also be expanded and explained in documentation.

It would be difficult to improve the documentation before our discussion 
about this series here. Now it is clear what questions and answers are 
missing from documentation.

-E