Re: [PATCH 3/3] net: j2: Introduce J-Core EMAC

[Rob Landley <rob@landley.net>]

On 8/15/25 17:38, Andrew Lunn wrote:
>>>> What support is there for MDIO? Normally the MAC driver would not be
>>>> setting the carrier status, phylink or phylib would do that.
>>>
>>>  From what I can tell, none. This is a very simple FPGA RTL
>>> implementation of a MAC, and looking at the VHDL, I don't see any MDIO
>>> registers.
>>
>>> Moreover, the MDIO pin on the PHY IC on my dev board also
>>> appears unconnected.
>>
>> I spoke too soon on that one. It appears to be connected through a trace
>> that goes under the IC. Nevertheless, I don't think MDIO support is in
>> the IP core design.
> 
> MDIO is actually two pins. MDC and MDIO.

I asked Jeff and he pointed me at 
https://github.com/j-core/jcore-soc/blob/master/targets/boards/turtle_1v1/pad_ring.vhd#L732 
and 
https://github.com/j-core/jcore-soc/blob/master/targets/pins/turtle_1v0.pins 
and said those two pins are "wired to zero".

He also said: "It would only take a few hrs to add MDIO." but there 
basically hasn't been a use case yet.

> It might be there is a second IP core which implements MDIO. There is
> no reason it needs to be tightly integrated into the MAC. But it does
> make the MAC driver slightly more complex. You then need a Linux MDIO
> bus driver for it, and the DT for the MAC would include a phy-handle
> property pointing to the PHY on the MDIO bus.
> 
> Is there an Ethernet PHY on your board?

According to 
https://github.com/j-core/jcore-jx/blob/master/schematic.pdf it's a 
https://www.micros.com.pl/mediaserver/info-uiip101a.pdf

> 	Andrew

Rob