* [PATCH v6 0/5] add support for T7 family clock controller
@ 2025-12-04 5:36 Jian Hu
2025-12-04 5:36 ` [PATCH v6 1/5] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Jian Hu @ 2025-12-04 5:36 UTC (permalink / raw)
To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, robh+dt,
Rob Herring
Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
It introduces three clock controllers:
- SCMI clock controller: these clocks are managed by the SCP and handled through SCMI.
- PLL clock controller.
- peripheral clock controller.
Changes v6 since v5 at [5]:
- add a blank line after each PLL register region
- update GP1 PLL note
- update PLL and peripherals help message
- add parentheses around the _iflags member in MESON_COMP_GATE
- drop CLK_SET_RATE_PARENT and the 4th parent for rtc
- move sd_emmc_c after sd_emmc_b
Changes v5 since v4 at [4]:
- rename rtc and cec dualdiv clocks
- rename dsp clocks
- rename anakin clocks
- rename fdiv2_divn to 25m and fix its parent
- add flag for T7_COMP_GATE
- use T7_COMP_SEL/DIV/GATE to define glitch clocks
- add CLK_SET_RATE_NO_REPARENT for t7_eth_rmii_sel and rtc
- move module_platform_driver after clock driver
Changes v4 since v3 at [3]:
- drop amlogic_t7_pll_probe, use meson_clkc_mmio_probe instead
- add CLK_DIVIDER_MAX_AT_ZERO for pcie_pll_od clk
- add frac for hifi_dco_pll_dco
- add l_detect for mclk_pll_dco
- drop v3 5/6 patch, and use MESON_PCLK
- drop SPI_PWM_CLK_XX macro and use MESON_COMP_XX
- drop the register's prefix
Changes v3 since v2 at [2]:
- update T7 PLL YAML
- add 't7_' prefix for t7 clock name and variable in t7-pll.c and t7-peripherals.c
- correct v1 patch link
- add new macro MESON_PCLK_V2
- update the driver,header,yaml file license
Changes v2 since v1 at [1]:
- add CLK_MESON import
- add const for clkc_regmap_config in PLL driver
- fix eth_rmii_sel parent
- update T7 PLL YAML file
[1]: https://lore.kernel.org/all/20241231060047.2298871-1-jian.hu@amlogic.com
[2]: https://lore.kernel.org/all/20250108094025.2664201-1-jian.hu@amlogic.com
[3]: https://lore.kernel.org/all/20250509074825.1933254-1-jian.hu@amlogic.com
[4]: https://lore.kernel.org/all/20251030094345.2571222-1-jian.hu@amlogic.com
[5]: https://lore.kernel.org/all/20251121105934.1759745-1-jian.hu@amlogic.com
Jian Hu (5):
dt-bindings: clock: add Amlogic T7 PLL clock controller
dt-bindings: clock: add Amlogic T7 SCMI clock controller
dt-bindings: clock: add Amlogic T7 peripherals clock controller
clk: meson: t7: add support for the T7 SoC PLL clock
clk: meson: t7: add t7 clock peripherals controller driver
.../clock/amlogic,t7-peripherals-clkc.yaml | 116 ++
.../bindings/clock/amlogic,t7-pll-clkc.yaml | 114 ++
drivers/clk/meson/Kconfig | 27 +
drivers/clk/meson/Makefile | 2 +
drivers/clk/meson/t7-peripherals.c | 1271 +++++++++++++++++
drivers/clk/meson/t7-pll.c | 1074 ++++++++++++++
.../clock/amlogic,t7-peripherals-clkc.h | 228 +++
.../dt-bindings/clock/amlogic,t7-pll-clkc.h | 56 +
include/dt-bindings/clock/amlogic,t7-scmi.h | 47 +
9 files changed, 2935 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
create mode 100644 drivers/clk/meson/t7-peripherals.c
create mode 100644 drivers/clk/meson/t7-pll.c
create mode 100644 include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h
create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h
--
2.47.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 1/5] dt-bindings: clock: add Amlogic T7 PLL clock controller
2025-12-04 5:36 [PATCH v6 0/5] add support for T7 family clock controller Jian Hu
@ 2025-12-04 5:36 ` Jian Hu
2025-12-04 5:36 ` [PATCH v6 2/5] dt-bindings: clock: add Amlogic T7 SCMI " Jian Hu
` (3 subsequent siblings)
4 siblings, 0 replies; 13+ messages in thread
From: Jian Hu @ 2025-12-04 5:36 UTC (permalink / raw)
To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, robh+dt,
Rob Herring
Cc: Jian Hu, Conor Dooley, devicetree, linux-clk, linux-amlogic,
linux-kernel, linux-arm-kernel
Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/clock/amlogic,t7-pll-clkc.yaml | 114 ++++++++++++++++++
.../dt-bindings/clock/amlogic,t7-pll-clkc.h | 56 +++++++++
2 files changed, 170 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
new file mode 100644
index 000000000000..49c61f65deff
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic T7 PLL Clock Control Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Jian Hu <jian.hu@amlogic.com>
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+
+properties:
+ compatible:
+ enum:
+ - amlogic,t7-gp0-pll
+ - amlogic,t7-gp1-pll
+ - amlogic,t7-hifi-pll
+ - amlogic,t7-pcie-pll
+ - amlogic,t7-mpll
+ - amlogic,t7-hdmi-pll
+ - amlogic,t7-mclk-pll
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ items:
+ - description: mclk pll input oscillator gate
+ - description: oscillator input clock source for mclk_sel_0
+ - description: fixed input clock source for mclk_sel_0
+ minItems: 1
+
+ clock-names:
+ items:
+ - const: in0
+ - const: in1
+ - const: in2
+ minItems: 1
+
+required:
+ - compatible
+ - '#clock-cells'
+ - reg
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: amlogic,t7-mclk-pll
+
+ then:
+ properties:
+ clocks:
+ minItems: 3
+
+ clock-names:
+ minItems: 3
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,t7-gp0-pll
+ - amlogic,t7-gp1--pll
+ - amlogic,t7-hifi-pll
+ - amlogic,t7-pcie-pll
+ - amlogic,t7-mpll
+ - amlogic,t7-hdmi-pll
+
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@8080 {
+ compatible = "amlogic,t7-gp0-pll";
+ reg = <0 0x8080 0 0x20>;
+ clocks = <&scmi_clk 2>;
+ clock-names = "in0";
+ #clock-cells = <1>;
+ };
+
+ clock-controller@8300 {
+ compatible = "amlogic,t7-mclk-pll";
+ reg = <0 0x8300 0 0x18>;
+ clocks = <&scmi_clk 2>,
+ <&xtal>,
+ <&scmi_clk 31>;
+ clock-names = "in0", "in1", "in2";
+ #clock-cells = <1>;
+ };
+ };
diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
new file mode 100644
index 000000000000..e2481f2f1163
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef __T7_PLL_CLKC_H
+#define __T7_PLL_CLKC_H
+
+/* GP0 */
+#define CLKID_GP0_PLL_DCO 0
+#define CLKID_GP0_PLL 1
+
+/* GP1 */
+#define CLKID_GP1_PLL_DCO 0
+#define CLKID_GP1_PLL 1
+
+/* HIFI */
+#define CLKID_HIFI_PLL_DCO 0
+#define CLKID_HIFI_PLL 1
+
+/* PCIE */
+#define CLKID_PCIE_PLL_DCO 0
+#define CLKID_PCIE_PLL_DCO_DIV2 1
+#define CLKID_PCIE_PLL_OD 2
+#define CLKID_PCIE_PLL 3
+
+/* MPLL */
+#define CLKID_MPLL_PREDIV 0
+#define CLKID_MPLL0_DIV 1
+#define CLKID_MPLL0 2
+#define CLKID_MPLL1_DIV 3
+#define CLKID_MPLL1 4
+#define CLKID_MPLL2_DIV 5
+#define CLKID_MPLL2 6
+#define CLKID_MPLL3_DIV 7
+#define CLKID_MPLL3 8
+
+/* HDMI */
+#define CLKID_HDMI_PLL_DCO 0
+#define CLKID_HDMI_PLL_OD 1
+#define CLKID_HDMI_PLL 2
+
+/* MCLK */
+#define CLKID_MCLK_PLL_DCO 0
+#define CLKID_MCLK_PRE 1
+#define CLKID_MCLK_PLL 2
+#define CLKID_MCLK_0_SEL 3
+#define CLKID_MCLK_0_DIV2 4
+#define CLKID_MCLK_0_PRE 5
+#define CLKID_MCLK_0 6
+#define CLKID_MCLK_1_SEL 7
+#define CLKID_MCLK_1_DIV2 8
+#define CLKID_MCLK_1_PRE 9
+#define CLKID_MCLK_1 10
+
+#endif /* __T7_PLL_CLKC_H */
--
2.47.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v6 2/5] dt-bindings: clock: add Amlogic T7 SCMI clock controller
2025-12-04 5:36 [PATCH v6 0/5] add support for T7 family clock controller Jian Hu
2025-12-04 5:36 ` [PATCH v6 1/5] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu
@ 2025-12-04 5:36 ` Jian Hu
2025-12-08 6:17 ` Krzysztof Kozlowski
2025-12-04 5:36 ` [PATCH v6 3/5] dt-bindings: clock: add Amlogic T7 peripherals " Jian Hu
` (2 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Jian Hu @ 2025-12-04 5:36 UTC (permalink / raw)
To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, robh+dt,
Rob Herring
Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
Add DT bindings for the SCMI clock controller of the Amlogic T7 SoC family.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
include/dt-bindings/clock/amlogic,t7-scmi.h | 47 +++++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h
diff --git a/include/dt-bindings/clock/amlogic,t7-scmi.h b/include/dt-bindings/clock/amlogic,t7-scmi.h
new file mode 100644
index 000000000000..27bd257bd4ea
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,t7-scmi.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef __T7_SCMI_CLKC_H
+#define __T7_SCMI_CLKC_H
+
+#define CLKID_DDR_PLL_OSC 0
+#define CLKID_AUD_PLL_OSC 1
+#define CLKID_TOP_PLL_OSC 2
+#define CLKID_TCON_PLL_OSC 3
+#define CLKID_USB_PLL0_OSC 4
+#define CLKID_USB_PLL1_OSC 5
+#define CLKID_MCLK_PLL_OSC 6
+#define CLKID_PCIE_OSC 7
+#define CLKID_ETH_PLL_OSC 8
+#define CLKID_PCIE_REFCLK_PLL_OSC 9
+#define CLKID_EARC_OSC 10
+#define CLKID_SYS1_PLL_OSC 11
+#define CLKID_HDMI_PLL_OSC 12
+#define CLKID_SYS_CLK 13
+#define CLKID_AXI_CLK 14
+#define CLKID_FIXED_PLL_DCO 15
+#define CLKID_FIXED_PLL 16
+#define CLKID_FCLK_DIV2_DIV 17
+#define CLKID_FCLK_DIV2 18
+#define CLKID_FCLK_DIV2P5_DIV 19
+#define CLKID_FCLK_DIV2P5 20
+#define CLKID_FCLK_DIV3_DIV 21
+#define CLKID_FCLK_DIV3 22
+#define CLKID_FCLK_DIV4_DIV 23
+#define CLKID_FCLK_DIV4 24
+#define CLKID_FCLK_DIV5_DIV 25
+#define CLKID_FCLK_DIV5 26
+#define CLKID_FCLK_DIV7_DIV 27
+#define CLKID_FCLK_DIV7 28
+#define CLKID_FCLK_50M_DIV 29
+#define CLKID_FCLK_50M 30
+#define CLKID_CPU_CLK 31
+#define CLKID_A73_CLK 32
+#define CLKID_CPU_CLK_DIV16_DIV 33
+#define CLKID_CPU_CLK_DIV16 34
+#define CLKID_A73_CLK_DIV16_DIV 35
+#define CLKID_A73_CLK_DIV16 36
+
+#endif /* __T7_SCMI_CLKC_H */
--
2.47.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v6 3/5] dt-bindings: clock: add Amlogic T7 peripherals clock controller
2025-12-04 5:36 [PATCH v6 0/5] add support for T7 family clock controller Jian Hu
2025-12-04 5:36 ` [PATCH v6 1/5] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu
2025-12-04 5:36 ` [PATCH v6 2/5] dt-bindings: clock: add Amlogic T7 SCMI " Jian Hu
@ 2025-12-04 5:36 ` Jian Hu
2025-12-04 5:36 ` [PATCH v6 4/5] clk: meson: t7: add support for the T7 SoC PLL clock Jian Hu
2025-12-04 5:36 ` [PATCH v6 5/5] clk: meson: t7: add t7 clock peripherals controller driver Jian Hu
4 siblings, 0 replies; 13+ messages in thread
From: Jian Hu @ 2025-12-04 5:36 UTC (permalink / raw)
To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, robh+dt,
Rob Herring
Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
Add DT bindings for the peripheral clock controller of the Amlogic T7
SoC family.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
.../clock/amlogic,t7-peripherals-clkc.yaml | 116 +++++++++
.../clock/amlogic,t7-peripherals-clkc.h | 228 ++++++++++++++++++
2 files changed, 344 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
create mode 100644 include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
new file mode 100644
index 000000000000..55bb73707d58
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic T7 Peripherals Clock Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+ - Jian Hu <jian.hu@amlogic.com>
+
+properties:
+ compatible:
+ const: amlogic,t7-peripherals-clkc
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ minItems: 14
+ items:
+ - description: input oscillator
+ - description: input sys clk
+ - description: input fixed pll
+ - description: input fclk div 2
+ - description: input fclk div 2p5
+ - description: input fclk div 3
+ - description: input fclk div 4
+ - description: input fclk div 5
+ - description: input fclk div 7
+ - description: input hifi pll
+ - description: input gp0 pll
+ - description: input gp1 pll
+ - description: input mpll1
+ - description: input mpll2
+ - description: external input rmii oscillator (optional)
+ - description: input video pll0 (optional)
+ - description: external pad input for rtc (optional)
+
+ clock-names:
+ minItems: 14
+ items:
+ - const: xtal
+ - const: sys
+ - const: fix
+ - const: fdiv2
+ - const: fdiv2p5
+ - const: fdiv3
+ - const: fdiv4
+ - const: fdiv5
+ - const: fdiv7
+ - const: hifi
+ - const: gp0
+ - const: gp1
+ - const: mpll1
+ - const: mpll2
+ - const: ext_rmii
+ - const: vid_pll0
+ - const: ext_rtc
+
+required:
+ - compatible
+ - '#clock-cells'
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clkc_periphs:clock-controller@0 {
+ compatible = "amlogic,t7-peripherals-clkc";
+ reg = <0 0x0 0 0x1c8>;
+ #clock-cells = <1>;
+ clocks = <&xtal>,
+ <&scmi_clk 13>,
+ <&scmi_clk 16>,
+ <&scmi_clk 18>,
+ <&scmi_clk 20>,
+ <&scmi_clk 22>,
+ <&scmi_clk 24>,
+ <&scmi_clk 26>,
+ <&scmi_clk 28>,
+ <&hifi 1>,
+ <&gp0 1>,
+ <&gp1 1>,
+ <&mpll 4>,
+ <&mpll 6>;
+ clock-names = "xtal",
+ "sys",
+ "fix",
+ "fdiv2",
+ "fdiv2p5",
+ "fdiv3",
+ "fdiv4",
+ "fdiv5",
+ "fdiv7",
+ "hifi",
+ "gp0",
+ "gp1",
+ "mpll1",
+ "mpll2";
+ };
+ };
diff --git a/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
new file mode 100644
index 000000000000..32c4b62037de
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
@@ -0,0 +1,228 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef __T7_PERIPHERALS_CLKC_H
+#define __T7_PERIPHERALS_CLKC_H
+
+#define CLKID_RTC_DUALDIV_IN 0
+#define CLKID_RTC_DUALDIV_DIV 1
+#define CLKID_RTC_DUALDIV_SEL 2
+#define CLKID_RTC_DUALDIV 3
+#define CLKID_RTC 4
+#define CLKID_CECA_DUALDIV_IN 5
+#define CLKID_CECA_DUALDIV_DIV 6
+#define CLKID_CECA_DUALDIV_SEL 7
+#define CLKID_CECA_DUALDIV 8
+#define CLKID_CECA 9
+#define CLKID_CECB_DUALDIV_IN 10
+#define CLKID_CECB_DUALDIV_DIV 11
+#define CLKID_CECB_DUALDIV_SEL 12
+#define CLKID_CECB_DUALDIV 13
+#define CLKID_CECB 14
+#define CLKID_SC_SEL 15
+#define CLKID_SC_DIV 16
+#define CLKID_SC 17
+#define CLKID_DSPA_0_SEL 18
+#define CLKID_DSPA_0_DIV 19
+#define CLKID_DSPA_0 20
+#define CLKID_DSPA_1_SEL 21
+#define CLKID_DSPA_1_DIV 22
+#define CLKID_DSPA_1 23
+#define CLKID_DSPA 24
+#define CLKID_DSPB_0_SEL 25
+#define CLKID_DSPB_0_DIV 26
+#define CLKID_DSPB_0 27
+#define CLKID_DSPB_1_SEL 28
+#define CLKID_DSPB_1_DIV 29
+#define CLKID_DSPB_1 30
+#define CLKID_DSPB 31
+#define CLKID_24M 32
+#define CLKID_24M_DIV2 33
+#define CLKID_12M 34
+#define CLKID_25M_DIV 35
+#define CLKID_25M 36
+#define CLKID_ANAKIN_0_SEL 37
+#define CLKID_ANAKIN_0_DIV 38
+#define CLKID_ANAKIN_0 39
+#define CLKID_ANAKIN_1_SEL 40
+#define CLKID_ANAKIN_1_DIV 41
+#define CLKID_ANAKIN_1 42
+#define CLKID_ANAKIN_01_SEL 43
+#define CLKID_ANAKIN 44
+#define CLKID_TS_DIV 45
+#define CLKID_TS 46
+#define CLKID_MIPI_CSI_PHY_0_SEL 47
+#define CLKID_MIPI_CSI_PHY_0_DIV 48
+#define CLKID_MIPI_CSI_PHY_0 49
+#define CLKID_MIPI_CSI_PHY_1_SEL 50
+#define CLKID_MIPI_CSI_PHY_1_DIV 51
+#define CLKID_MIPI_CSI_PHY_1 52
+#define CLKID_MIPI_CSI_PHY 53
+#define CLKID_MIPI_ISP_SEL 54
+#define CLKID_MIPI_ISP_DIV 55
+#define CLKID_MIPI_ISP 56
+#define CLKID_MALI_0_SEL 57
+#define CLKID_MALI_0_DIV 58
+#define CLKID_MALI_0 59
+#define CLKID_MALI_1_SEL 60
+#define CLKID_MALI_1_DIV 61
+#define CLKID_MALI_1 62
+#define CLKID_MALI 63
+#define CLKID_ETH_RMII_SEL 64
+#define CLKID_ETH_RMII_DIV 65
+#define CLKID_ETH_RMII 66
+#define CLKID_FCLK_DIV2_DIV8 67
+#define CLKID_ETH_125M 68
+#define CLKID_SD_EMMC_A_SEL 69
+#define CLKID_SD_EMMC_A_DIV 70
+#define CLKID_SD_EMMC_A 71
+#define CLKID_SD_EMMC_B_SEL 72
+#define CLKID_SD_EMMC_B_DIV 73
+#define CLKID_SD_EMMC_B 74
+#define CLKID_SD_EMMC_C_SEL 75
+#define CLKID_SD_EMMC_C_DIV 76
+#define CLKID_SD_EMMC_C 77
+#define CLKID_SPICC0_SEL 78
+#define CLKID_SPICC0_DIV 79
+#define CLKID_SPICC0 80
+#define CLKID_SPICC1_SEL 81
+#define CLKID_SPICC1_DIV 82
+#define CLKID_SPICC1 83
+#define CLKID_SPICC2_SEL 84
+#define CLKID_SPICC2_DIV 85
+#define CLKID_SPICC2 86
+#define CLKID_SPICC3_SEL 87
+#define CLKID_SPICC3_DIV 88
+#define CLKID_SPICC3 89
+#define CLKID_SPICC4_SEL 90
+#define CLKID_SPICC4_DIV 91
+#define CLKID_SPICC4 92
+#define CLKID_SPICC5_SEL 93
+#define CLKID_SPICC5_DIV 94
+#define CLKID_SPICC5 95
+#define CLKID_SARADC_SEL 96
+#define CLKID_SARADC_DIV 97
+#define CLKID_SARADC 98
+#define CLKID_PWM_A_SEL 99
+#define CLKID_PWM_A_DIV 100
+#define CLKID_PWM_A 101
+#define CLKID_PWM_B_SEL 102
+#define CLKID_PWM_B_DIV 103
+#define CLKID_PWM_B 104
+#define CLKID_PWM_C_SEL 105
+#define CLKID_PWM_C_DIV 106
+#define CLKID_PWM_C 107
+#define CLKID_PWM_D_SEL 108
+#define CLKID_PWM_D_DIV 109
+#define CLKID_PWM_D 110
+#define CLKID_PWM_E_SEL 111
+#define CLKID_PWM_E_DIV 112
+#define CLKID_PWM_E 113
+#define CLKID_PWM_F_SEL 114
+#define CLKID_PWM_F_DIV 115
+#define CLKID_PWM_F 116
+#define CLKID_PWM_AO_A_SEL 117
+#define CLKID_PWM_AO_A_DIV 118
+#define CLKID_PWM_AO_A 119
+#define CLKID_PWM_AO_B_SEL 120
+#define CLKID_PWM_AO_B_DIV 121
+#define CLKID_PWM_AO_B 122
+#define CLKID_PWM_AO_C_SEL 123
+#define CLKID_PWM_AO_C_DIV 124
+#define CLKID_PWM_AO_C 125
+#define CLKID_PWM_AO_D_SEL 126
+#define CLKID_PWM_AO_D_DIV 127
+#define CLKID_PWM_AO_D 128
+#define CLKID_PWM_AO_E_SEL 129
+#define CLKID_PWM_AO_E_DIV 130
+#define CLKID_PWM_AO_E 131
+#define CLKID_PWM_AO_F_SEL 132
+#define CLKID_PWM_AO_F_DIV 133
+#define CLKID_PWM_AO_F 134
+#define CLKID_PWM_AO_G_SEL 135
+#define CLKID_PWM_AO_G_DIV 136
+#define CLKID_PWM_AO_G 137
+#define CLKID_PWM_AO_H_SEL 138
+#define CLKID_PWM_AO_H_DIV 139
+#define CLKID_PWM_AO_H 140
+#define CLKID_SYS_DDR 141
+#define CLKID_SYS_DOS 142
+#define CLKID_SYS_MIPI_DSI_A 143
+#define CLKID_SYS_MIPI_DSI_B 144
+#define CLKID_SYS_ETHPHY 145
+#define CLKID_SYS_MALI 146
+#define CLKID_SYS_AOCPU 147
+#define CLKID_SYS_AUCPU 148
+#define CLKID_SYS_CEC 149
+#define CLKID_SYS_GDC 150
+#define CLKID_SYS_DESWARP 151
+#define CLKID_SYS_AMPIPE_NAND 152
+#define CLKID_SYS_AMPIPE_ETH 153
+#define CLKID_SYS_AM2AXI0 154
+#define CLKID_SYS_AM2AXI1 155
+#define CLKID_SYS_AM2AXI2 156
+#define CLKID_SYS_SD_EMMC_A 157
+#define CLKID_SYS_SD_EMMC_B 158
+#define CLKID_SYS_SD_EMMC_C 159
+#define CLKID_SYS_SMARTCARD 160
+#define CLKID_SYS_ACODEC 161
+#define CLKID_SYS_SPIFC 162
+#define CLKID_SYS_MSR_CLK 163
+#define CLKID_SYS_IR_CTRL 164
+#define CLKID_SYS_AUDIO 165
+#define CLKID_SYS_ETH 166
+#define CLKID_SYS_UART_A 167
+#define CLKID_SYS_UART_B 168
+#define CLKID_SYS_UART_C 169
+#define CLKID_SYS_UART_D 170
+#define CLKID_SYS_UART_E 171
+#define CLKID_SYS_UART_F 172
+#define CLKID_SYS_AIFIFO 173
+#define CLKID_SYS_SPICC2 174
+#define CLKID_SYS_SPICC3 175
+#define CLKID_SYS_SPICC4 176
+#define CLKID_SYS_TS_A73 177
+#define CLKID_SYS_TS_A53 178
+#define CLKID_SYS_SPICC5 179
+#define CLKID_SYS_G2D 180
+#define CLKID_SYS_SPICC0 181
+#define CLKID_SYS_SPICC1 182
+#define CLKID_SYS_PCIE 183
+#define CLKID_SYS_USB 184
+#define CLKID_SYS_PCIE_PHY 185
+#define CLKID_SYS_I2C_AO_A 186
+#define CLKID_SYS_I2C_AO_B 187
+#define CLKID_SYS_I2C_M_A 188
+#define CLKID_SYS_I2C_M_B 189
+#define CLKID_SYS_I2C_M_C 190
+#define CLKID_SYS_I2C_M_D 191
+#define CLKID_SYS_I2C_M_E 192
+#define CLKID_SYS_I2C_M_F 193
+#define CLKID_SYS_HDMITX_APB 194
+#define CLKID_SYS_I2C_S_A 195
+#define CLKID_SYS_HDMIRX_PCLK 196
+#define CLKID_SYS_MMC_APB 197
+#define CLKID_SYS_MIPI_ISP_PCLK 198
+#define CLKID_SYS_RSA 199
+#define CLKID_SYS_PCLK_SYS_APB 200
+#define CLKID_SYS_A73PCLK_APB 201
+#define CLKID_SYS_DSPA 202
+#define CLKID_SYS_DSPB 203
+#define CLKID_SYS_VPU_INTR 204
+#define CLKID_SYS_SAR_ADC 205
+#define CLKID_SYS_GIC 206
+#define CLKID_SYS_TS_GPU 207
+#define CLKID_SYS_TS_NNA 208
+#define CLKID_SYS_TS_VPU 209
+#define CLKID_SYS_TS_HEVC 210
+#define CLKID_SYS_PWM_AB 211
+#define CLKID_SYS_PWM_CD 212
+#define CLKID_SYS_PWM_EF 213
+#define CLKID_SYS_PWM_AO_AB 214
+#define CLKID_SYS_PWM_AO_CD 215
+#define CLKID_SYS_PWM_AO_EF 216
+#define CLKID_SYS_PWM_AO_GH 217
+
+#endif /* __T7_PERIPHERALS_CLKC_H */
--
2.47.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v6 4/5] clk: meson: t7: add support for the T7 SoC PLL clock
2025-12-04 5:36 [PATCH v6 0/5] add support for T7 family clock controller Jian Hu
` (2 preceding siblings ...)
2025-12-04 5:36 ` [PATCH v6 3/5] dt-bindings: clock: add Amlogic T7 peripherals " Jian Hu
@ 2025-12-04 5:36 ` Jian Hu
2025-12-06 3:18 ` kernel test robot
2025-12-04 5:36 ` [PATCH v6 5/5] clk: meson: t7: add t7 clock peripherals controller driver Jian Hu
4 siblings, 1 reply; 13+ messages in thread
From: Jian Hu @ 2025-12-04 5:36 UTC (permalink / raw)
To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, robh+dt,
Rob Herring
Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
Add PLL clock controller driver for the Amlogic T7 SoC family.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
---
drivers/clk/meson/Kconfig | 14 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/t7-pll.c | 1074 ++++++++++++++++++++++++++++++++++++
3 files changed, 1089 insertions(+)
create mode 100644 drivers/clk/meson/t7-pll.c
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 71481607a6d5..c071de83f35b 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -201,4 +201,18 @@ config COMMON_CLK_S4_PERIPHERALS
help
Support for the peripherals clock controller on Amlogic S805X2 and S905Y4
devices, AKA S4. Say Y if you want S4 peripherals clock controller to work.
+
+config COMMON_CLK_T7_PLL
+ tristate "Amlogic T7 SoC PLL controller support"
+ depends on ARM64
+ default ARCH_MESON
+ select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_CLKC_UTILS
+ select COMMON_CLK_MESON_PLL
+ imply COMMON_CLK_SCMI
+ help
+ Support for the PLL clock controller on Amlogic A311D2 based
+ device, AKA T7. PLLs are required by most peripheral to operate.
+ Say Y if you want T7 PLL clock controller to work.
+
endmenu
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index c6998e752c68..8e3f7f94c639 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o
obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o
+obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o
diff --git a/drivers/clk/meson/t7-pll.c b/drivers/clk/meson/t7-pll.c
new file mode 100644
index 000000000000..0a622f45fa36
--- /dev/null
+++ b/drivers/clk/meson/t7-pll.c
@@ -0,0 +1,1074 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved.
+ * Author: Jian Hu <jian.hu@amlogic.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "clk-mpll.h"
+#include "meson-clkc-utils.h"
+#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
+
+#define GP0PLL_CTRL0 0x00
+#define GP0PLL_CTRL1 0x04
+#define GP0PLL_CTRL2 0x08
+#define GP0PLL_CTRL3 0x0c
+#define GP0PLL_CTRL4 0x10
+#define GP0PLL_CTRL5 0x14
+#define GP0PLL_CTRL6 0x18
+#define GP0PLL_STS 0x1c
+
+#define GP1PLL_CTRL0 0x00
+#define GP1PLL_CTRL1 0x04
+#define GP1PLL_CTRL2 0x08
+#define GP1PLL_CTRL3 0x0c
+#define GP1PLL_STS 0x1c
+
+#define HIFIPLL_CTRL0 0x00
+#define HIFIPLL_CTRL1 0x04
+#define HIFIPLL_CTRL2 0x08
+#define HIFIPLL_CTRL3 0x0c
+#define HIFIPLL_CTRL4 0x10
+#define HIFIPLL_CTRL5 0x14
+#define HIFIPLL_CTRL6 0x18
+#define HIFIPLL_STS 0x1c
+
+#define PCIEPLL_CTRL0 0x00
+#define PCIEPLL_CTRL1 0x04
+#define PCIEPLL_CTRL2 0x08
+#define PCIEPLL_CTRL3 0x0c
+#define PCIEPLL_CTRL4 0x10
+#define PCIEPLL_CTRL5 0x14
+#define PCIEPLL_STS 0x18
+
+#define MPLL_CTRL0 0x00
+#define MPLL_CTRL1 0x04
+#define MPLL_CTRL2 0x08
+#define MPLL_CTRL3 0x0c
+#define MPLL_CTRL4 0x10
+#define MPLL_CTRL5 0x14
+#define MPLL_CTRL6 0x18
+#define MPLL_CTRL7 0x1c
+#define MPLL_CTRL8 0x20
+#define MPLL_STS 0x24
+
+#define HDMIPLL_CTRL0 0x00
+#define HDMIPLL_CTRL1 0x04
+#define HDMIPLL_CTRL2 0x08
+#define HDMIPLL_CTRL3 0x0c
+#define HDMIPLL_CTRL4 0x10
+#define HDMIPLL_CTRL5 0x14
+#define HDMIPLL_CTRL6 0x18
+#define HDMIPLL_STS 0x1c
+
+#define MCLK_PLL_CNTL0 0x00
+#define MCLK_PLL_CNTL1 0x04
+#define MCLK_PLL_CNTL2 0x08
+#define MCLK_PLL_CNTL3 0x0c
+#define MCLK_PLL_CNTL4 0x10
+#define MCLK_PLL_STS 0x14
+
+static const struct pll_mult_range t7_media_pll_mult_range = {
+ .min = 125,
+ .max = 250,
+};
+
+static const struct reg_sequence t7_gp0_init_regs[] = {
+ { .reg = GP0PLL_CTRL1, .def = 0x00000000 },
+ { .reg = GP0PLL_CTRL2, .def = 0x00000000 },
+ { .reg = GP0PLL_CTRL3, .def = 0x48681c00 },
+ { .reg = GP0PLL_CTRL4, .def = 0x88770290 },
+ { .reg = GP0PLL_CTRL5, .def = 0x3927200a },
+ { .reg = GP0PLL_CTRL6, .def = 0x56540000 },
+};
+
+static struct clk_regmap t7_gp0_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .l = {
+ .reg_off = GP0PLL_STS,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .range = &t7_media_pll_mult_range,
+ .init_regs = t7_gp0_init_regs,
+ .init_count = ARRAY_SIZE(t7_gp0_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gp0_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "in0",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_gp0_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = GP0PLL_CTRL0,
+ .shift = 16,
+ .width = 3,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "gp0_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_gp0_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/*
+ * Compared with GP0 PLL, GP1 PLL is a newly designed PLL with
+ * a DCO range of 1.6GHz to 3.2GHz.
+ */
+static const struct pll_mult_range t7_gp1_pll_mult_range = {
+ .min = 67,
+ .max = 133,
+};
+
+static const struct reg_sequence t7_gp1_init_regs[] = {
+ { .reg = GP1PLL_CTRL1, .def = 0x1420500f },
+ { .reg = GP1PLL_CTRL2, .def = 0x00023001 },
+ { .reg = GP1PLL_CTRL3, .def = 0x00000000 },
+};
+
+static struct clk_regmap t7_gp1_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = GP1PLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = GP1PLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = GP1PLL_CTRL0,
+ .shift = 16,
+ .width = 5,
+ },
+ .l = {
+ .reg_off = GP1PLL_STS,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = GP1PLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .range = &t7_gp1_pll_mult_range,
+ .init_regs = t7_gp1_init_regs,
+ .init_count = ARRAY_SIZE(t7_gp1_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gp1_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "in0",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_gp1_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = GP1PLL_CTRL0,
+ .shift = 12,
+ .width = 3,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "gp1_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_gp1_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence t7_hifi_init_regs[] = {
+ { .reg = HIFIPLL_CTRL1, .def = 0x00000000 },
+ { .reg = HIFIPLL_CTRL2, .def = 0x00000000 },
+ { .reg = HIFIPLL_CTRL3, .def = 0x6a285c00 },
+ { .reg = HIFIPLL_CTRL4, .def = 0x65771290 },
+ { .reg = HIFIPLL_CTRL5, .def = 0x3927200a },
+ { .reg = HIFIPLL_CTRL6, .def = 0x56540000 }
+};
+
+static struct clk_regmap t7_hifi_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = HIFIPLL_CTRL1,
+ .shift = 0,
+ .width = 17,
+ },
+ .l = {
+ .reg_off = HIFIPLL_STS,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .range = &t7_media_pll_mult_range,
+ .init_regs = t7_hifi_init_regs,
+ .init_count = ARRAY_SIZE(t7_hifi_init_regs),
+ .frac_max = 100000,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hifi_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "in0",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_hifi_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HIFIPLL_CTRL0,
+ .shift = 16,
+ .width = 2,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hifi_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_hifi_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/*
+ * The T7 PCIE PLL is fined tuned to deliver a very precise
+ * 100MHz reference clock for the PCIe Analog PHY, and thus requires
+ * a strict register sequence to enable the PLL.
+ */
+static const struct reg_sequence t7_pcie_pll_init_regs[] = {
+ { .reg = PCIEPLL_CTRL0, .def = 0x200c04c8 },
+ { .reg = PCIEPLL_CTRL0, .def = 0x300c04c8 },
+ { .reg = PCIEPLL_CTRL1, .def = 0x30000000 },
+ { .reg = PCIEPLL_CTRL2, .def = 0x00001100 },
+ { .reg = PCIEPLL_CTRL3, .def = 0x10058e00 },
+ { .reg = PCIEPLL_CTRL4, .def = 0x000100c0 },
+ { .reg = PCIEPLL_CTRL5, .def = 0x68000048 },
+ { .reg = PCIEPLL_CTRL5, .def = 0x68000068, .delay_us = 20 },
+ { .reg = PCIEPLL_CTRL4, .def = 0x008100c0, .delay_us = 20 },
+ { .reg = PCIEPLL_CTRL0, .def = 0x340c04c8 },
+ { .reg = PCIEPLL_CTRL0, .def = 0x140c04c8, .delay_us = 20 },
+ { .reg = PCIEPLL_CTRL2, .def = 0x00001000 }
+};
+
+static struct clk_regmap t7_pcie_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = PCIEPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = PCIEPLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = PCIEPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .l = {
+ .reg_off = PCIEPLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = PCIEPLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .init_regs = t7_pcie_pll_init_regs,
+ .init_count = ARRAY_SIZE(t7_pcie_pll_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie_pll_dco",
+ .ops = &meson_clk_pcie_pll_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "in0",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor t7_pcie_pll_dco_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie_pll_dco_div2",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_pcie_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_pcie_pll_od = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = PCIEPLL_CTRL0,
+ .shift = 16,
+ .width = 5,
+ /* the divisor is 32 when [16:21] = 0 */
+ .flags = CLK_DIVIDER_MAX_AT_ZERO,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie_pll_od",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_pcie_pll_dco_div2.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_fixed_factor t7_pcie_pll = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie_pll",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_pcie_pll_od.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_fixed_factor t7_mpll_prediv = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll_prediv",
+ .ops = &clk_fixed_factor_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "in0",
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct reg_sequence t7_mpll0_init_regs[] = {
+ { .reg = MPLL_CTRL2, .def = 0x40000033 }
+};
+
+static struct clk_regmap t7_mpll0_div = {
+ .data = &(struct meson_clk_mpll_data){
+ .sdm = {
+ .reg_off = MPLL_CTRL1,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = MPLL_CTRL1,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = MPLL_CTRL1,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg_off = MPLL_CTRL1,
+ .shift = 29,
+ .width = 1,
+ },
+ .init_regs = t7_mpll0_init_regs,
+ .init_count = ARRAY_SIZE(t7_mpll0_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll0_div",
+ .ops = &meson_clk_mpll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mpll_prediv.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_mpll0 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MPLL_CTRL1,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &t7_mpll0_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence t7_mpll1_init_regs[] = {
+ { .reg = MPLL_CTRL4, .def = 0x40000033 }
+};
+
+static struct clk_regmap t7_mpll1_div = {
+ .data = &(struct meson_clk_mpll_data){
+ .sdm = {
+ .reg_off = MPLL_CTRL3,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = MPLL_CTRL3,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = MPLL_CTRL3,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg_off = MPLL_CTRL3,
+ .shift = 29,
+ .width = 1,
+ },
+ .init_regs = t7_mpll1_init_regs,
+ .init_count = ARRAY_SIZE(t7_mpll1_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll1_div",
+ .ops = &meson_clk_mpll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mpll_prediv.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_mpll1 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MPLL_CTRL3,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &t7_mpll1_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence t7_mpll2_init_regs[] = {
+ { .reg = MPLL_CTRL6, .def = 0x40000033 }
+};
+
+static struct clk_regmap t7_mpll2_div = {
+ .data = &(struct meson_clk_mpll_data){
+ .sdm = {
+ .reg_off = MPLL_CTRL5,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = MPLL_CTRL5,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = MPLL_CTRL5,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg_off = MPLL_CTRL5,
+ .shift = 29,
+ .width = 1,
+ },
+ .init_regs = t7_mpll2_init_regs,
+ .init_count = ARRAY_SIZE(t7_mpll2_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll2_div",
+ .ops = &meson_clk_mpll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mpll_prediv.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_mpll2 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MPLL_CTRL5,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll2",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &t7_mpll2_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence t7_mpll3_init_regs[] = {
+ { .reg = MPLL_CTRL8, .def = 0x40000033 }
+};
+
+static struct clk_regmap t7_mpll3_div = {
+ .data = &(struct meson_clk_mpll_data){
+ .sdm = {
+ .reg_off = MPLL_CTRL7,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = MPLL_CTRL7,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = MPLL_CTRL7,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg_off = MPLL_CTRL7,
+ .shift = 29,
+ .width = 1,
+ },
+ .init_regs = t7_mpll3_init_regs,
+ .init_count = ARRAY_SIZE(t7_mpll3_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll3_div",
+ .ops = &meson_clk_mpll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mpll_prediv.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_mpll3 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MPLL_CTRL7,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll3",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &t7_mpll3_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence t7_hdmi_init_regs[] = {
+ { .reg = HDMIPLL_CTRL1, .def = 0x00000000 },
+ { .reg = HDMIPLL_CTRL2, .def = 0x00000000 },
+ { .reg = HDMIPLL_CTRL3, .def = 0x6a28dc00 },
+ { .reg = HDMIPLL_CTRL4, .def = 0x65771290 },
+ { .reg = HDMIPLL_CTRL5, .def = 0x39272000 },
+ { .reg = HDMIPLL_CTRL6, .def = 0x56540000 }
+};
+
+static struct clk_regmap t7_hdmi_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = HDMIPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = HDMIPLL_CTRL0,
+ .shift = 0,
+ .width = 9,
+ },
+ .n = {
+ .reg_off = HDMIPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .l = {
+ .reg_off = HDMIPLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = HDMIPLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .range = &t7_media_pll_mult_range,
+ .init_regs = t7_hdmi_init_regs,
+ .init_count = ARRAY_SIZE(t7_hdmi_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hdmi_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "in0", }
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_hdmi_pll_od = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HDMIPLL_CTRL0,
+ .shift = 16,
+ .width = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hdmi_pll_od",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_hdmi_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_hdmi_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HDMIPLL_CTRL0,
+ .shift = 20,
+ .width = 2,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hdmi_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_hdmi_pll_od.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct pll_mult_range t7_mclk_pll_mult_range = {
+ .min = 67,
+ .max = 133,
+};
+
+static const struct reg_sequence t7_mclk_init_regs[] = {
+ { .reg = MCLK_PLL_CNTL1, .def = 0x1470500f },
+ { .reg = MCLK_PLL_CNTL2, .def = 0x00023001 },
+ { .reg = MCLK_PLL_CNTL3, .def = 0x18180000 },
+ { .reg = MCLK_PLL_CNTL4, .def = 0x00180303 },
+};
+
+static struct clk_regmap t7_mclk_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = MCLK_PLL_CNTL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = MCLK_PLL_CNTL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = MCLK_PLL_CNTL0,
+ .shift = 16,
+ .width = 5,
+ },
+ .l = {
+ .reg_off = MCLK_PLL_CNTL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = MCLK_PLL_CNTL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .l_detect = {
+ .reg_off = MCLK_PLL_CNTL2,
+ .shift = 6,
+ .width = 1,
+ },
+ .range = &t7_mclk_pll_mult_range,
+ .init_regs = t7_mclk_init_regs,
+ .init_count = ARRAY_SIZE(t7_mclk_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mclk_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "in0",
+ },
+ .num_parents = 1,
+ },
+};
+
+/* max div is 16 */
+static const struct clk_div_table t7_mclk_div[] = {
+ { .val = 0, .div = 1 },
+ { .val = 1, .div = 2 },
+ { .val = 2, .div = 4 },
+ { .val = 3, .div = 8 },
+ { .val = 4, .div = 16 },
+ { /* sentinel */ }
+};
+
+static struct clk_regmap t7_mclk_pre_od = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = MCLK_PLL_CNTL0,
+ .shift = 12,
+ .width = 3,
+ .table = t7_mclk_div,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mclk_pre_od",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mclk_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mclk_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = MCLK_PLL_CNTL4,
+ .shift = 16,
+ .width = 5,
+ .flags = CLK_DIVIDER_ONE_BASED,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mclk_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mclk_pre_od.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mclk_0_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = MCLK_PLL_CNTL4,
+ .mask = 0x3,
+ .shift = 4,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mclk_0_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .hw = &t7_mclk_pll.hw },
+ { .fw_name = "in1", },
+ { .fw_name = "in2", },
+ },
+ .num_parents = 3,
+ },
+};
+
+static struct clk_fixed_factor t7_mclk_0_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "mclk_0_div2",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) { &t7_mclk_0_sel.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mclk_0_pre = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MCLK_PLL_CNTL4,
+ .bit_idx = 2,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mclk_0_pre",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mclk_0_div2.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mclk_0 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MCLK_PLL_CNTL4,
+ .bit_idx = 0,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mclk_0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mclk_0_pre.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mclk_1_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = MCLK_PLL_CNTL4,
+ .mask = 0x3,
+ .shift = 12,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mclk_1_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .hw = &t7_mclk_pll.hw },
+ { .fw_name = "in1", },
+ { .fw_name = "in2", },
+ },
+ .num_parents = 3,
+ },
+};
+
+static struct clk_fixed_factor t7_mclk_1_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "mclk_1_div2",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) { &t7_mclk_1_sel.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mclk_1_pre = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MCLK_PLL_CNTL4,
+ .bit_idx = 10,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mclk_1_pre",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mclk_1_div2.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mclk_1 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MCLK_PLL_CNTL4,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mclk_1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mclk_1_pre.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_hw *t7_gp0_hw_clks[] = {
+ [CLKID_GP0_PLL_DCO] = &t7_gp0_pll_dco.hw,
+ [CLKID_GP0_PLL] = &t7_gp0_pll.hw,
+};
+
+static struct clk_hw *t7_gp1_hw_clks[] = {
+ [CLKID_GP1_PLL_DCO] = &t7_gp1_pll_dco.hw,
+ [CLKID_GP1_PLL] = &t7_gp1_pll.hw,
+};
+
+static struct clk_hw *t7_hifi_hw_clks[] = {
+ [CLKID_HIFI_PLL_DCO] = &t7_hifi_pll_dco.hw,
+ [CLKID_HIFI_PLL] = &t7_hifi_pll.hw,
+};
+
+static struct clk_hw *t7_pcie_hw_clks[] = {
+ [CLKID_PCIE_PLL_DCO] = &t7_pcie_pll_dco.hw,
+ [CLKID_PCIE_PLL_DCO_DIV2] = &t7_pcie_pll_dco_div2.hw,
+ [CLKID_PCIE_PLL_OD] = &t7_pcie_pll_od.hw,
+ [CLKID_PCIE_PLL] = &t7_pcie_pll.hw,
+};
+
+static struct clk_hw *t7_mpll_hw_clks[] = {
+ [CLKID_MPLL_PREDIV] = &t7_mpll_prediv.hw,
+ [CLKID_MPLL0_DIV] = &t7_mpll0_div.hw,
+ [CLKID_MPLL0] = &t7_mpll0.hw,
+ [CLKID_MPLL1_DIV] = &t7_mpll1_div.hw,
+ [CLKID_MPLL1] = &t7_mpll1.hw,
+ [CLKID_MPLL2_DIV] = &t7_mpll2_div.hw,
+ [CLKID_MPLL2] = &t7_mpll2.hw,
+ [CLKID_MPLL3_DIV] = &t7_mpll3_div.hw,
+ [CLKID_MPLL3] = &t7_mpll3.hw,
+};
+
+static struct clk_hw *t7_hdmi_hw_clks[] = {
+ [CLKID_HDMI_PLL_DCO] = &t7_hdmi_pll_dco.hw,
+ [CLKID_HDMI_PLL_OD] = &t7_hdmi_pll_od.hw,
+ [CLKID_HDMI_PLL] = &t7_hdmi_pll.hw,
+};
+
+static struct clk_hw *t7_mclk_hw_clks[] = {
+ [CLKID_MCLK_PLL_DCO] = &t7_mclk_pll_dco.hw,
+ [CLKID_MCLK_PRE] = &t7_mclk_pre_od.hw,
+ [CLKID_MCLK_PLL] = &t7_mclk_pll.hw,
+ [CLKID_MCLK_0_SEL] = &t7_mclk_0_sel.hw,
+ [CLKID_MCLK_0_DIV2] = &t7_mclk_0_div2.hw,
+ [CLKID_MCLK_0_PRE] = &t7_mclk_0_pre.hw,
+ [CLKID_MCLK_0] = &t7_mclk_0.hw,
+ [CLKID_MCLK_1_SEL] = &t7_mclk_1_sel.hw,
+ [CLKID_MCLK_1_DIV2] = &t7_mclk_1_div2.hw,
+ [CLKID_MCLK_1_PRE] = &t7_mclk_1_pre.hw,
+ [CLKID_MCLK_1] = &t7_mclk_1.hw,
+};
+
+static const struct meson_clkc_data t7_gp0_data = {
+ .hw_clks = {
+ .hws = t7_gp0_hw_clks,
+ .num = ARRAY_SIZE(t7_gp0_hw_clks),
+ },
+};
+
+static const struct meson_clkc_data t7_gp1_data = {
+ .hw_clks = {
+ .hws = t7_gp1_hw_clks,
+ .num = ARRAY_SIZE(t7_gp1_hw_clks),
+ },
+};
+
+static const struct meson_clkc_data t7_hifi_data = {
+ .hw_clks = {
+ .hws = t7_hifi_hw_clks,
+ .num = ARRAY_SIZE(t7_hifi_hw_clks),
+ },
+};
+
+static const struct meson_clkc_data t7_pcie_data = {
+ .hw_clks = {
+ .hws = t7_pcie_hw_clks,
+ .num = ARRAY_SIZE(t7_pcie_hw_clks),
+ },
+};
+
+static const struct reg_sequence t7_mpll_init_regs[] = {
+ { .reg = MPLL_CTRL0, .def = 0x00000543 }
+};
+
+static const struct meson_clkc_data t7_mpll_data = {
+ .hw_clks = {
+ .hws = t7_mpll_hw_clks,
+ .num = ARRAY_SIZE(t7_mpll_hw_clks),
+ },
+ .init_regs = t7_mpll_init_regs,
+ .init_count = ARRAY_SIZE(t7_mpll_init_regs),
+};
+
+static const struct meson_clkc_data t7_hdmi_data = {
+ .hw_clks = {
+ .hws = t7_hdmi_hw_clks,
+ .num = ARRAY_SIZE(t7_hdmi_hw_clks),
+ },
+};
+
+static const struct meson_clkc_data t7_mclk_data = {
+ .hw_clks = {
+ .hws = t7_mclk_hw_clks,
+ .num = ARRAY_SIZE(t7_mclk_hw_clks),
+ },
+};
+
+static const struct of_device_id t7_pll_clkc_match_table[] = {
+ { .compatible = "amlogic,t7-gp0-pll", .data = &t7_gp0_data, },
+ { .compatible = "amlogic,t7-gp1-pll", .data = &t7_gp1_data, },
+ { .compatible = "amlogic,t7-hifi-pll", .data = &t7_hifi_data, },
+ { .compatible = "amlogic,t7-pcie-pll", .data = &t7_pcie_data, },
+ { .compatible = "amlogic,t7-mpll", .data = &t7_mpll_data, },
+ { .compatible = "amlogic,t7-hdmi-pll", .data = &t7_hdmi_data, },
+ { .compatible = "amlogic,t7-mclk-pll", .data = &t7_mclk_data, },
+ {}
+};
+MODULE_DEVICE_TABLE(of, t7_pll_clkc_match_table);
+
+static struct platform_driver t7_pll_clkc_driver = {
+ .probe = meson_clkc_mmio_probe,
+ .driver = {
+ .name = "t7-pll-clkc",
+ .of_match_table = t7_pll_clkc_match_table,
+ },
+};
+module_platform_driver(t7_pll_clkc_driver);
+
+MODULE_DESCRIPTION("Amlogic T7 PLL Clock Controller driver");
+MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("CLK_MESON");
--
2.47.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v6 5/5] clk: meson: t7: add t7 clock peripherals controller driver
2025-12-04 5:36 [PATCH v6 0/5] add support for T7 family clock controller Jian Hu
` (3 preceding siblings ...)
2025-12-04 5:36 ` [PATCH v6 4/5] clk: meson: t7: add support for the T7 SoC PLL clock Jian Hu
@ 2025-12-04 5:36 ` Jian Hu
4 siblings, 0 replies; 13+ messages in thread
From: Jian Hu @ 2025-12-04 5:36 UTC (permalink / raw)
To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, robh+dt,
Rob Herring
Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
Add Peripheral clock controller driver for the Amlogic T7 SoC family.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
---
drivers/clk/meson/Kconfig | 13 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/t7-peripherals.c | 1271 ++++++++++++++++++++++++++++
3 files changed, 1285 insertions(+)
create mode 100644 drivers/clk/meson/t7-peripherals.c
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index c071de83f35b..ad35b171485c 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -215,4 +215,17 @@ config COMMON_CLK_T7_PLL
device, AKA T7. PLLs are required by most peripheral to operate.
Say Y if you want T7 PLL clock controller to work.
+config COMMON_CLK_T7_PERIPHERALS
+ tristate "Amlogic T7 SoC peripherals clock controller support"
+ depends on ARM64
+ default ARCH_MESON
+ select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_CLKC_UTILS
+ select COMMON_CLK_MESON_DUALDIV
+ imply COMMON_CLK_SCMI
+ imply COMMON_CLK_T7_PLL
+ help
+ Support for the peripherals clock controller on Amlogic A311D2 based
+ device, AKA T7. Peripherals are required by most peripheral to operate.
+ Say Y if you want T7 peripherals clock controller to work.
endmenu
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 8e3f7f94c639..c6719694a242 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -27,3 +27,4 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o
obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o
obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o
+obj-$(CONFIG_COMMON_CLK_T7_PERIPHERALS) += t7-peripherals.o
diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peripherals.c
new file mode 100644
index 000000000000..214db7850d86
--- /dev/null
+++ b/drivers/clk/meson/t7-peripherals.c
@@ -0,0 +1,1271 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved.
+ * Author: Jian Hu <jian.hu@amlogic.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include "clk-dualdiv.h"
+#include "clk-regmap.h"
+#include "meson-clkc-utils.h"
+#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>
+
+#define RTC_BY_OSCIN_CTRL0 0x8
+#define RTC_BY_OSCIN_CTRL1 0xc
+#define RTC_CTRL 0x10
+#define SYS_CLK_CTRL0 0x40
+#define SYS_CLK_EN0_REG0 0x44
+#define SYS_CLK_EN0_REG1 0x48
+#define SYS_CLK_EN0_REG2 0x4c
+#define SYS_CLK_EN0_REG3 0x50
+#define CECA_CTRL0 0x88
+#define CECA_CTRL1 0x8c
+#define CECB_CTRL0 0x90
+#define CECB_CTRL1 0x94
+#define SC_CLK_CTRL 0x98
+#define DSPA_CLK_CTRL0 0x9c
+#define DSPB_CLK_CTRL0 0xa0
+#define CLK12_24_CTRL 0xa8
+#define ANAKIN_CLK_CTRL 0xac
+#define MIPI_CSI_PHY_CLK_CTRL 0x10c
+#define MIPI_ISP_CLK_CTRL 0x110
+#define TS_CLK_CTRL 0x158
+#define MALI_CLK_CTRL 0x15c
+#define ETH_CLK_CTRL 0x164
+#define NAND_CLK_CTRL 0x168
+#define SD_EMMC_CLK_CTRL 0x16c
+#define SPICC_CLK_CTRL 0x174
+#define SAR_CLK_CTRL0 0x17c
+#define PWM_CLK_AB_CTRL 0x180
+#define PWM_CLK_CD_CTRL 0x184
+#define PWM_CLK_EF_CTRL 0x188
+#define PWM_CLK_AO_AB_CTRL 0x1a0
+#define PWM_CLK_AO_CD_CTRL 0x1a4
+#define PWM_CLK_AO_EF_CTRL 0x1a8
+#define PWM_CLK_AO_GH_CTRL 0x1ac
+#define SPICC_CLK_CTRL1 0x1c0
+#define SPICC_CLK_CTRL2 0x1c4
+
+#define T7_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
+ MESON_COMP_SEL(t7_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)
+
+#define T7_COMP_DIV(_name, _reg, _shift, _width) \
+ MESON_COMP_DIV(t7_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)
+
+#define T7_COMP_GATE(_name, _reg, _bit, _iflags) \
+ MESON_COMP_GATE(t7_, _name, _reg, _bit, CLK_SET_RATE_PARENT | (_iflags))
+
+static struct clk_regmap t7_rtc_dualdiv_in = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = RTC_BY_OSCIN_CTRL0,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_duandiv_in",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct meson_clk_dualdiv_param t7_dualdiv_table[] = {
+ {
+ .n1 = 733, .m1 = 8,
+ .n2 = 732, .m2 = 11,
+ .dual = 1,
+ },
+ {}
+};
+
+static struct clk_regmap t7_rtc_dualdiv_div = {
+ .data = &(struct meson_clk_dualdiv_data){
+ .n1 = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 0,
+ .width = 12,
+ },
+ .n2 = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 12,
+ .width = 12,
+ },
+ .m1 = {
+ .reg_off = RTC_BY_OSCIN_CTRL1,
+ .shift = 0,
+ .width = 12,
+ },
+ .m2 = {
+ .reg_off = RTC_BY_OSCIN_CTRL1,
+ .shift = 12,
+ .width = 12,
+ },
+ .dual = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .table = t7_dualdiv_table,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "rtc_dualdiv_div",
+ .ops = &meson_clk_dualdiv_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_rtc_dualdiv_in.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_rtc_dualdiv_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = RTC_BY_OSCIN_CTRL1,
+ .mask = 0x1,
+ .shift = 24,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "rtc_dualdiv_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_rtc_dualdiv_div.hw,
+ &t7_rtc_dualdiv_in.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_rtc_dualdiv = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = RTC_BY_OSCIN_CTRL0,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_dualdiv",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_rtc_dualdiv_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_rtc = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = RTC_CTRL,
+ .mask = 0x3,
+ .shift = 0,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "rtc",
+ .ops = &clk_regmap_mux_ops,
+ /*
+ * xtal is also on parent input #3 but that it is not useful to CCF since
+ * the same parent is available with parent input #0
+ */
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal", },
+ { .hw = &t7_rtc_dualdiv.hw },
+ { .fw_name = "ext_rtc", },
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_NO_REPARENT,
+ },
+};
+
+static struct clk_regmap t7_ceca_dualdiv_in = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CECA_CTRL0,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "ceca_dualdiv_in",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_ceca_dualdiv_div = {
+ .data = &(struct meson_clk_dualdiv_data){
+ .n1 = {
+ .reg_off = CECA_CTRL0,
+ .shift = 0,
+ .width = 12,
+ },
+ .n2 = {
+ .reg_off = CECA_CTRL0,
+ .shift = 12,
+ .width = 12,
+ },
+ .m1 = {
+ .reg_off = CECA_CTRL1,
+ .shift = 0,
+ .width = 12,
+ },
+ .m2 = {
+ .reg_off = CECA_CTRL1,
+ .shift = 12,
+ .width = 12,
+ },
+ .dual = {
+ .reg_off = CECA_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .table = t7_dualdiv_table,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ceca_dualdiv_div",
+ .ops = &meson_clk_dualdiv_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_ceca_dualdiv_in.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_ceca_dualdiv_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CECA_CTRL1,
+ .mask = 0x1,
+ .shift = 24,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ceca_dualdiv_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_ceca_dualdiv_div.hw,
+ &t7_ceca_dualdiv_in.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_ceca_dualdiv = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CECA_CTRL0,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ceca_dualdiv",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_ceca_dualdiv_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_ceca = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CECA_CTRL1,
+ .mask = 0x1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ceca",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_ceca_dualdiv.hw,
+ &t7_rtc.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_cecb_dualdiv_in = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CECB_CTRL0,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "cecb_dualdiv_in",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_cecb_dualdiv_div = {
+ .data = &(struct meson_clk_dualdiv_data){
+ .n1 = {
+ .reg_off = CECB_CTRL0,
+ .shift = 0,
+ .width = 12,
+ },
+ .n2 = {
+ .reg_off = CECB_CTRL0,
+ .shift = 12,
+ .width = 12,
+ },
+ .m1 = {
+ .reg_off = CECB_CTRL1,
+ .shift = 0,
+ .width = 12,
+ },
+ .m2 = {
+ .reg_off = CECB_CTRL1,
+ .shift = 12,
+ .width = 12,
+ },
+ .dual = {
+ .reg_off = CECB_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .table = t7_dualdiv_table,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cecb_dualdiv_div",
+ .ops = &meson_clk_dualdiv_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_cecb_dualdiv_in.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_cecb_dualdiv_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CECB_CTRL1,
+ .mask = 0x1,
+ .shift = 24,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cecb_dualdiv_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_cecb_dualdiv_div.hw,
+ &t7_cecb_dualdiv_in.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_cecb_dualdiv = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CECB_CTRL0,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cecb_dualdiv",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_cecb_dualdiv_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_cecb = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CECB_CTRL1,
+ .mask = 0x1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cecb",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_cecb_dualdiv.hw,
+ &t7_rtc.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data t7_sc_parents[] = {
+ { .fw_name = "fdiv4", },
+ { .fw_name = "fdiv3", },
+ { .fw_name = "fdiv5", },
+ { .fw_name = "xtal", },
+};
+
+static T7_COMP_SEL(sc, SC_CLK_CTRL, 9, 0x3, t7_sc_parents);
+static T7_COMP_DIV(sc, SC_CLK_CTRL, 0, 8);
+static T7_COMP_GATE(sc, SC_CLK_CTRL, 8, 0);
+
+static const struct clk_parent_data t7_dsp_parents[] = {
+ { .fw_name = "xtal", },
+ { .fw_name = "fdiv2p5", },
+ { .fw_name = "fdiv3", },
+ { .fw_name = "fdiv5", },
+ { .fw_name = "hifi", },
+ { .fw_name = "fdiv4", },
+ { .fw_name = "fdiv7", },
+ { .hw = &t7_rtc.hw },
+};
+
+static T7_COMP_SEL(dspa_0, DSPA_CLK_CTRL0, 10, 0x7, t7_dsp_parents);
+static T7_COMP_DIV(dspa_0, DSPA_CLK_CTRL0, 0, 10);
+static T7_COMP_GATE(dspa_0, DSPA_CLK_CTRL0, 13, CLK_SET_RATE_GATE);
+
+static T7_COMP_SEL(dspa_1, DSPA_CLK_CTRL0, 26, 0x7, t7_dsp_parents);
+static T7_COMP_DIV(dspa_1, DSPA_CLK_CTRL0, 16, 10);
+static T7_COMP_GATE(dspa_1, DSPA_CLK_CTRL0, 29, CLK_SET_RATE_GATE);
+
+static struct clk_regmap t7_dspa = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DSPA_CLK_CTRL0,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspa",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_dspa_0.hw,
+ &t7_dspa_1.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static T7_COMP_SEL(dspb_0, DSPB_CLK_CTRL0, 10, 0x7, t7_dsp_parents);
+static T7_COMP_DIV(dspb_0, DSPB_CLK_CTRL0, 0, 10);
+static T7_COMP_GATE(dspb_0, DSPB_CLK_CTRL0, 13, CLK_SET_RATE_GATE);
+
+static T7_COMP_SEL(dspb_1, DSPB_CLK_CTRL0, 26, 0x7, t7_dsp_parents);
+static T7_COMP_DIV(dspb_1, DSPB_CLK_CTRL0, 16, 10);
+static T7_COMP_GATE(dspb_1, DSPB_CLK_CTRL0, 29, CLK_SET_RATE_GATE);
+
+static struct clk_regmap t7_dspb = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DSPB_CLK_CTRL0,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspb",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_dspb_0.hw,
+ &t7_dspb_1.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_24m = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CLK12_24_CTRL,
+ .bit_idx = 11,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "24m",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor t7_24m_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "24m_div2",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_24m.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_12m = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CLK12_24_CTRL,
+ .bit_idx = 10,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "12m",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_24m_div2.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_25m_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = CLK12_24_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "25m_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "fix",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_25m = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CLK12_24_CTRL,
+ .bit_idx = 12,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "25m",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_25m_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data t7_anakin_parents[] = {
+ { .fw_name = "fdiv4", },
+ { .fw_name = "fdiv3", },
+ { .fw_name = "fdiv5", },
+ { .fw_name = "fdiv2", },
+ { .fw_name = "vid_pll0", },
+ { .fw_name = "mpll1", },
+ { .fw_name = "mpll2", },
+ { .fw_name = "fdiv2p5", },
+};
+
+static T7_COMP_SEL(anakin_0, ANAKIN_CLK_CTRL, 9, 0x7, t7_anakin_parents);
+static T7_COMP_DIV(anakin_0, ANAKIN_CLK_CTRL, 0, 7);
+static T7_COMP_GATE(anakin_0, ANAKIN_CLK_CTRL, 8, CLK_SET_RATE_GATE);
+
+static T7_COMP_SEL(anakin_1, ANAKIN_CLK_CTRL, 25, 0x7, t7_anakin_parents);
+static T7_COMP_DIV(anakin_1, ANAKIN_CLK_CTRL, 16, 7);
+static T7_COMP_GATE(anakin_1, ANAKIN_CLK_CTRL, 24, CLK_SET_RATE_GATE);
+
+static struct clk_regmap t7_anakin_01_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = ANAKIN_CLK_CTRL,
+ .mask = 1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "anakin_01_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_anakin_0.hw,
+ &t7_anakin_1.hw
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT
+ },
+};
+
+static struct clk_regmap t7_anakin = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANAKIN_CLK_CTRL,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "anakin",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_anakin_01_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT
+ },
+};
+
+static const struct clk_parent_data t7_mipi_csi_phy_parents[] = {
+ { .fw_name = "xtal", },
+ { .fw_name = "gp1", },
+ { .fw_name = "mpll1", },
+ { .fw_name = "mpll2", },
+ { .fw_name = "fdiv3", },
+ { .fw_name = "fdiv4", },
+ { .fw_name = "fdiv5", },
+ { .fw_name = "fdiv7", },
+};
+
+static T7_COMP_SEL(mipi_csi_phy_0, MIPI_CSI_PHY_CLK_CTRL, 9, 0x7, t7_mipi_csi_phy_parents);
+static T7_COMP_DIV(mipi_csi_phy_0, MIPI_CSI_PHY_CLK_CTRL, 0, 7);
+static T7_COMP_GATE(mipi_csi_phy_0, MIPI_CSI_PHY_CLK_CTRL, 8, CLK_SET_RATE_GATE);
+
+static T7_COMP_SEL(mipi_csi_phy_1, MIPI_CSI_PHY_CLK_CTRL, 25, 0x7, t7_mipi_csi_phy_parents);
+static T7_COMP_DIV(mipi_csi_phy_1, MIPI_CSI_PHY_CLK_CTRL, 16, 7);
+static T7_COMP_GATE(mipi_csi_phy_1, MIPI_CSI_PHY_CLK_CTRL, 24, CLK_SET_RATE_GATE);
+
+static struct clk_regmap t7_mipi_csi_phy = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = MIPI_CSI_PHY_CLK_CTRL,
+ .mask = 0x1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mipi_csi_phy",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mipi_csi_phy_0.hw,
+ &t7_mipi_csi_phy_1.hw
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data t7_mipi_isp_parents[] = {
+ { .fw_name = "xtal", },
+ { .fw_name = "fdiv4", },
+ { .fw_name = "fdiv3", },
+ { .fw_name = "fdiv5", },
+ { .fw_name = "fdiv7", },
+ { .fw_name = "mpll2", },
+ { .fw_name = "mpll3", },
+ { .fw_name = "gp1", },
+};
+
+static T7_COMP_SEL(mipi_isp, MIPI_ISP_CLK_CTRL, 9, 0x7, t7_mipi_isp_parents);
+static T7_COMP_DIV(mipi_isp, MIPI_ISP_CLK_CTRL, 0, 7);
+static T7_COMP_GATE(mipi_isp, MIPI_ISP_CLK_CTRL, 8, 0);
+
+static struct clk_regmap t7_ts_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = TS_CLK_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ts_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_ts = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = TS_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ts",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_ts_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data t7_mali_parents[] = {
+ { .fw_name = "xtal", },
+ { .fw_name = "gp0", },
+ { .fw_name = "gp1", },
+ { .fw_name = "fdiv2p5", },
+ { .fw_name = "fdiv3", },
+ { .fw_name = "fdiv4", },
+ { .fw_name = "fdiv5", },
+ { .fw_name = "fdiv7", },
+};
+
+static T7_COMP_SEL(mali_0, MALI_CLK_CTRL, 9, 0x7, t7_mali_parents);
+static T7_COMP_DIV(mali_0, MALI_CLK_CTRL, 0, 7);
+static T7_COMP_GATE(mali_0, MALI_CLK_CTRL, 8, CLK_SET_RATE_GATE);
+
+static T7_COMP_SEL(mali_1, MALI_CLK_CTRL, 25, 0x7, t7_mali_parents);
+static T7_COMP_DIV(mali_1, MALI_CLK_CTRL, 16, 7);
+static T7_COMP_GATE(mali_1, MALI_CLK_CTRL, 24, CLK_SET_RATE_GATE);
+
+static struct clk_regmap t7_mali = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = MALI_CLK_CTRL,
+ .mask = 1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mali",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mali_0.hw,
+ &t7_mali_1.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/*
+ * parent index 2, 3, 4, 5, 6 not connect any clock signal,
+ * the last parent connect external PAD
+ */
+static u32 t7_eth_rmii_parents_val_table[] = { 0, 1, 7 };
+static const struct clk_parent_data t7_eth_rmii_parents[] = {
+ { .fw_name = "fdiv2", },
+ { .fw_name = "gp1", },
+ { .fw_name = "ext_rmii", },
+};
+
+static struct clk_regmap t7_eth_rmii_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = ETH_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ .table = t7_eth_rmii_parents_val_table,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "eth_rmii_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = t7_eth_rmii_parents,
+ .num_parents = ARRAY_SIZE(t7_eth_rmii_parents),
+ .flags = CLK_SET_RATE_NO_REPARENT,
+ },
+};
+
+static struct clk_regmap t7_eth_rmii_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = ETH_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "eth_rmii_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_eth_rmii_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_eth_rmii = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = ETH_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "eth_rmii",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_eth_rmii_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_fixed_factor t7_fdiv2_div8 = {
+ .mult = 1,
+ .div = 8,
+ .hw.init = &(struct clk_init_data){
+ .name = "fdiv2_div8",
+ .ops = &clk_fixed_factor_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "fdiv2",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_eth_125m = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = ETH_CLK_CTRL,
+ .bit_idx = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "eth_125m",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_fdiv2_div8.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct clk_parent_data t7_sd_emmc_parents[] = {
+ { .fw_name = "xtal", },
+ { .fw_name = "fdiv2", },
+ { .fw_name = "fdiv3", },
+ { .fw_name = "hifi", },
+ { .fw_name = "fdiv2p5", },
+ { .fw_name = "mpll2", },
+ { .fw_name = "mpll3", },
+ { .fw_name = "gp0", },
+};
+
+static T7_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7, t7_sd_emmc_parents);
+static T7_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7);
+static T7_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL, 7, 0);
+
+static T7_COMP_SEL(sd_emmc_b, SD_EMMC_CLK_CTRL, 25, 0x7, t7_sd_emmc_parents);
+static T7_COMP_DIV(sd_emmc_b, SD_EMMC_CLK_CTRL, 16, 7);
+static T7_COMP_GATE(sd_emmc_b, SD_EMMC_CLK_CTRL, 23, 0);
+
+static T7_COMP_SEL(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7, t7_sd_emmc_parents);
+static T7_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7);
+static T7_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7, 0);
+
+static const struct clk_parent_data t7_spicc_parents[] = {
+ { .fw_name = "xtal", },
+ { .fw_name = "sys", },
+ { .fw_name = "fdiv4", },
+ { .fw_name = "fdiv3", },
+ { .fw_name = "fdiv2", },
+ { .fw_name = "fdiv5", },
+ { .fw_name = "fdiv7", },
+ { .fw_name = "gp1", },
+};
+
+static T7_COMP_SEL(spicc0, SPICC_CLK_CTRL, 7, 0x7, t7_spicc_parents);
+static T7_COMP_DIV(spicc0, SPICC_CLK_CTRL, 0, 6);
+static T7_COMP_GATE(spicc0, SPICC_CLK_CTRL, 6, 0);
+
+static T7_COMP_SEL(spicc1, SPICC_CLK_CTRL, 23, 0x7, t7_spicc_parents);
+static T7_COMP_DIV(spicc1, SPICC_CLK_CTRL, 16, 6);
+static T7_COMP_GATE(spicc1, SPICC_CLK_CTRL, 22, 0);
+
+static T7_COMP_SEL(spicc2, SPICC_CLK_CTRL1, 7, 0x7, t7_spicc_parents);
+static T7_COMP_DIV(spicc2, SPICC_CLK_CTRL1, 0, 6);
+static T7_COMP_GATE(spicc2, SPICC_CLK_CTRL1, 6, 0);
+
+static T7_COMP_SEL(spicc3, SPICC_CLK_CTRL1, 23, 0x7, t7_spicc_parents);
+static T7_COMP_DIV(spicc3, SPICC_CLK_CTRL1, 16, 6);
+static T7_COMP_GATE(spicc3, SPICC_CLK_CTRL1, 22, 0);
+
+static T7_COMP_SEL(spicc4, SPICC_CLK_CTRL2, 7, 0x7, t7_spicc_parents);
+static T7_COMP_DIV(spicc4, SPICC_CLK_CTRL2, 0, 6);
+static T7_COMP_GATE(spicc4, SPICC_CLK_CTRL2, 6, 0);
+
+static T7_COMP_SEL(spicc5, SPICC_CLK_CTRL2, 23, 0x7, t7_spicc_parents);
+static T7_COMP_DIV(spicc5, SPICC_CLK_CTRL2, 16, 6);
+static T7_COMP_GATE(spicc5, SPICC_CLK_CTRL2, 22, 0);
+
+static const struct clk_parent_data t7_saradc_parents[] = {
+ { .fw_name = "xtal" },
+ { .fw_name = "sys" },
+};
+
+static T7_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x1, t7_saradc_parents);
+static T7_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8);
+static T7_COMP_GATE(saradc, SAR_CLK_CTRL0, 8, 0);
+
+static const struct clk_parent_data t7_pwm_parents[] = {
+ { .fw_name = "xtal", },
+ { .fw_name = "vid_pll0", },
+ { .fw_name = "fdiv4", },
+ { .fw_name = "fdiv3", },
+};
+
+static T7_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8);
+static T7_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8, 0);
+
+static T7_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8);
+static T7_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24, 0);
+
+static T7_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8);
+static T7_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8, 0);
+
+static T7_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8);
+static T7_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24, 0);
+
+static T7_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8);
+static T7_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8, 0);
+
+static T7_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8);
+static T7_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24, 0);
+
+static T7_COMP_SEL(pwm_ao_a, PWM_CLK_AO_AB_CTRL, 9, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_ao_a, PWM_CLK_AO_AB_CTRL, 0, 8);
+static T7_COMP_GATE(pwm_ao_a, PWM_CLK_AO_AB_CTRL, 8, 0);
+
+static T7_COMP_SEL(pwm_ao_b, PWM_CLK_AO_AB_CTRL, 25, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_ao_b, PWM_CLK_AO_AB_CTRL, 16, 8);
+static T7_COMP_GATE(pwm_ao_b, PWM_CLK_AO_AB_CTRL, 24, 0);
+
+static T7_COMP_SEL(pwm_ao_c, PWM_CLK_AO_CD_CTRL, 9, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_ao_c, PWM_CLK_AO_CD_CTRL, 0, 8);
+static T7_COMP_GATE(pwm_ao_c, PWM_CLK_AO_CD_CTRL, 8, 0);
+
+static T7_COMP_SEL(pwm_ao_d, PWM_CLK_AO_CD_CTRL, 25, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_ao_d, PWM_CLK_AO_CD_CTRL, 16, 8);
+static T7_COMP_GATE(pwm_ao_d, PWM_CLK_AO_CD_CTRL, 24, 0);
+
+static T7_COMP_SEL(pwm_ao_e, PWM_CLK_AO_EF_CTRL, 9, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_ao_e, PWM_CLK_AO_EF_CTRL, 0, 8);
+static T7_COMP_GATE(pwm_ao_e, PWM_CLK_AO_EF_CTRL, 8, 0);
+
+static T7_COMP_SEL(pwm_ao_f, PWM_CLK_AO_EF_CTRL, 25, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_ao_f, PWM_CLK_AO_EF_CTRL, 16, 8);
+static T7_COMP_GATE(pwm_ao_f, PWM_CLK_AO_EF_CTRL, 24, 0);
+
+static T7_COMP_SEL(pwm_ao_g, PWM_CLK_AO_GH_CTRL, 9, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_ao_g, PWM_CLK_AO_GH_CTRL, 0, 8);
+static T7_COMP_GATE(pwm_ao_g, PWM_CLK_AO_GH_CTRL, 8, 0);
+
+static T7_COMP_SEL(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 25, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 16, 8);
+static T7_COMP_GATE(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 24, 0);
+
+static const struct clk_parent_data t7_sys_pclk_parents = { .fw_name = "sys" };
+
+#define T7_SYS_PCLK(_name, _reg, _bit, _flags) \
+ MESON_PCLK(t7_##_name, _reg, _bit, &t7_sys_pclk_parents, _flags)
+
+static T7_SYS_PCLK(sys_ddr, SYS_CLK_EN0_REG0, 0, 0);
+static T7_SYS_PCLK(sys_dos, SYS_CLK_EN0_REG0, 1, 0);
+static T7_SYS_PCLK(sys_mipi_dsi_a, SYS_CLK_EN0_REG0, 2, 0);
+static T7_SYS_PCLK(sys_mipi_dsi_b, SYS_CLK_EN0_REG0, 3, 0);
+static T7_SYS_PCLK(sys_ethphy, SYS_CLK_EN0_REG0, 4, 0);
+static T7_SYS_PCLK(sys_mali, SYS_CLK_EN0_REG0, 6, 0);
+static T7_SYS_PCLK(sys_aocpu, SYS_CLK_EN0_REG0, 13, 0);
+static T7_SYS_PCLK(sys_aucpu, SYS_CLK_EN0_REG0, 14, 0);
+static T7_SYS_PCLK(sys_cec, SYS_CLK_EN0_REG0, 16, 0);
+static T7_SYS_PCLK(sys_gdc, SYS_CLK_EN0_REG0, 17, 0);
+static T7_SYS_PCLK(sys_deswarp, SYS_CLK_EN0_REG0, 18, 0);
+static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, 0);
+static T7_SYS_PCLK(sys_ampipe_eth, SYS_CLK_EN0_REG0, 20, 0);
+static T7_SYS_PCLK(sys_am2axi0, SYS_CLK_EN0_REG0, 21, 0);
+static T7_SYS_PCLK(sys_am2axi1, SYS_CLK_EN0_REG0, 22, 0);
+static T7_SYS_PCLK(sys_am2axi2, SYS_CLK_EN0_REG0, 23, 0);
+static T7_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG0, 24, 0);
+static T7_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG0, 25, 0);
+static T7_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG0, 26, 0);
+static T7_SYS_PCLK(sys_smartcard, SYS_CLK_EN0_REG0, 27, 0);
+static T7_SYS_PCLK(sys_acodec, SYS_CLK_EN0_REG0, 28, 0);
+static T7_SYS_PCLK(sys_spifc, SYS_CLK_EN0_REG0, 29, 0);
+static T7_SYS_PCLK(sys_msr_clk, SYS_CLK_EN0_REG0, 30, 0);
+static T7_SYS_PCLK(sys_ir_ctrl, SYS_CLK_EN0_REG0, 31, 0);
+static T7_SYS_PCLK(sys_audio, SYS_CLK_EN0_REG1, 0, 0);
+static T7_SYS_PCLK(sys_eth, SYS_CLK_EN0_REG1, 3, 0);
+static T7_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 5, 0);
+static T7_SYS_PCLK(sys_uart_b, SYS_CLK_EN0_REG1, 6, 0);
+static T7_SYS_PCLK(sys_uart_c, SYS_CLK_EN0_REG1, 7, 0);
+static T7_SYS_PCLK(sys_uart_d, SYS_CLK_EN0_REG1, 8, 0);
+static T7_SYS_PCLK(sys_uart_e, SYS_CLK_EN0_REG1, 9, 0);
+static T7_SYS_PCLK(sys_uart_f, SYS_CLK_EN0_REG1, 10, 0);
+static T7_SYS_PCLK(sys_aififo, SYS_CLK_EN0_REG1, 11, 0);
+static T7_SYS_PCLK(sys_spicc2, SYS_CLK_EN0_REG1, 12, 0);
+static T7_SYS_PCLK(sys_spicc3, SYS_CLK_EN0_REG1, 13, 0);
+static T7_SYS_PCLK(sys_spicc4, SYS_CLK_EN0_REG1, 14, 0);
+static T7_SYS_PCLK(sys_ts_a73, SYS_CLK_EN0_REG1, 15, 0);
+static T7_SYS_PCLK(sys_ts_a53, SYS_CLK_EN0_REG1, 16, 0);
+static T7_SYS_PCLK(sys_spicc5, SYS_CLK_EN0_REG1, 17, 0);
+static T7_SYS_PCLK(sys_g2d, SYS_CLK_EN0_REG1, 20, 0);
+static T7_SYS_PCLK(sys_spicc0, SYS_CLK_EN0_REG1, 21, 0);
+static T7_SYS_PCLK(sys_spicc1, SYS_CLK_EN0_REG1, 22, 0);
+static T7_SYS_PCLK(sys_pcie, SYS_CLK_EN0_REG1, 24, 0);
+static T7_SYS_PCLK(sys_usb, SYS_CLK_EN0_REG1, 26, 0);
+static T7_SYS_PCLK(sys_pcie_phy, SYS_CLK_EN0_REG1, 27, 0);
+static T7_SYS_PCLK(sys_i2c_ao_a, SYS_CLK_EN0_REG1, 28, 0);
+static T7_SYS_PCLK(sys_i2c_ao_b, SYS_CLK_EN0_REG1, 29, 0);
+static T7_SYS_PCLK(sys_i2c_m_a, SYS_CLK_EN0_REG1, 30, 0);
+static T7_SYS_PCLK(sys_i2c_m_b, SYS_CLK_EN0_REG1, 31, 0);
+static T7_SYS_PCLK(sys_i2c_m_c, SYS_CLK_EN0_REG2, 0, 0);
+static T7_SYS_PCLK(sys_i2c_m_d, SYS_CLK_EN0_REG2, 1, 0);
+static T7_SYS_PCLK(sys_i2c_m_e, SYS_CLK_EN0_REG2, 2, 0);
+static T7_SYS_PCLK(sys_i2c_m_f, SYS_CLK_EN0_REG2, 3, 0);
+static T7_SYS_PCLK(sys_hdmitx_apb, SYS_CLK_EN0_REG2, 4, 0);
+static T7_SYS_PCLK(sys_i2c_s_a, SYS_CLK_EN0_REG2, 5, 0);
+static T7_SYS_PCLK(sys_hdmirx_pclk, SYS_CLK_EN0_REG2, 8, 0);
+static T7_SYS_PCLK(sys_mmc_apb, SYS_CLK_EN0_REG2, 11, 0);
+static T7_SYS_PCLK(sys_mipi_isp_pclk, SYS_CLK_EN0_REG2, 17, 0);
+static T7_SYS_PCLK(sys_rsa, SYS_CLK_EN0_REG2, 18, 0);
+static T7_SYS_PCLK(sys_pclk_sys_apb, SYS_CLK_EN0_REG2, 19, 0);
+static T7_SYS_PCLK(sys_a73pclk_apb, SYS_CLK_EN0_REG2, 20, 0);
+static T7_SYS_PCLK(sys_dspa, SYS_CLK_EN0_REG2, 21, 0);
+static T7_SYS_PCLK(sys_dspb, SYS_CLK_EN0_REG2, 22, 0);
+static T7_SYS_PCLK(sys_vpu_intr, SYS_CLK_EN0_REG2, 25, 0);
+static T7_SYS_PCLK(sys_sar_adc, SYS_CLK_EN0_REG2, 28, 0);
+/*
+ * sys_gic provides the clock for GIC(Generic Interrupt Controller).
+ * After clock is disabled, The GIC cannot work properly. At present, the driver
+ * used by our GIC is the public driver in kernel, and there is no management
+ * clock in the driver.
+ */
+static T7_SYS_PCLK(sys_gic, SYS_CLK_EN0_REG2, 30, CLK_IS_CRITICAL);
+static T7_SYS_PCLK(sys_ts_gpu, SYS_CLK_EN0_REG2, 31, 0);
+static T7_SYS_PCLK(sys_ts_nna, SYS_CLK_EN0_REG3, 0, 0);
+static T7_SYS_PCLK(sys_ts_vpu, SYS_CLK_EN0_REG3, 1, 0);
+static T7_SYS_PCLK(sys_ts_hevc, SYS_CLK_EN0_REG3, 2, 0);
+static T7_SYS_PCLK(sys_pwm_ao_ab, SYS_CLK_EN0_REG3, 3, 0);
+static T7_SYS_PCLK(sys_pwm_ao_cd, SYS_CLK_EN0_REG3, 4, 0);
+static T7_SYS_PCLK(sys_pwm_ao_ef, SYS_CLK_EN0_REG3, 5, 0);
+static T7_SYS_PCLK(sys_pwm_ao_gh, SYS_CLK_EN0_REG3, 6, 0);
+static T7_SYS_PCLK(sys_pwm_ab, SYS_CLK_EN0_REG3, 7, 0);
+static T7_SYS_PCLK(sys_pwm_cd, SYS_CLK_EN0_REG3, 8, 0);
+static T7_SYS_PCLK(sys_pwm_ef, SYS_CLK_EN0_REG3, 9, 0);
+
+/* Array of all clocks registered by this provider */
+static struct clk_hw *t7_peripherals_hw_clks[] = {
+ [CLKID_RTC_DUALDIV_IN] = &t7_rtc_dualdiv_in.hw,
+ [CLKID_RTC_DUALDIV_DIV] = &t7_rtc_dualdiv_div.hw,
+ [CLKID_RTC_DUALDIV_SEL] = &t7_rtc_dualdiv_sel.hw,
+ [CLKID_RTC_DUALDIV] = &t7_rtc_dualdiv.hw,
+ [CLKID_RTC] = &t7_rtc.hw,
+ [CLKID_CECA_DUALDIV_IN] = &t7_ceca_dualdiv_in.hw,
+ [CLKID_CECA_DUALDIV_DIV] = &t7_ceca_dualdiv_div.hw,
+ [CLKID_CECA_DUALDIV_SEL] = &t7_ceca_dualdiv_sel.hw,
+ [CLKID_CECA_DUALDIV] = &t7_ceca_dualdiv.hw,
+ [CLKID_CECA] = &t7_ceca.hw,
+ [CLKID_CECB_DUALDIV_IN] = &t7_cecb_dualdiv_in.hw,
+ [CLKID_CECB_DUALDIV_DIV] = &t7_cecb_dualdiv_div.hw,
+ [CLKID_CECB_DUALDIV_SEL] = &t7_cecb_dualdiv_sel.hw,
+ [CLKID_CECB_DUALDIV] = &t7_cecb_dualdiv.hw,
+ [CLKID_CECB] = &t7_cecb.hw,
+ [CLKID_SC_SEL] = &t7_sc_sel.hw,
+ [CLKID_SC_DIV] = &t7_sc_div.hw,
+ [CLKID_SC] = &t7_sc.hw,
+ [CLKID_DSPA_0_SEL] = &t7_dspa_0_sel.hw,
+ [CLKID_DSPA_0_DIV] = &t7_dspa_0_div.hw,
+ [CLKID_DSPA_0] = &t7_dspa_0.hw,
+ [CLKID_DSPA_1_SEL] = &t7_dspa_1_sel.hw,
+ [CLKID_DSPA_1_DIV] = &t7_dspa_1_div.hw,
+ [CLKID_DSPA_1] = &t7_dspa_1.hw,
+ [CLKID_DSPA] = &t7_dspa.hw,
+ [CLKID_DSPB_0_SEL] = &t7_dspb_0_sel.hw,
+ [CLKID_DSPB_0_DIV] = &t7_dspb_0_div.hw,
+ [CLKID_DSPB_0] = &t7_dspb_0.hw,
+ [CLKID_DSPB_1_SEL] = &t7_dspb_1_sel.hw,
+ [CLKID_DSPB_1_DIV] = &t7_dspb_1_div.hw,
+ [CLKID_DSPB_1] = &t7_dspb_1.hw,
+ [CLKID_DSPB] = &t7_dspb.hw,
+ [CLKID_24M] = &t7_24m.hw,
+ [CLKID_24M_DIV2] = &t7_24m_div2.hw,
+ [CLKID_12M] = &t7_12m.hw,
+ [CLKID_25M_DIV] = &t7_25m_div.hw,
+ [CLKID_25M] = &t7_25m.hw,
+ [CLKID_ANAKIN_0_SEL] = &t7_anakin_0_sel.hw,
+ [CLKID_ANAKIN_0_DIV] = &t7_anakin_0_div.hw,
+ [CLKID_ANAKIN_0] = &t7_anakin_0.hw,
+ [CLKID_ANAKIN_1_SEL] = &t7_anakin_1_sel.hw,
+ [CLKID_ANAKIN_1_DIV] = &t7_anakin_1_div.hw,
+ [CLKID_ANAKIN_1] = &t7_anakin_1.hw,
+ [CLKID_ANAKIN_01_SEL] = &t7_anakin_01_sel.hw,
+ [CLKID_ANAKIN] = &t7_anakin.hw,
+ [CLKID_MIPI_CSI_PHY_0_SEL] = &t7_mipi_csi_phy_0_sel.hw,
+ [CLKID_MIPI_CSI_PHY_0_DIV] = &t7_mipi_csi_phy_0_div.hw,
+ [CLKID_MIPI_CSI_PHY_0] = &t7_mipi_csi_phy_0.hw,
+ [CLKID_MIPI_CSI_PHY_1_SEL] = &t7_mipi_csi_phy_1_sel.hw,
+ [CLKID_MIPI_CSI_PHY_1_DIV] = &t7_mipi_csi_phy_1_div.hw,
+ [CLKID_MIPI_CSI_PHY_1] = &t7_mipi_csi_phy_1.hw,
+ [CLKID_MIPI_CSI_PHY] = &t7_mipi_csi_phy.hw,
+ [CLKID_MIPI_ISP_SEL] = &t7_mipi_isp_sel.hw,
+ [CLKID_MIPI_ISP_DIV] = &t7_mipi_isp_div.hw,
+ [CLKID_MIPI_ISP] = &t7_mipi_isp.hw,
+ [CLKID_TS_DIV] = &t7_ts_div.hw,
+ [CLKID_TS] = &t7_ts.hw,
+ [CLKID_MALI_0_SEL] = &t7_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &t7_mali_0_div.hw,
+ [CLKID_MALI_0] = &t7_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &t7_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &t7_mali_1_div.hw,
+ [CLKID_MALI_1] = &t7_mali_1.hw,
+ [CLKID_MALI] = &t7_mali.hw,
+ [CLKID_ETH_RMII_SEL] = &t7_eth_rmii_sel.hw,
+ [CLKID_ETH_RMII_DIV] = &t7_eth_rmii_div.hw,
+ [CLKID_ETH_RMII] = &t7_eth_rmii.hw,
+ [CLKID_FCLK_DIV2_DIV8] = &t7_fdiv2_div8.hw,
+ [CLKID_ETH_125M] = &t7_eth_125m.hw,
+ [CLKID_SD_EMMC_A_SEL] = &t7_sd_emmc_a_sel.hw,
+ [CLKID_SD_EMMC_A_DIV] = &t7_sd_emmc_a_div.hw,
+ [CLKID_SD_EMMC_A] = &t7_sd_emmc_a.hw,
+ [CLKID_SD_EMMC_B_SEL] = &t7_sd_emmc_b_sel.hw,
+ [CLKID_SD_EMMC_B_DIV] = &t7_sd_emmc_b_div.hw,
+ [CLKID_SD_EMMC_B] = &t7_sd_emmc_b.hw,
+ [CLKID_SD_EMMC_C_SEL] = &t7_sd_emmc_c_sel.hw,
+ [CLKID_SD_EMMC_C_DIV] = &t7_sd_emmc_c_div.hw,
+ [CLKID_SD_EMMC_C] = &t7_sd_emmc_c.hw,
+ [CLKID_SPICC0_SEL] = &t7_spicc0_sel.hw,
+ [CLKID_SPICC0_DIV] = &t7_spicc0_div.hw,
+ [CLKID_SPICC0] = &t7_spicc0.hw,
+ [CLKID_SPICC1_SEL] = &t7_spicc1_sel.hw,
+ [CLKID_SPICC1_DIV] = &t7_spicc1_div.hw,
+ [CLKID_SPICC1] = &t7_spicc1.hw,
+ [CLKID_SPICC2_SEL] = &t7_spicc2_sel.hw,
+ [CLKID_SPICC2_DIV] = &t7_spicc2_div.hw,
+ [CLKID_SPICC2] = &t7_spicc2.hw,
+ [CLKID_SPICC3_SEL] = &t7_spicc3_sel.hw,
+ [CLKID_SPICC3_DIV] = &t7_spicc3_div.hw,
+ [CLKID_SPICC3] = &t7_spicc3.hw,
+ [CLKID_SPICC4_SEL] = &t7_spicc4_sel.hw,
+ [CLKID_SPICC4_DIV] = &t7_spicc4_div.hw,
+ [CLKID_SPICC4] = &t7_spicc4.hw,
+ [CLKID_SPICC5_SEL] = &t7_spicc5_sel.hw,
+ [CLKID_SPICC5_DIV] = &t7_spicc5_div.hw,
+ [CLKID_SPICC5] = &t7_spicc5.hw,
+ [CLKID_SARADC_SEL] = &t7_saradc_sel.hw,
+ [CLKID_SARADC_DIV] = &t7_saradc_div.hw,
+ [CLKID_SARADC] = &t7_saradc.hw,
+ [CLKID_PWM_A_SEL] = &t7_pwm_a_sel.hw,
+ [CLKID_PWM_A_DIV] = &t7_pwm_a_div.hw,
+ [CLKID_PWM_A] = &t7_pwm_a.hw,
+ [CLKID_PWM_B_SEL] = &t7_pwm_b_sel.hw,
+ [CLKID_PWM_B_DIV] = &t7_pwm_b_div.hw,
+ [CLKID_PWM_B] = &t7_pwm_b.hw,
+ [CLKID_PWM_C_SEL] = &t7_pwm_c_sel.hw,
+ [CLKID_PWM_C_DIV] = &t7_pwm_c_div.hw,
+ [CLKID_PWM_C] = &t7_pwm_c.hw,
+ [CLKID_PWM_D_SEL] = &t7_pwm_d_sel.hw,
+ [CLKID_PWM_D_DIV] = &t7_pwm_d_div.hw,
+ [CLKID_PWM_D] = &t7_pwm_d.hw,
+ [CLKID_PWM_E_SEL] = &t7_pwm_e_sel.hw,
+ [CLKID_PWM_E_DIV] = &t7_pwm_e_div.hw,
+ [CLKID_PWM_E] = &t7_pwm_e.hw,
+ [CLKID_PWM_F_SEL] = &t7_pwm_f_sel.hw,
+ [CLKID_PWM_F_DIV] = &t7_pwm_f_div.hw,
+ [CLKID_PWM_F] = &t7_pwm_f.hw,
+ [CLKID_PWM_AO_A_SEL] = &t7_pwm_ao_a_sel.hw,
+ [CLKID_PWM_AO_A_DIV] = &t7_pwm_ao_a_div.hw,
+ [CLKID_PWM_AO_A] = &t7_pwm_ao_a.hw,
+ [CLKID_PWM_AO_B_SEL] = &t7_pwm_ao_b_sel.hw,
+ [CLKID_PWM_AO_B_DIV] = &t7_pwm_ao_b_div.hw,
+ [CLKID_PWM_AO_B] = &t7_pwm_ao_b.hw,
+ [CLKID_PWM_AO_C_SEL] = &t7_pwm_ao_c_sel.hw,
+ [CLKID_PWM_AO_C_DIV] = &t7_pwm_ao_c_div.hw,
+ [CLKID_PWM_AO_C] = &t7_pwm_ao_c.hw,
+ [CLKID_PWM_AO_D_SEL] = &t7_pwm_ao_d_sel.hw,
+ [CLKID_PWM_AO_D_DIV] = &t7_pwm_ao_d_div.hw,
+ [CLKID_PWM_AO_D] = &t7_pwm_ao_d.hw,
+ [CLKID_PWM_AO_E_SEL] = &t7_pwm_ao_e_sel.hw,
+ [CLKID_PWM_AO_E_DIV] = &t7_pwm_ao_e_div.hw,
+ [CLKID_PWM_AO_E] = &t7_pwm_ao_e.hw,
+ [CLKID_PWM_AO_F_SEL] = &t7_pwm_ao_f_sel.hw,
+ [CLKID_PWM_AO_F_DIV] = &t7_pwm_ao_f_div.hw,
+ [CLKID_PWM_AO_F] = &t7_pwm_ao_f.hw,
+ [CLKID_PWM_AO_G_SEL] = &t7_pwm_ao_g_sel.hw,
+ [CLKID_PWM_AO_G_DIV] = &t7_pwm_ao_g_div.hw,
+ [CLKID_PWM_AO_G] = &t7_pwm_ao_g.hw,
+ [CLKID_PWM_AO_H_SEL] = &t7_pwm_ao_h_sel.hw,
+ [CLKID_PWM_AO_H_DIV] = &t7_pwm_ao_h_div.hw,
+ [CLKID_PWM_AO_H] = &t7_pwm_ao_h.hw,
+ [CLKID_SYS_DDR] = &t7_sys_ddr.hw,
+ [CLKID_SYS_DOS] = &t7_sys_dos.hw,
+ [CLKID_SYS_MIPI_DSI_A] = &t7_sys_mipi_dsi_a.hw,
+ [CLKID_SYS_MIPI_DSI_B] = &t7_sys_mipi_dsi_b.hw,
+ [CLKID_SYS_ETHPHY] = &t7_sys_ethphy.hw,
+ [CLKID_SYS_MALI] = &t7_sys_mali.hw,
+ [CLKID_SYS_AOCPU] = &t7_sys_aocpu.hw,
+ [CLKID_SYS_AUCPU] = &t7_sys_aucpu.hw,
+ [CLKID_SYS_CEC] = &t7_sys_cec.hw,
+ [CLKID_SYS_GDC] = &t7_sys_gdc.hw,
+ [CLKID_SYS_DESWARP] = &t7_sys_deswarp.hw,
+ [CLKID_SYS_AMPIPE_NAND] = &t7_sys_ampipe_nand.hw,
+ [CLKID_SYS_AMPIPE_ETH] = &t7_sys_ampipe_eth.hw,
+ [CLKID_SYS_AM2AXI0] = &t7_sys_am2axi0.hw,
+ [CLKID_SYS_AM2AXI1] = &t7_sys_am2axi1.hw,
+ [CLKID_SYS_AM2AXI2] = &t7_sys_am2axi2.hw,
+ [CLKID_SYS_SD_EMMC_A] = &t7_sys_sd_emmc_a.hw,
+ [CLKID_SYS_SD_EMMC_B] = &t7_sys_sd_emmc_b.hw,
+ [CLKID_SYS_SD_EMMC_C] = &t7_sys_sd_emmc_c.hw,
+ [CLKID_SYS_SMARTCARD] = &t7_sys_smartcard.hw,
+ [CLKID_SYS_ACODEC] = &t7_sys_acodec.hw,
+ [CLKID_SYS_SPIFC] = &t7_sys_spifc.hw,
+ [CLKID_SYS_MSR_CLK] = &t7_sys_msr_clk.hw,
+ [CLKID_SYS_IR_CTRL] = &t7_sys_ir_ctrl.hw,
+ [CLKID_SYS_AUDIO] = &t7_sys_audio.hw,
+ [CLKID_SYS_ETH] = &t7_sys_eth.hw,
+ [CLKID_SYS_UART_A] = &t7_sys_uart_a.hw,
+ [CLKID_SYS_UART_B] = &t7_sys_uart_b.hw,
+ [CLKID_SYS_UART_C] = &t7_sys_uart_c.hw,
+ [CLKID_SYS_UART_D] = &t7_sys_uart_d.hw,
+ [CLKID_SYS_UART_E] = &t7_sys_uart_e.hw,
+ [CLKID_SYS_UART_F] = &t7_sys_uart_f.hw,
+ [CLKID_SYS_AIFIFO] = &t7_sys_aififo.hw,
+ [CLKID_SYS_SPICC2] = &t7_sys_spicc2.hw,
+ [CLKID_SYS_SPICC3] = &t7_sys_spicc3.hw,
+ [CLKID_SYS_SPICC4] = &t7_sys_spicc4.hw,
+ [CLKID_SYS_TS_A73] = &t7_sys_ts_a73.hw,
+ [CLKID_SYS_TS_A53] = &t7_sys_ts_a53.hw,
+ [CLKID_SYS_SPICC5] = &t7_sys_spicc5.hw,
+ [CLKID_SYS_G2D] = &t7_sys_g2d.hw,
+ [CLKID_SYS_SPICC0] = &t7_sys_spicc0.hw,
+ [CLKID_SYS_SPICC1] = &t7_sys_spicc1.hw,
+ [CLKID_SYS_PCIE] = &t7_sys_pcie.hw,
+ [CLKID_SYS_USB] = &t7_sys_usb.hw,
+ [CLKID_SYS_PCIE_PHY] = &t7_sys_pcie_phy.hw,
+ [CLKID_SYS_I2C_AO_A] = &t7_sys_i2c_ao_a.hw,
+ [CLKID_SYS_I2C_AO_B] = &t7_sys_i2c_ao_b.hw,
+ [CLKID_SYS_I2C_M_A] = &t7_sys_i2c_m_a.hw,
+ [CLKID_SYS_I2C_M_B] = &t7_sys_i2c_m_b.hw,
+ [CLKID_SYS_I2C_M_C] = &t7_sys_i2c_m_c.hw,
+ [CLKID_SYS_I2C_M_D] = &t7_sys_i2c_m_d.hw,
+ [CLKID_SYS_I2C_M_E] = &t7_sys_i2c_m_e.hw,
+ [CLKID_SYS_I2C_M_F] = &t7_sys_i2c_m_f.hw,
+ [CLKID_SYS_HDMITX_APB] = &t7_sys_hdmitx_apb.hw,
+ [CLKID_SYS_I2C_S_A] = &t7_sys_i2c_s_a.hw,
+ [CLKID_SYS_HDMIRX_PCLK] = &t7_sys_hdmirx_pclk.hw,
+ [CLKID_SYS_MMC_APB] = &t7_sys_mmc_apb.hw,
+ [CLKID_SYS_MIPI_ISP_PCLK] = &t7_sys_mipi_isp_pclk.hw,
+ [CLKID_SYS_RSA] = &t7_sys_rsa.hw,
+ [CLKID_SYS_PCLK_SYS_APB] = &t7_sys_pclk_sys_apb.hw,
+ [CLKID_SYS_A73PCLK_APB] = &t7_sys_a73pclk_apb.hw,
+ [CLKID_SYS_DSPA] = &t7_sys_dspa.hw,
+ [CLKID_SYS_DSPB] = &t7_sys_dspb.hw,
+ [CLKID_SYS_VPU_INTR] = &t7_sys_vpu_intr.hw,
+ [CLKID_SYS_SAR_ADC] = &t7_sys_sar_adc.hw,
+ [CLKID_SYS_GIC] = &t7_sys_gic.hw,
+ [CLKID_SYS_TS_GPU] = &t7_sys_ts_gpu.hw,
+ [CLKID_SYS_TS_NNA] = &t7_sys_ts_nna.hw,
+ [CLKID_SYS_TS_VPU] = &t7_sys_ts_vpu.hw,
+ [CLKID_SYS_TS_HEVC] = &t7_sys_ts_hevc.hw,
+ [CLKID_SYS_PWM_AO_AB] = &t7_sys_pwm_ao_ab.hw,
+ [CLKID_SYS_PWM_AO_CD] = &t7_sys_pwm_ao_cd.hw,
+ [CLKID_SYS_PWM_AO_EF] = &t7_sys_pwm_ao_ef.hw,
+ [CLKID_SYS_PWM_AO_GH] = &t7_sys_pwm_ao_gh.hw,
+ [CLKID_SYS_PWM_AB] = &t7_sys_pwm_ab.hw,
+ [CLKID_SYS_PWM_CD] = &t7_sys_pwm_cd.hw,
+ [CLKID_SYS_PWM_EF] = &t7_sys_pwm_ef.hw,
+};
+
+static const struct meson_clkc_data t7_peripherals_data = {
+ .hw_clks = {
+ .hws = t7_peripherals_hw_clks,
+ .num = ARRAY_SIZE(t7_peripherals_hw_clks),
+ },
+};
+
+static const struct of_device_id t7_peripherals_clkc_match_table[] = {
+ {
+ .compatible = "amlogic,t7-peripherals-clkc",
+ .data = &t7_peripherals_data
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, t7_peripherals_clkc_match_table);
+
+static struct platform_driver t7_peripherals_clkc_driver = {
+ .probe = meson_clkc_mmio_probe,
+ .driver = {
+ .name = "t7-peripherals-clkc",
+ .of_match_table = t7_peripherals_clkc_match_table,
+ },
+};
+module_platform_driver(t7_peripherals_clkc_driver);
+
+MODULE_DESCRIPTION("Amlogic T7 Peripherals Clock Controller driver");
+MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("CLK_MESON");
--
2.47.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v6 4/5] clk: meson: t7: add support for the T7 SoC PLL clock
2025-12-04 5:36 ` [PATCH v6 4/5] clk: meson: t7: add support for the T7 SoC PLL clock Jian Hu
@ 2025-12-06 3:18 ` kernel test robot
0 siblings, 0 replies; 13+ messages in thread
From: kernel test robot @ 2025-12-06 3:18 UTC (permalink / raw)
To: Jian Hu, Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, robh+dt,
Rob Herring
Cc: llvm, oe-kbuild-all, Jian Hu, devicetree, linux-clk,
linux-amlogic, linux-kernel, linux-arm-kernel
Hi Jian,
kernel test robot noticed the following build errors:
[auto build test ERROR on clk/clk-next]
[also build test ERROR on linus/master v6.18 next-20251205]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jian-Hu/dt-bindings-clock-add-Amlogic-T7-PLL-clock-controller/20251204-135351
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
patch link: https://lore.kernel.org/r/20251204053635.1234150-5-jian.hu%40amlogic.com
patch subject: [PATCH v6 4/5] clk: meson: t7: add support for the T7 SoC PLL clock
config: arm64-randconfig-003-20251206 (https://download.01.org/0day-ci/archive/20251206/202512061054.wsIzRCCd-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 14bf95b06a18b9b59c89601cbc0e5a6f2176b118)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251206/202512061054.wsIzRCCd-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512061054.wsIzRCCd-lkp@intel.com/
All errors (new ones prefixed by >>):
>> ld.lld: error: undefined symbol: meson_clk_mpll_ops
>>> referenced by t7-pll.c
>>> drivers/clk/meson/t7-pll.o:(.compoundliteral.51) in archive vmlinux.a
>>> referenced by t7-pll.c
>>> drivers/clk/meson/t7-pll.o:(.compoundliteral.59) in archive vmlinux.a
>>> referenced by t7-pll.c
>>> drivers/clk/meson/t7-pll.o:(.compoundliteral.67) in archive vmlinux.a
>>> referenced 1 more times
>>> did you mean: meson_clk_pll_ops
>>> defined in: vmlinux.a(drivers/clk/meson/clk-pll.o)
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 2/5] dt-bindings: clock: add Amlogic T7 SCMI clock controller
2025-12-04 5:36 ` [PATCH v6 2/5] dt-bindings: clock: add Amlogic T7 SCMI " Jian Hu
@ 2025-12-08 6:17 ` Krzysztof Kozlowski
2025-12-08 8:40 ` Jian Hu
0 siblings, 1 reply; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-12-08 6:17 UTC (permalink / raw)
To: Jian Hu
Cc: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, robh+dt,
Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
On Thu, Dec 04, 2025 at 01:36:31PM +0800, Jian Hu wrote:
> Add DT bindings for the SCMI clock controller of the Amlogic T7 SoC family.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> ---
> include/dt-bindings/clock/amlogic,t7-scmi.h | 47 +++++++++++++++++++++
> 1 file changed, 47 insertions(+)
> create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h
>
Where is any binding doc for this? Why is this a separate patch?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 2/5] dt-bindings: clock: add Amlogic T7 SCMI clock controller
2025-12-08 6:17 ` Krzysztof Kozlowski
@ 2025-12-08 8:40 ` Jian Hu
2025-12-09 6:01 ` Krzysztof Kozlowski
0 siblings, 1 reply; 13+ messages in thread
From: Jian Hu @ 2025-12-08 8:40 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, robh+dt,
Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
Hi, Krzysztof
Thans for your review.
On 12/8/2025 2:17 PM, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On Thu, Dec 04, 2025 at 01:36:31PM +0800, Jian Hu wrote:
>> Add DT bindings for the SCMI clock controller of the Amlogic T7 SoC family.
>>
>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>> Acked-by: Rob Herring (Arm) <robh@kernel.org>
>> ---
>> include/dt-bindings/clock/amlogic,t7-scmi.h | 47 +++++++++++++++++++++
>> 1 file changed, 47 insertions(+)
>> create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h
>>
> Where is any binding doc for this? Why is this a separate patch?
The ARM SCMI device tree binding specification is located at
./Documentation/devicetree/bindings/firmware/arm,scmi.yaml.
Certain secure clocks on the T7 rely on the ARM SCMI driver stack, which
is officially supported by ARM.
The kernel-side SCMI client implementation resides in
./drivers/firmware/arm_scmi/.
To enable ARM SCMI on T7, three components are needed:
- Kernel-side definition of ARM SCMI clock indices (this patch addresses
this component);
- SCMI server implementation in the ARM Trusted Firmware (ATF) running
at Exception Level 3 (EL3), which has been integrated into the bootloader;
- Device Tree Source (DTS) configuration for ARM SCMI clock nodes (the
DTS changes will be submitted after the T7 clock driver patches are
merged upstream).
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 2/5] dt-bindings: clock: add Amlogic T7 SCMI clock controller
2025-12-08 8:40 ` Jian Hu
@ 2025-12-09 6:01 ` Krzysztof Kozlowski
2025-12-09 10:16 ` Jerome Brunet
0 siblings, 1 reply; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-12-09 6:01 UTC (permalink / raw)
To: Jian Hu
Cc: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, robh+dt,
Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
On 08/12/2025 09:40, Jian Hu wrote:
> Hi, Krzysztof
>
>
> Thans for your review.
>
> On 12/8/2025 2:17 PM, Krzysztof Kozlowski wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On Thu, Dec 04, 2025 at 01:36:31PM +0800, Jian Hu wrote:
>>> Add DT bindings for the SCMI clock controller of the Amlogic T7 SoC family.
>>>
>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>>> Acked-by: Rob Herring (Arm) <robh@kernel.org>
>>> ---
>>> include/dt-bindings/clock/amlogic,t7-scmi.h | 47 +++++++++++++++++++++
>>> 1 file changed, 47 insertions(+)
>>> create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h
>>>
>> Where is any binding doc for this? Why is this a separate patch?
>
>
> The ARM SCMI device tree binding specification is located at
> ./Documentation/devicetree/bindings/firmware/arm,scmi.yaml.
Then git grep for the file name - there is no such compatible. Are you
sure you follow writing bindings doc?
Think how are you going to use these values. You will have phandle, yes?
To some controller, yes? Which one?
>
> Certain secure clocks on the T7 rely on the ARM SCMI driver stack, which
> is officially supported by ARM.
>
> The kernel-side SCMI client implementation resides in
> ./drivers/firmware/arm_scmi/.
>
> To enable ARM SCMI on T7, three components are needed:
>
> - Kernel-side definition of ARM SCMI clock indices (this patch addresses
> this component);
> - SCMI server implementation in the ARM Trusted Firmware (ATF) running
> at Exception Level 3 (EL3), which has been integrated into the bootloader;
> - Device Tree Source (DTS) configuration for ARM SCMI clock nodes (the
> DTS changes will be submitted after the T7 clock driver patches are
> merged upstream).
So silently you keep the users hidden? No, I want to see the users.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 2/5] dt-bindings: clock: add Amlogic T7 SCMI clock controller
2025-12-09 6:01 ` Krzysztof Kozlowski
@ 2025-12-09 10:16 ` Jerome Brunet
2025-12-11 6:16 ` Krzysztof Kozlowski
0 siblings, 1 reply; 13+ messages in thread
From: Jerome Brunet @ 2025-12-09 10:16 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Jian Hu, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman,
Stephen Boyd, Michael Turquette, robh+dt, Rob Herring, devicetree,
linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel
On Tue 09 Dec 2025 at 07:01, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On 08/12/2025 09:40, Jian Hu wrote:
>> Hi, Krzysztof
>>
>>
>> Thans for your review.
>>
>> On 12/8/2025 2:17 PM, Krzysztof Kozlowski wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On Thu, Dec 04, 2025 at 01:36:31PM +0800, Jian Hu wrote:
>>>> Add DT bindings for the SCMI clock controller of the Amlogic T7 SoC family.
>>>>
>>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>>>> Acked-by: Rob Herring (Arm) <robh@kernel.org>
>>>> ---
>>>> include/dt-bindings/clock/amlogic,t7-scmi.h | 47 +++++++++++++++++++++
>>>> 1 file changed, 47 insertions(+)
>>>> create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h
>>>>
>>> Where is any binding doc for this? Why is this a separate patch?
>>
>>
>> The ARM SCMI device tree binding specification is located at
>> ./Documentation/devicetree/bindings/firmware/arm,scmi.yaml.
>
> Then git grep for the file name - there is no such compatible. Are you
> sure you follow writing bindings doc?
>
> Think how are you going to use these values. You will have phandle, yes?
> To some controller, yes? Which one?
For the C3 (I believe the T7 is the same), the compatible being used is
"arm,scmi-smc". It is a generic one documented here:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/firmware/arm,scmi.yaml?h=v6.18#n202
The phandle used is a subnode of that, to clock protocol:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi?h=v6.18#n116
Same things is done on imx, stm and rockchip platforms from what I can
see.
Jian is just adding the arbitrary IDs used to identify the clocks in the
FW. I don't think there is anything out of the ordirnary here.
Is there something else Rob and I missed reviewing this ?
>
>>
>> Certain secure clocks on the T7 rely on the ARM SCMI driver stack, which
>> is officially supported by ARM.
>>
>> The kernel-side SCMI client implementation resides in
>> ./drivers/firmware/arm_scmi/.
>>
>> To enable ARM SCMI on T7, three components are needed:
>>
>> - Kernel-side definition of ARM SCMI clock indices (this patch addresses
>> this component);
>> - SCMI server implementation in the ARM Trusted Firmware (ATF) running
>> at Exception Level 3 (EL3), which has been integrated into the bootloader;
>> - Device Tree Source (DTS) configuration for ARM SCMI clock nodes (the
>> DTS changes will be submitted after the T7 clock driver patches are
>> merged upstream).
>
> So silently you keep the users hidden? No, I want to see the users.
>
Is there a new requirement to submit the DTS file changes along with the
driver changes now ?
This has never been case before, especially since the changes are merged
through different trees.
>
> Best regards,
> Krzysztof
--
Jerome
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 2/5] dt-bindings: clock: add Amlogic T7 SCMI clock controller
2025-12-09 10:16 ` Jerome Brunet
@ 2025-12-11 6:16 ` Krzysztof Kozlowski
2025-12-11 8:30 ` Jerome Brunet
0 siblings, 1 reply; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-12-11 6:16 UTC (permalink / raw)
To: Jerome Brunet
Cc: Jian Hu, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman,
Stephen Boyd, Michael Turquette, robh+dt, Rob Herring, devicetree,
linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel
On 09/12/2025 11:16, Jerome Brunet wrote:
> On Tue 09 Dec 2025 at 07:01, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
>> On 08/12/2025 09:40, Jian Hu wrote:
>>> Hi, Krzysztof
>>>
>>>
>>> Thans for your review.
>>>
>>> On 12/8/2025 2:17 PM, Krzysztof Kozlowski wrote:
>>>> [ EXTERNAL EMAIL ]
>>>>
>>>> On Thu, Dec 04, 2025 at 01:36:31PM +0800, Jian Hu wrote:
>>>>> Add DT bindings for the SCMI clock controller of the Amlogic T7 SoC family.
>>>>>
>>>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>>>>> Acked-by: Rob Herring (Arm) <robh@kernel.org>
>>>>> ---
>>>>> include/dt-bindings/clock/amlogic,t7-scmi.h | 47 +++++++++++++++++++++
>>>>> 1 file changed, 47 insertions(+)
>>>>> create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h
>>>>>
>>>> Where is any binding doc for this? Why is this a separate patch?
>>>
>>>
>>> The ARM SCMI device tree binding specification is located at
>>> ./Documentation/devicetree/bindings/firmware/arm,scmi.yaml.
>>
>> Then git grep for the file name - there is no such compatible. Are you
>> sure you follow writing bindings doc?
>>
>> Think how are you going to use these values. You will have phandle, yes?
>> To some controller, yes? Which one?
>
> For the C3 (I believe the T7 is the same), the compatible being used is
> "arm,scmi-smc". It is a generic one documented here:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/firmware/arm,scmi.yaml?h=v6.18#n202
>
> The phandle used is a subnode of that, to clock protocol:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi?h=v6.18#n116
>
> Same things is done on imx, stm and rockchip platforms from what I can
> see.
I see, thanks for explanation, it's fine.
>
> Jian is just adding the arbitrary IDs used to identify the clocks in the
> FW. I don't think there is anything out of the ordirnary here.
>
> Is there something else Rob and I missed reviewing this ?
>
>>
>>>
>>> Certain secure clocks on the T7 rely on the ARM SCMI driver stack, which
>>> is officially supported by ARM.
>>>
>>> The kernel-side SCMI client implementation resides in
>>> ./drivers/firmware/arm_scmi/.
>>>
>>> To enable ARM SCMI on T7, three components are needed:
>>>
>>> - Kernel-side definition of ARM SCMI clock indices (this patch addresses
>>> this component);
>>> - SCMI server implementation in the ARM Trusted Firmware (ATF) running
>>> at Exception Level 3 (EL3), which has been integrated into the bootloader;
>>> - Device Tree Source (DTS) configuration for ARM SCMI clock nodes (the
>>> DTS changes will be submitted after the T7 clock driver patches are
>>> merged upstream).
>>
>> So silently you keep the users hidden? No, I want to see the users.
>>
>
> Is there a new requirement to submit the DTS file changes along with the
> driver changes now ?
>
> This has never been case before, especially since the changes are merged
> through different trees.
There is no such requirement, but "has never been case before" is
clearly not accurate, because I raised this question multiple times last
two-three years.
There is no reasonable way to hold publishing of DTS, therefore if
someone uses arguments like above with waiting for driver, I usually got
suspicious.
Also note, that many contributions from various people (not saying that
this one here is) were bad quality and badly designed but without seeing
DTS it takes me significantly more time to understand that design. So
yes, publish your DTS solving all of the questions and making reviewing
easier. Or don't and receive questions...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 2/5] dt-bindings: clock: add Amlogic T7 SCMI clock controller
2025-12-11 6:16 ` Krzysztof Kozlowski
@ 2025-12-11 8:30 ` Jerome Brunet
0 siblings, 0 replies; 13+ messages in thread
From: Jerome Brunet @ 2025-12-11 8:30 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Jian Hu, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman,
Stephen Boyd, Michael Turquette, robh+dt, Rob Herring, devicetree,
linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel
On Thu 11 Dec 2025 at 07:16, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>> Is there a new requirement to submit the DTS file changes along with the
>> driver changes now ?
>>
>> This has never been case before, especially since the changes are merged
>> through different trees.
>
> There is no such requirement, but "has never been case before" is
> clearly not accurate, because I raised this question multiple times last
> two-three years.
>
> There is no reasonable way to hold publishing of DTS, therefore if
> someone uses arguments like above with waiting for driver, I usually got
> suspicious.
>
> Also note, that many contributions from various people (not saying that
> this one here is) were bad quality and badly designed but without seeing
> DTS it takes me significantly more time to understand that design. So
> yes, publish your DTS solving all of the questions and making reviewing
> easier. Or don't and receive questions...
>
That's fair. Thanks for clarifying.
>
> Best regards,
> Krzysztof
--
Jerome
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2025-12-11 8:30 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-12-04 5:36 [PATCH v6 0/5] add support for T7 family clock controller Jian Hu
2025-12-04 5:36 ` [PATCH v6 1/5] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu
2025-12-04 5:36 ` [PATCH v6 2/5] dt-bindings: clock: add Amlogic T7 SCMI " Jian Hu
2025-12-08 6:17 ` Krzysztof Kozlowski
2025-12-08 8:40 ` Jian Hu
2025-12-09 6:01 ` Krzysztof Kozlowski
2025-12-09 10:16 ` Jerome Brunet
2025-12-11 6:16 ` Krzysztof Kozlowski
2025-12-11 8:30 ` Jerome Brunet
2025-12-04 5:36 ` [PATCH v6 3/5] dt-bindings: clock: add Amlogic T7 peripherals " Jian Hu
2025-12-04 5:36 ` [PATCH v6 4/5] clk: meson: t7: add support for the T7 SoC PLL clock Jian Hu
2025-12-06 3:18 ` kernel test robot
2025-12-04 5:36 ` [PATCH v6 5/5] clk: meson: t7: add t7 clock peripherals controller driver Jian Hu
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