From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4E628362094; Tue, 9 Sep 2025 16:58:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757437085; cv=none; b=E2wiTEeMqhFATtAUqLko/tek61F1IsZ/Sjeq9KkA2uTb52x80PJf2c+rOnAZbWAtSvR7HWY+mbfGiGougt2r2eJT56tIZpmUrM7kTb1KJbhC7QBVb/AQmmA6sJfP80VxWWK8zK2XyPrQcwRnsyCyU3S/MXx6IgpNx4gvocoobNY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757437085; c=relaxed/simple; bh=GpQo9QmEwcAmI5NcO84HjLc0BalR2RhF0SbpzI+C67M=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=t1vR89ol0a8GBbS2KmbTRQ8v+Jj8wX7HZ4vmU7uVf4VY77kZq3zxgeCkvYGiNjmHFZjsc+Qso4tGRhx4fLf+qq8HafmAi4As6sgDBUds4SZ2iQcrch8meFMSfCsad8isu+XikMan8G0xL+P2iNMmPU9/A9RM+zWL1ONry9R+2Aw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4775320E3; Tue, 9 Sep 2025 09:57:55 -0700 (PDT) Received: from [10.1.197.69] (eglon.cambridge.arm.com [10.1.197.69]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BD3323F694; Tue, 9 Sep 2025 09:57:57 -0700 (PDT) Message-ID: Date: Tue, 9 Sep 2025 17:57:57 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 20/33] arm_mpam: Add a helper to touch an MSC from any CPU To: Ben Horgan , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, devicetree@vger.kernel.org Cc: shameerali.kolothum.thodi@huawei.com, D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Rex Nie , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich References: <20250822153048.2287-1-james.morse@arm.com> <20250822153048.2287-21-james.morse@arm.com> <8635e616-79b7-4d7d-a8b8-aa76ba027bc4@arm.com> Content-Language: en-GB From: James Morse In-Reply-To: <8635e616-79b7-4d7d-a8b8-aa76ba027bc4@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Ben, On 28/08/2025 17:13, Ben Horgan wrote: > On 8/22/25 16:30, James Morse wrote: >> Resetting RIS entries from the cpuhp callback is easy as the >> callback occurs on the correct CPU. This won't be true for any other >> caller that wants to reset or configure an MSC. >> >> Add a helper that schedules the provided function if necessary. >> Prevent the cpuhp callbacks from changing the MSC state by taking the >> cpuhp lock. > At first, I thought this was referring to something done in the patch. > Consider changing to something like: > > Callers should take the cpuhp lock to prevent the cpuhp callbacks from > changing the MSC state. Yes - that is better, > Regardless, this looks good to me. > > Reviewed-by: Ben Horgan Thanks! James