From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCF58C77B60 for ; Mon, 3 Apr 2023 09:11:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231585AbjDCJLC (ORCPT ); Mon, 3 Apr 2023 05:11:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231285AbjDCJLC (ORCPT ); Mon, 3 Apr 2023 05:11:02 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EDEA97692 for ; Mon, 3 Apr 2023 02:10:59 -0700 (PDT) Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33392php004488; Mon, 3 Apr 2023 11:10:49 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=selector1; bh=E6EGVKst8D+0Gk/EJvcw0vEtNpKhnEpfCWUrxagkj3I=; b=tjcYCKEyQqCHeAviFBthWAZgf9+bXppYmgj72WgkOFd0YjTUlb3kZeQCvMmhkcZW1kA8 me2zsaCDOFVezcIUZXp3Yjjt4c9cFn4BL78x44ixwy8VqP2X5RHF8PyTGDKTlQp/Eq2x Er41s1RxEfz1Tu7sBH6cJp5R8WKxBRlnkdI9vv91rxHR21PiqJkewPhETPBY3R3wTmpk rpFLgbASbSuyu7rjsD0REjemfZg+0pY5oDQidz5/7rNRkRDE/t9KYMq/yMeV3j6tvJhn lbowmA85pvRDwESdV2eX0uFXyfUalP/cZsUM5iuV8f7wE5akkVx7RkJFMscJMnxHpvQT Yg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ppa1m9d13-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 03 Apr 2023 11:10:49 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0854E10002A; Mon, 3 Apr 2023 11:10:49 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id F37332138D9; Mon, 3 Apr 2023 11:10:48 +0200 (CEST) Received: from [10.201.21.93] (10.201.21.93) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.17; Mon, 3 Apr 2023 11:10:48 +0200 Message-ID: Date: Mon, 3 Apr 2023 11:10:47 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v7 09/10] ARM: dts: stm32: add STM32MP1-based Phytec SoM Content-Language: en-US To: Steffen Trumtrar , CC: Krzysztof Kozlowski , Maxime Coquelin , , References: <20230330050408.3806093-1-s.trumtrar@pengutronix.de> <20230330050408.3806093-10-s.trumtrar@pengutronix.de> From: Alexandre TORGUE In-Reply-To: <20230330050408.3806093-10-s.trumtrar@pengutronix.de> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.201.21.93] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-03_06,2023-03-31_01,2023-02-09_01 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Steffen On 3/30/23 07:04, Steffen Trumtrar wrote: > The Phytec STM32MP1 based SoMs feature up to 1 GB DDR3LP RAM, up to 1 GB > eMMC, up to 16 MB QSPI and up to 128 GB NAND flash. > > Signed-off-by: Steffen Trumtrar > --- I'm not so far to merge your series but I still have questions. > Notes: > checkpatch warns about un-documented binding > > According to checkpatch the binding for "winbond,w25q128" > used in this dtsi is un-documented. > However, 'jedec,spi-nor.yaml' defines the pattern > > (winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$" > > so, this should be good!? > > Changes since v6: > - rename mdio0->mdio > > Changes since v5: > - cleanup dt_bindings_check warnings > > Changes since v4: > - cleanup usage of "status = okay|disabled" > - fix remaining non-generic node names > - rework sai nodes to not duplicate the existing settings in stm32mp151.dtsi > > Changes since v3: > - cleanup board-compatible > - cleanup aliases > - rename nodes according to schema > - use interrupt flag > > .../stm32mp157c-phycore-stm32mp15-som.dtsi | 594 ++++++++++++++++++ > 1 file changed, 594 insertions(+) > create mode 100644 arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi > > diff --git a/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi b/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi > new file mode 100644 > index 0000000000000..f612daa4c66a7 > --- /dev/null > +++ b/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi > @@ -0,0 +1,594 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) > +/* > + * Copyright (C) 2022-2023 Steffen Trumtrar > + * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved > + * Author: Dom VOVARD . > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "stm32mp15-pinctrl.dtsi" > + > +/ { > + model = "PHYTEC phyCORE-STM32MP15 SOM"; > + compatible = "phytec,phycore-stm32mp157c-som", "st,stm32mp157"; > + > + aliases { > + ethernet0 = ðernet0; > + rtc0 = &i2c4_rtc; > + rtc1 = &rtc; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + gpio-keys { > + compatible = "gpio-keys"; > + > + key-home { > + label = "Home"; > + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; > + linux,code = ; > + }; > + > + key-enter { > + label = "Enter"; > + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; > + linux,code = ; > + }; > + }; > + > + reserved-memory { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + retram: retram@38000000 { > + compatible = "shared-dma-pool"; > + reg = <0x38000000 0x10000>; > + no-map; > + }; > + > + mcuram: mcuram@30000000 { > + compatible = "shared-dma-pool"; > + reg = <0x30000000 0x40000>; > + no-map; > + }; > + > + mcuram2: mcuram2@10000000 { > + compatible = "shared-dma-pool"; > + reg = <0x10000000 0x40000>; > + no-map; > + }; > + > + vdev0vring0: vdev0vring0@10040000 { > + compatible = "shared-dma-pool"; > + reg = <0x10040000 0x1000>; > + no-map; > + }; > + > + vdev0vring1: vdev0vring1@10041000 { > + compatible = "shared-dma-pool"; > + reg = <0x10041000 0x1000>; > + no-map; > + }; > + > + vdev0buffer: vdev0buffer@10042000 { > + compatible = "shared-dma-pool"; > + reg = <0x10042000 0x4000>; > + no-map; > + }; > + > + gpu_reserved: gpu@f8000000 { > + reg = <0xf8000000 0x8000000>; > + no-map; > + }; It seems that this region is not used. Furthermore if you plan to use it to GPU note that it doesn't respect YAMl verification. So please remove it. > + }; > + > + sound { > + compatible = "audio-graph-card"; > + label = "STM32MP1-PHYCORE"; > + routing = > + "Playback", "MCLK", /* Set a route between "MCLK" and "playback" widgets */ > + "Capture", "MCLK"; > + dais = <&sai2b_port>, > + <&sai2a_port>; > + }; > + > + regulator_vin: regulator { > + compatible = "regulator-fixed"; > + regulator-name = "vin"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-always-on; > + }; > +}; > + > +ðernet0 { > + pinctrl-0 = <ðernet0_rgmii_pins_d>; > + pinctrl-1 = <ðernet0_rgmii_sleep_pins_d>; > + pinctrl-names = "default", "sleep"; > + phy-mode = "rgmii-id"; > + max-speed = <1000>; > + phy-handle = <&phy0>; > + st,eth-clk-sel; > + clock-names = "stmmaceth", > + "mac-clk-tx", > + "mac-clk-rx", > + "eth-ck", > + "syscfg-clk", > + "ethstp"; > + clocks = <&rcc ETHMAC>, > + <&rcc ETHTX>, > + <&rcc ETHRX>, > + <&rcc ETHCK_K>, > + <&rcc SYSCFG>, > + <&rcc ETHSTP>; Why do you re define those clocks ? They are all already defined in stm32mp151.dtsi > + status = "okay"; > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dwmac-mdio"; > + > + phy0: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + interrupt-parent = <&gpiog>; > + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; > + ti,rx-internal-delay = ; > + ti,tx-internal-delay = ; > + ti,fifo-depth = ; > + ti,min-output-impedance; > + enet-phy-lane-no-swap; > + ti,clk-output-sel = ; > + }; > + }; > +}; > + ...