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[83.9.3.225]) by smtp.gmail.com with ESMTPSA id c1-20020a2e6801000000b002a421ac8629sm1678069lja.49.2023.03.28.06.30.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Mar 2023 06:30:52 -0700 (PDT) Message-ID: Date: Tue, 28 Mar 2023 15:30:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v4 5/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP Content-Language: en-US To: Rohit Agarwal , agross@kernel.org, andersson@kernel.org, lee@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <1679036039-27157-1-git-send-email-quic_rohiagar@quicinc.com> <1679036039-27157-6-git-send-email-quic_rohiagar@quicinc.com> From: Konrad Dybcio In-Reply-To: <1679036039-27157-6-git-send-email-quic_rohiagar@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 17.03.2023 07:53, Rohit Agarwal wrote: > Enable PCIe Endpoint controller on the SDX65 MTP board based > on Qualcomm SDX65 platform. > > Signed-off-by: Rohit Agarwal > --- > arch/arm/boot/dts/qcom-sdx65-mtp.dts | 34 ++++++++++++++++++++++++++++++++++ > 1 file changed, 34 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts > index 70720e6..afe970a 100644 > --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts > +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts > @@ -245,6 +245,17 @@ > status = "okay"; > }; > > +&pcie_ep { > + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default > + &pcie_ep_wake_default>; This seems misaligned, the &s should be one below another But other than that: Reviewed-by: Konrad Dybcio Konrad > + pinctrl-names = "default"; > + > + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; > + > + status = "okay"; > +}; > + > &pcie_phy { > vdda-phy-supply = <&vreg_l1b_1p2>; > vdda-pll-supply = <&vreg_l4b_0p88>; > @@ -277,6 +288,29 @@ > status = "okay"; > }; > > +&tlmm { > + pcie_ep_clkreq_default: pcie-ep-clkreq-default-state { > + pins = "gpio56"; > + function = "pcie_clkreq"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + pcie_ep_perst_default: pcie-ep-perst-default-state { > + pins = "gpio57"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + pcie_ep_wake_default: pcie-ep-wake-default-state { > + pins = "gpio53"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + }; > +}; > + > &usb { > status = "okay"; > };