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Wed, 12 Feb 2025 15:04:40 -0800 (PST) Message-ID: Subject: Re: [PATCH v3 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files From: Alexander Sverdlin To: Inochi Amaoto , soc@lists.linux.dev Cc: Chen Wang , Inochi Amaoto , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Arnd Bergmann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Chao Wei Date: Thu, 13 Feb 2025 00:04:39 +0100 In-Reply-To: References: <20250212224347.1767819-1-alexander.sverdlin@gmail.com> <20250212224347.1767819-2-alexander.sverdlin@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.2 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Inochi! On Thu, 2025-02-13 at 06:54 +0800, Inochi Amaoto wrote: > On Wed, Feb 12, 2025 at 11:43:33PM +0100, Alexander Sverdlin wrote: > > Make the peripheral device tree re-usable on ARM64 platform by moving C= PU > > core and interrupt controllers' parts into new cv18xx-cpu.dtsi and > > cv18xx-intc.dtsi. > >=20 > > Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nuberin= g > > into "plic" interrupt-controller numbering. > >=20 > > On RiscV side this patch has been dtc-compile-tested only. IRQ numbers > > substitution with SOC_PERIPHERAL_IRQ() has been scripted in vim. > >=20 > > Signed-off-by: Alexander Sverdlin > > --- > > Changelog: > > v3: > > - &cpus node has been moved into cv18xx-cpu.dtsi, &plic and &clint node= s > > were moved into cv18xx-intc.dtsi to reduce code duplication; > > v2: > > - instead of carving out peripherals' part, carve out ARCH-specifics (C= PU > > core, interrupt controllers) and spread them among 3 SoC .dtsi files wh= ich > > included cv18xx.dtsi; > > - define a label for the "soc" node and use it in the newly introduced = DTs; > >=20 > > =C2=A0 arch/riscv/boot/dts/sophgo/cv1800b.dtsi=C2=A0=C2=A0=C2=A0=C2=A0 = | 28 ++++--- > > =C2=A0 arch/riscv/boot/dts/sophgo/cv1812h.dtsi=C2=A0=C2=A0=C2=A0=C2=A0 = | 28 ++++--- > > =C2=A0 arch/riscv/boot/dts/sophgo/cv181x.dtsi=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 |=C2=A0 2 +- > > =C2=A0 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi=C2=A0 | 36 ++++++++ > > =C2=A0 arch/riscv/boot/dts/sophgo/cv18xx-intc.dtsi | 23 ++++++ > > =C2=A0 arch/riscv/boot/dts/sophgo/cv18xx.dtsi=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 | 91 ++++++--------------- > > =C2=A0 arch/riscv/boot/dts/sophgo/sg2002.dtsi=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 | 34 ++++---- > > =C2=A0 7 files changed, 137 insertions(+), 105 deletions(-) > > =C2=A0 create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi > > =C2=A0 create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-intc.dtsi > >=20 > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/= dts/sophgo/cv1800b.dtsi > > index aa1f5df100f0..9fb7dd2dab18 100644 > > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > @@ -3,8 +3,12 @@ > > =C2=A0=C2=A0 * Copyright (C) 2023 Jisheng Zhang > > =C2=A0=C2=A0 */ > > =C2=A0=20 > > +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) > > + > > =C2=A0 #include > > +#include "cv18xx-cpu.dtsi" > > =C2=A0 #include "cv18xx.dtsi" > > +#include "cv18xx-intc.dtsi" > > =C2=A0=20 > > =C2=A0 / { > > =C2=A0=C2=A0 compatible =3D "sophgo,cv1800b"; > > @@ -13,17 +17,23 @@ memory@80000000 { > > =C2=A0=C2=A0 device_type =3D "memory"; > > =C2=A0=C2=A0 reg =3D <0x80000000 0x4000000>; > > =C2=A0=C2=A0 }; > > +}; > > + >=20 > > +&soc { > > + dma-noncoherent; > > =C2=A0=20 > > - soc { > > - pinctrl: pinctrl@3001000 { > > - compatible =3D "sophgo,cv1800b-pinctrl"; > > - reg =3D <0x03001000 0x1000>, > > - =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0x05027000 0x1000>; > > - reg-names =3D "sys", "rtc"; > > - }; > > + pinctrl: pinctrl@3001000 { > > + compatible =3D "sophgo,cv1800b-pinctrl"; > > + reg =3D <0x03001000 0x1000>, > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0x05027000 0x1000>; > > + reg-names =3D "sys", "rtc"; > > =C2=A0=C2=A0 }; > > =C2=A0 }; > > =C2=A0=20 >=20 > The origianl /soc path can be used to override things,=20 > why change it to the reference archor? I see no change > for it. https://lore.kernel.org/soc/d3ba0ea5-0491-42d5-a18e-64cf21df696c@kernel.org= / The corresponding label is being introduced in cv18xx.dtsi. > > +&clk { > > + compatible =3D "sophgo,cv1800-clk"; > > +}; > > + > > =C2=A0 &plic { > > =C2=A0=C2=A0 compatible =3D "sophgo,cv1800b-plic", "thead,c900-plic"; > > =C2=A0 }; > > @@ -31,7 +41,3 @@ &plic { > > =C2=A0 &clint { > > =C2=A0=C2=A0 compatible =3D "sophgo,cv1800b-clint", "thead,c900-clint"; > > =C2=A0 }; > > - > > -&clk { > > - compatible =3D "sophgo,cv1800-clk"; > > -}; > > diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/= dts/sophgo/cv1812h.dtsi > > index 8a1b95c5116b..f23c4dd6687d 100644 > > --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > > +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > > @@ -3,10 +3,14 @@ > > =C2=A0=C2=A0 * Copyright (C) 2023 Inochi Amaoto > > =C2=A0=C2=A0 */ > > =C2=A0=20 > > +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) > > + > > =C2=A0 #include > > =C2=A0 #include > > +#include "cv18xx-cpu.dtsi" > > =C2=A0 #include "cv18xx.dtsi" > > =C2=A0 #include "cv181x.dtsi" > > +#include "cv18xx-intc.dtsi" > > =C2=A0=20 > > =C2=A0 / { > > =C2=A0=C2=A0 compatible =3D "sophgo,cv1812h"; > > @@ -15,17 +19,23 @@ memory@80000000 { > > =C2=A0=C2=A0 device_type =3D "memory"; > > =C2=A0=C2=A0 reg =3D <0x80000000 0x10000000>; > > =C2=A0=C2=A0 }; > > +}; > > + > > +&soc { >=20 > > + dma-noncoherent; >=20 > I think this can be moved into cv18xx-cpu.dtsi file, and let > all SoCs share it. https://lore.kernel.org/soc/d3ba0ea5-0491-42d5-a18e-64cf21df696c@kernel.org= / If SOC_PERIPHERAL_IRQ() doesn't belong to -cpu.dtsi, then "dma-noncoherent;= " probably neither... > > - soc { > > - pinctrl: pinctrl@3001000 { > > - compatible =3D "sophgo,cv1812h-pinctrl"; > > - reg =3D <0x03001000 0x1000>, > > - =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0x05027000 0x1000>; > > - reg-names =3D "sys", "rtc"; > > - }; > > + pinctrl: pinctrl@3001000 { > > + compatible =3D "sophgo,cv1812h-pinctrl"; > > + reg =3D <0x03001000 0x1000>, > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0x05027000 0x1000>; > > + reg-names =3D "sys", "rtc"; > > =C2=A0=C2=A0 }; > > =C2=A0 }; > > =C2=A0=20 > > +&clk { > > + compatible =3D "sophgo,cv1810-clk"; > > +}; > > + > > =C2=A0 &plic { > > =C2=A0=C2=A0 compatible =3D "sophgo,cv1812h-plic", "thead,c900-plic"; > > =C2=A0 }; > > @@ -33,7 +43,3 @@ &plic { > > =C2=A0 &clint { > > =C2=A0=C2=A0 compatible =3D "sophgo,cv1812h-clint", "thead,c900-clint"; > > =C2=A0 }; > > - > > -&clk { > > - compatible =3D "sophgo,cv1810-clk"; > > -}; > >=20 > > [...] > >=20 >=20 > > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-intc.dtsi b/arch/riscv/b= oot/dts/sophgo/cv18xx-intc.dtsi > > new file mode 100644 > > index 000000000000..90817993a326 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/sophgo/cv18xx-intc.dtsi > > @@ -0,0 +1,23 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* > > + * Copyright (C) 2023 Jisheng Zhang > > + * Copyright (C) 2023 Inochi Amaoto > > + */ > > + > > +&soc { > > + interrupt-parent =3D <&plic>; > > + > > + plic: interrupt-controller@70000000 { > > + reg =3D <0x70000000 0x4000000>; > > + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; > > + interrupt-controller; > > + #address-cells =3D <0>; > > + #interrupt-cells =3D <2>; > > + riscv,ndev =3D <101>; > > + }; > > + > > + clint: timer@74000000 { > > + reg =3D <0x74000000 0x10000>; > > + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; > > + }; > > +}; >=20 >=20 > I think this file can be merged in to cv18xx-cpu.dtsi. > clint and plic is more like a core specific device. Yes, this can be done now, as long as SOC_PERIPHERAL_IRQ() remains outside of the -cpu-intc.dtsi... --=20 Alexander Sverdlin.