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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2df5d02fb15sm8331415ad.40.2026.09.22.04.14.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 22 Sep 2026 04:14:18 -0700 (PDT) Message-ID: Date: Tue, 22 Sep 2026 19:14:01 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 00/12] clk: qcom: ipq-cmn-pll: Add IPQ5210 CMN PLL support To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, Konrad Dybcio , Abel Vesa References: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> Content-Language: en-US From: Jie Luo In-Reply-To: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: Q5wYWkl7St9xRd6i1Ii8GX6y8NC1gh3Y X-Authority-Analysis: v=2.4 cv=KqHYSmWN c=1 sm=1 tr=0 ts=6ab2630e cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=bC-a23v3AAAA:8 a=EUspDBNiAAAA:8 a=g-7O86lBZr47vv8Ef_0A:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=FO4_E8m0qiDe52t0p3_H:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIyMDE2MiBTYWx0ZWRfX14gSMaWUYcNQ 4CV5+2X2KcjLnLncHLAyznsspaJee473jg6cQRItc+tBokDYoHC+LwIKiK/y7tzrc5wbLqnxo6/ 14fk72CZJF4wCl2SVjFK8LEaK7+99vqyvBbuSpjC8H+eX1LAUTfjw+5EJW+391KbRr29wSUAlvb orLr+MNjdfOStmR7MZ+GLUlNKitSDWvs6lvWfJvszdQC1JZFa808OsW70eYYLzVHHhqqX2YimNR tkTeIHk0ax/vYkSi3zLZW0SMzAlHit1ZgV9ApvqaHPwsqLpYAKcnTZi0qdcxAyjZabHgpHGitH6 +uwSgGOeYDjtLnll7H4SLM2X7T46fWytBi8qS6bUZUmndJmeHBO1lY4RmDOj4x48w4W84ArQ+g8 Vv7nio9mjBt0b/k05mSorWozrmzj+QDCsPLeW//uJWHGJZPbLkBblKkX/bvR/u92zr0EFzdhitC Rqh2BteUaZ1EG89RRGw== X-Proofpoint-ORIG-GUID: Q5wYWkl7St9xRd6i1Ii8GX6y8NC1gh3Y X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIyMDE2MiBTYWx0ZWRfX1f+WU+PAcfIy XYali3kFSAgE/a+qJWyTa1VU7nkNyJ5izDEGL9OxZ7sSrvzuSAgivnVX6TkxsWmYDIefBm9pNjH HdVDr+1cDg2cxt4TdUz22FDpCkweMzI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-21_07,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 bulkscore=0 priorityscore=1501 phishscore=0 malwarescore=0 suspectscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609220162 Konrad, Abel, Thanks for your review of this patch series. Gentle reminder to re-review v4, which addresses the feedback from v3, for any further comments. Best regards, Jie. On 9/6/2026 10:18 PM, Luo Jie wrote: > The CMN (Common) PLL block of IPQ5210 is almost same as that of IPQ9574 > which is currently supported by the driver. It accepts a 48 MHz reference > clock from the on-board Wi-Fi block and is configured to run at 12 GHz. > The difference is in the output clocks. > > This patch series adds support for IPQ5210 into the CMN PLL clock driver. > On the IPQ5210, the CMN PLL block supplies a broad set of output clocks > to the networking hardware and GCC: > > - NSS (network subsystem): configurable rate via 6-bit divider > - PPE (packet process engine): configurable rate via 6-bit divider > - PON (passive optical network): configurable rate via 8-bit divider, > plus a fixed 31.25 MHz UNIPHY mode > - EPHY-RAW: 125 MHz or 312.5 MHz for the SoC-integrated Ethernet PHY > (EPHY), which supports up to 2.5G link speed: > 125 MHz for 1G/100M/10M, 312.5 MHz for 2.5G > - Gated fixed-rate outputs: PCS 31.25 MHz, ETH0/1/2 50 MHz, > EPHY 50 MHz, ETH 25 MHz > - Fixed-rate outputs: XO 24 MHz, sleep 32 kHz > > The patch series is organised as follows: > > 1/12 clk: convert fixed-rate registration to devm, remove remove callback > 2/12 dt-bindings + clock ID header for IPQ5210 > 3/12 clk-regmap-divider support for CLK_DIVIDER_* flags > 4/12 Register a shared cmn_pll_div2 fixed-factor clock > 5/12 NSS configurable divider clock > 6/12 PPE configurable divider clock > 7/12 PON reference clock with enable/disable and divider > 8/12 EPHY-RAW 125/312.5 MHz select clock > 9/12 clk_fixed_gate gate clock type for gated fixed-rate outputs > 10/12 IPQ5210 output clock array and device match table entry > 11/12 DTS node in ipq5210.dtsi > 12/12 Update IPQ5210 xo_board to use fixed-factor-clock > > Changes in v4: > - Convert the PON reference clock's and clk_fixed_gate's hand-rolled > enable/disable/is_enabled ops to the clk framework's > clk_enable_regmap()/clk_disable_regmap()/clk_is_enabled_regmap() > helpers. > - Convert the EPHY-RAW clock's registration and ops from the > CMN-PLL-specific struct clk_cmn_pll to struct clk_regmap and > devm_clk_register_regmap(), > - Drop the comment above the cmn_pll_div2 fixed-factor clock > registration call; the call itself is self-explanatory. > - Sort the ref_48mhz_clk node alphabetically by label. > - Collect the Reviewed-by tags. > - Link to v3: https://patch.msgid.link/20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com > > Changes in v3: > - Drop the new CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET flag per review > feedback; add a dedicated patch registering a shared cmn_pll_div2 > fixed-factor clock (this /2 stage exists on every supported SoC's > CMN PLL block, so the clock is registered unconditionally (Only > IPQ5210's output clocks currently parent on it). Reparent every > IPQ5210 output clock except the plain fixed-rate xo-24mhz/ > sleep-32khz taps (NSS, PPE, PON, EPHY-RAW, and the gated fixed-rate > clocks) onto it, using the existing CLK_DIVIDER_ONE_BASED flag for > NSS/PPE. Same output rates throughout; more accurately models the > hardware's real shared /2 stage. > - Remove PON's now-redundant internal /2 math to match, and rename its > pon_refclk-suffixed identifiers to pon_clk for consistency with the > other per-clock-type helpers. > - Reword the clk-regmap-divider flags patch to cite CLK_DIVIDER_ONE_BASED > as the motivating flag. > - Collect the Reviewed-by tag. > - Link to v2: https://patch.msgid.link/20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com > > Changes in v2: > - Introduce a new CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET flag in the > generic clk divider framework and re-register the NSS/PPE clocks > as plain clk_regmap_div instances instead of hand-rolled ops. > - Replace the composite clk_fixed_rate + clk_gate implementation for > gated fixed clocks with a dedicated clk_fixed_gate type that reads/ > modifies the shared gate register through regmap. > - Replace the rate/enable_bit/strcmp(name, ...) runtime inference in > ipq_cmn_pll_register_clks() with an explicit enum cmn_pll_clk_type > field, making each output clock's registration path self-describing > instead of implicit in its rate/name/enable_bit fields. > - Update the EPHY-RAW clock's determine_rate() to pick the nearest of > the two supported rates (125 MHz / 312.5 MHz) using the same abs_diff() > - Link to v1: https://patch.msgid.link/20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com > > --- > Luo Jie (12): > clk: qcom: ipq-cmn-pll: Use devm_clk_hw_register_fixed_rate_parent_data > dt-bindings: clock: qcom: Add CMN PLL support for IPQ5210 SoC > clk: qcom: clk-regmap-divider: Support CLK_DIVIDER_* flags > clk: qcom: ipq-cmn-pll: Register CMN PLL /2 clock > clk: qcom: ipq-cmn-pll: Add NSS clock support > clk: qcom: ipq-cmn-pll: Add PPE clock support > clk: qcom: ipq-cmn-pll: Add PON reference clock support > clk: qcom: ipq-cmn-pll: Add EPHY-RAW clock support > clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks > clk: qcom: ipq-cmn-pll: Add all output clocks for IPQ5210 > arm64: dts: qcom: ipq5210: Add CMN PLL device node > arm64: dts: qcom: Update IPQ5210 xo_board to use fixed factor clock > > .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 + > arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 22 +- > arch/arm64/boot/dts/qcom/ipq5210.dtsi | 27 +- > drivers/clk/qcom/clk-regmap-divider.c | 16 +- > drivers/clk/qcom/clk-regmap-divider.h | 1 + > drivers/clk/qcom/ipq-cmn-pll.c | 535 +++++++++++++++++++-- > include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h | 30 ++ > 7 files changed, 591 insertions(+), 41 deletions(-) > --- > base-commit: af5f12805e5cefa4fe68d6127c7e1fb78cd5535c > change-id: 20260724-qcom_ipq5210_cmnpll-0eb9a9615dff > > Best regards, > -- > Luo Jie >