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Wed, 15 Jan 2025 06:10:15 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50F6ADsi021363 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Jan 2025 06:10:14 GMT Received: from [10.152.195.140] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 14 Jan 2025 22:10:08 -0800 Message-ID: Date: Wed, 15 Jan 2025 11:40:05 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] arm64: dts: qcom: ipq5424: Enable PCIe PHYs and controllers To: Varadarajan Narayanan CC: , , , , , , , , , , , , , , , , References: <20241213134950.234946-1-quic_mmanikan@quicinc.com> <20241213134950.234946-5-quic_mmanikan@quicinc.com> Content-Language: en-US From: Manikanta Mylavarapu In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 3_2duaB9QtO-ValdXUL5KxjW83haJFRj X-Proofpoint-ORIG-GUID: 3_2duaB9QtO-ValdXUL5KxjW83haJFRj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-15_02,2025-01-13_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxlogscore=713 priorityscore=1501 phishscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 suspectscore=0 bulkscore=0 mlxscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501150043 On 1/3/2025 12:22 PM, Varadarajan Narayanan wrote: > On Fri, Dec 13, 2024 at 07:19:50PM +0530, Manikanta Mylavarapu wrote: > > [ . . . ] > >> +&pcie2_phy { >> + status = "okay"; >> +}; >> + >> +&pcie2 { >> + pinctrl-0 = <&pcie2_default_state>; >> + pinctrl-names = "default"; >> + >> + perst-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; >> + status = "okay"; >> +}; > > pcie2 should come before pcie2_phy > Okay, i will update in the next version. >> + >> +&pcie3_phy { >> + status = "okay"; >> +}; >> + >> +&pcie3 { >> + pinctrl-0 = <&pcie3_default_state>; >> + pinctrl-names = "default"; >> + >> + perst-gpios = <&tlmm 34 GPIO_ACTIVE_LOW>; >> + status = "okay"; >> +}; > > same here. Okay, i will update in the next version. Thanks & Regards, Manikanta.