Re: [PATCH 1/5] dt-bindings: PCI: mediatek-gen3: Add MT8196 support

["Jianjun Wang (王建军)" <Jianjun.Wang@mediatek.com>]

On Tue, 2025-01-07 at 14:04 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until
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> 
> 
> Il 06/01/25 10:19, Jianjun Wang (王建军) ha scritto:
> > On Fri, 2025-01-03 at 10:26 +0100, AngeloGioacchino Del Regno
> > wrote:
> > > External email : Please do not click links or open attachments
> > > until
> > > you have verified the sender or the content.
> > > 
> > > 
> > > Il 03/01/25 07:00, Jianjun Wang ha scritto:
> > > > Add compatible string and clock definition for MT8196. It has 6
> > > > clocks like
> > > > the MT8195, but 2 of them are different.
> > > > 
> > > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> > > > ---
> > > >    .../bindings/pci/mediatek-pcie-gen3.yaml      | 29
> > > > +++++++++++++++++++
> > > >    1 file changed, 29 insertions(+)
> > > > 
> > > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-
> > > > pcie-
> > > > gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-
> > > > pcie-
> > > > gen3.yaml
> > > > index f05aab2b1add..b4158a666fb6 100644
> > > > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-
> > > > gen3.yaml
> > > > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-
> > > > gen3.yaml
> > > > @@ -51,6 +51,7 @@ properties:
> > > >                  - mediatek,mt7986-pcie
> > > >                  - mediatek,mt8188-pcie
> > > >                  - mediatek,mt8195-pcie
> > > > +              - mediatek,mt8196-pcie
> > > >              - const: mediatek,mt8192-pcie
> > > >          - const: mediatek,mt8192-pcie
> > > >          - const: airoha,en7581-pcie
> > > > @@ -197,6 +198,34 @@ allOf:
> > > >              minItems: 1
> > > >              maxItems: 2
> > > > 
> > > > +  - if:
> > > > +      properties:
> > > > +        compatible:
> > > > +          contains:
> > > > +            enum:
> > > > +              - mediatek,mt8196-pcie
> > > > +    then:
> > > > +      properties:
> > > > +        clocks:
> > > > +          minItems: 6
> > > > +
> > > > +        clock-names:
> > > > +          items:
> > > > +            - const: pl_250m
> > > > +            - const: tl_26m
> > > > +            - const: peri_26m
> > > > +            - const: peri_mem
> > > > +            - const: ahb_apb
> > > 
> > > ahb_apb is a bus clock, so you can set it as
> > > 
> > > - const: bus
> > 
> > Agree, I'll change it to "bus" in the next version, thanks.
> > 
> > > 
> > > 
> > > > +            - const: low_power
> > > 
> > > Can you please clarify what the LP clock is for?
> > 
> > This is a power-saving clock. Its clock source consumes less power
> > than
> > a regular clock, we need to keep this clock on if when entering
> > L1.2
> > during suspend.
> > 
> 
> In the driver, you are keeping all clocks ON instead.
> 
> Is this clock required to be ON when the full power ones are enabled
> and
> the SoC is not in suspend state?

This clock affects the exit from L1.2 via the CLKREQ# signal, and ASPM
L1.2 can be entered in the normal state. Therefore, we need to keep it
on like the other clocks.

> 
> Can you please add handling for this "special" clock so that we can
> save power
> during suspend?

When entering the L1.2 state, this clock is the only clock needed by
the PCIe HW. However, since ASPM L1.2 is controlled by HW and we don't
know when it will exit(e.g., exit by the device side), we still need to
keep other clocks on to ensure the PCIe is ready to work.

Thanks.

> 
> Cheers,
> Angelo
> 
> > Thanks.
> > 
> > > 
> > > Thanks,
> > > Angelo
> > > 
> > > > +
> > > > +        resets:
> > > > +          minItems: 1
> > > > +          maxItems: 2
> > > > +
> > > > +        reset-names:
> > > > +          minItems: 1
> > > > +          maxItems: 2
> > > > +
> > > >      - if:
> > > >          properties:
> > > >            compatible:
> > > 
> > > 
> 
> 
>