From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Biju Das <biju.das.jz@bp.renesas.com>,
Thierry Reding <thierry.reding@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Chris Paterson" <chris.paterson2@renesas.com>,
"Prabhakar Mahadev Lad" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH 2/3] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property
Date: Fri, 4 Nov 2022 11:04:59 -0400 [thread overview]
Message-ID: <dea44f32-e10f-0164-0175-4fe2e5d053a2@linaro.org> (raw)
In-Reply-To: <20221104145938.1782464-3-biju.das.jz@bp.renesas.com>
On 04/11/2022 10:59, Biju Das wrote:
> RZ/G2L GPT IP supports output pin disable function by dead time
> error and detecting short-circuits between output pins.
>
> Add documentation for the optional property renesas,poegs to
> link a pair of GPT IOs with POEG.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> .../bindings/pwm/renesas,rzg2l-gpt.yaml | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> index 620d5ae4ae30..32f9deae89e5 100644
> --- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> @@ -245,6 +245,24 @@ properties:
> resets:
> maxItems: 1
>
> + renesas,poegs:
> + $ref: "/schemas/types.yaml#/definitions/phandle-array"
No need for quotes.
> + items:
You miss here maxItems... but if you have just one item, then below
"items" should be " - items"
> + items:
> + - description: phandle to POEG instance that serves the output disable
> + - description: An index identifying pair of GPT channels.
> + <0> - GPT channels 0 and 1
> + <1> - GPT channels 2 and 3
> + <2> - GPT channels 4 and 5
> + <3> - GPT channels 6 and 7
> + <4> - GPT channels 8 and 9
> + <5> - GPT channels 10 and 11
> + <6> - GPT channels 12 and 13
> + <7> - GPT channels 14 and 15
then this could bave enum or minimum/maximum. Can you try if these work?
> + description:
> + A list of phandle and channel index pair tuples to the POEGs that handle the
> + output disable for the GPT channels.
> +
> required:
> - compatible
> - reg
> @@ -375,4 +393,5 @@ examples:
> power-domains = <&cpg>;
> resets = <&cpg R9A07G044_GPT_RST_C>;
> #pwm-cells = <2>;
> + renesas,poegs = <&poeggd 4>;
> };
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-11-04 15:05 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-04 14:59 [PATCH 0/3] Add support for linking gpt with poeg Biju Das
2022-11-04 14:59 ` [PATCH 1/3] dt-bindings: pwm: Add RZ/G2L GPT binding Biju Das
2022-11-04 15:02 ` Krzysztof Kozlowski
2022-11-04 15:58 ` Biju Das
2022-11-04 14:59 ` [PATCH 2/3] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property Biju Das
2022-11-04 15:04 ` Krzysztof Kozlowski [this message]
2022-11-04 15:32 ` Biju Das
2022-11-04 16:52 ` Biju Das
2022-11-04 17:10 ` Krzysztof Kozlowski
2022-11-11 6:50 ` Biju Das
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