[PATCH 0/4] Make i.MX8M Nano OCOTP work as accessing controller

[PATCH 0/4] Make i.MX8M Nano OCOTP work as accessing controller

[Alexander Stein]

Hi,

inspired by [1] this adds the accessing controller feature to i.MX8M Nano.
The OCOTP eFuse has bits which can disable particular peripherals, such as
GPU, MIPI-DSI oder USB.

In OCOTP driver, the nodes under "/" will be iterated, and checked
if property "#access-controllers" exsits. If not allow access, detach
the node.

I successfully used this on a i.MX8M Nano DualLite which has GPU disabled.
Without this patchset the default DT completly freezes the SoC if GPU
is accessed.
Using this patchset the GPU is disabled without any DT modification from
bootloader:
> imx_ocotp 30350000.efuse: /soc@0/gpu@38000000: disabled by fuse, device driver will not be probed

Adding the other i.MX8M SoCs is straight forward.

Best regards,
Alexander

[1] https://lore.kernel.org/all/20250121-imx-ocotp-v6-0-76dab40e13db@nxp.com/

Alexander Stein (4):
  dt-bindings: nvmem: imx-ocotp: Add i.MX8M Nano access controller
    definitions
  nvmem: imx-ocotp: Sort header alphabetically
  nvmem: imx-ocotp: Support accessing controller for i.MX8M Nano
  arm64: dts: imx8mn: Add access-controller references

 arch/arm64/boot/dts/freescale/imx8mn.dtsi    |   8 ++
 drivers/nvmem/Kconfig                        |   3 +
 drivers/nvmem/imx-ocotp.c                    | 107 ++++++++++++++++++-
 include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h |  16 +++
 4 files changed, 132 insertions(+), 2 deletions(-)
 create mode 100644 include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h

-- 
2.34.1

[PATCH 1/4] dt-bindings: nvmem: imx-ocotp: Add i.MX8M Nano access controller definitions

[Alexander Stein]

These are the definition for the bindings of imx-ocotp for disabling
fuses.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h

diff --git a/include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h b/include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h
new file mode 100644
index 0000000000000..6e554edefd488
--- /dev/null
+++ b/include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+
+#ifndef _DT_BINDINGS_NVMEM_IMX8MN_OCOTP_H
+#define _DT_BINDINGS_NVMEM_IMX8MN_OCOTP_H
+
+#define IMX8MN_OCOTP_M7_DISABLE		0
+#define IMX8MN_OCOTP_M7_MPU_DISABLE	1
+#define IMX8MN_OCOTP_M7_FPU_DISABLE	2
+#define IMX8MN_OCOTP_USB_OTG1_DISABLE	3
+#define IMX8MN_OCOTP_GPU3D_DISABLE	4
+#define IMX8MN_OCOTP_MIPI_DSI_DISABLE	5
+#define IMX8MN_OCOTP_ENET_DISABLE	6
+#define IMX8MN_OCOTP_MIPI_CSI_DISABLE	7
+#define IMX8MN_OCOTP_ASRC_DISABLE	8
+
+#endif
-- 
2.34.1

[PATCH 2/4] nvmem: imx-ocotp: Sort header alphabetically

[Alexander Stein]

Move linux/delay.h to the right position.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 drivers/nvmem/imx-ocotp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 79dd4fda03295..c5086a16450ac 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -15,6 +15,7 @@
  */
 
 #include <linux/clk.h>
+#include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/io.h>
 #include <linux/module.h>
@@ -22,7 +23,6 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
-#include <linux/delay.h>
 
 #define IMX_OCOTP_OFFSET_B0W0		0x400 /* Offset from base address of the
 					       * OTP Bank0 Word0
-- 
2.34.1

[PATCH 3/4] nvmem: imx-ocotp: Support accessing controller for i.MX8M Nano

[Alexander Stein]

i.MX8M OCOTP supports a specific peripheral or function being fused
which means disabled, so
 - Introduce disable_fuse for a list of possible fused peripherals.
 - Iterate all nodes to check accessing permission. If not
   allowed to be accessed, detach the node

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 drivers/nvmem/Kconfig     |   3 ++
 drivers/nvmem/imx-ocotp.c | 105 +++++++++++++++++++++++++++++++++++++-
 2 files changed, 107 insertions(+), 1 deletion(-)

diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 8671b7c974b93..ba5c928cab520 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -84,6 +84,9 @@ config NVMEM_IMX_OCOTP
 	  This driver can also be built as a module. If so, the module
 	  will be called nvmem-imx-ocotp.
 
+	  If built as modules, any other driver relying on this working
+	  as access controller also needs to be a module as well.
+
 config NVMEM_IMX_OCOTP_ELE
 	tristate "i.MX On-Chip OTP Controller support"
 	depends on ARCH_MXC || COMPILE_TEST
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index c5086a16450ac..e3ea026a37d0d 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -23,6 +23,7 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <dt-bindings/nvmem/fsl,imx8mn-ocotp.h>
 
 #define IMX_OCOTP_OFFSET_B0W0		0x400 /* Offset from base address of the
 					       * OTP Bank0 Word0
@@ -91,11 +92,20 @@ struct ocotp_ctrl_reg {
 	u32 bm_rel_shadows;
 };
 
+#define OCOTP_MAX_NUM_GATE_WORDS 4
+
+struct disable_fuse {
+	u32 fuse_addr;
+	u32 mask;
+};
+
 struct ocotp_params {
 	unsigned int nregs;
 	unsigned int bank_address_words;
 	void (*set_timing)(struct ocotp_priv *priv);
 	struct ocotp_ctrl_reg ctrl;
+	u32 num_disables;
+	struct disable_fuse *disables;
 };
 
 static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags)
@@ -552,11 +562,25 @@ static const struct ocotp_params imx8mm_params = {
 	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 };
 
+struct disable_fuse imx8mn_disable_fuse[] = {
+		[IMX8MN_OCOTP_M7_DISABLE]	= { .fuse_addr = 20, .mask = BIT(8) },
+		[IMX8MN_OCOTP_M7_MPU_DISABLE]	= { .fuse_addr = 20, .mask = BIT(9) },
+		[IMX8MN_OCOTP_M7_FPU_DISABLE]	= { .fuse_addr = 20, .mask = BIT(10) },
+		[IMX8MN_OCOTP_USB_OTG1_DISABLE]	= { .fuse_addr = 20, .mask = BIT(11) },
+		[IMX8MN_OCOTP_GPU3D_DISABLE]	= { .fuse_addr = 20, .mask = BIT(24) },
+		[IMX8MN_OCOTP_MIPI_DSI_DISABLE]	= { .fuse_addr = 20, .mask = BIT(28) },
+		[IMX8MN_OCOTP_ENET_DISABLE]	= { .fuse_addr = 20, .mask = BIT(29) },
+		[IMX8MN_OCOTP_MIPI_CSI_DISABLE]	= { .fuse_addr = 20, .mask = BIT(30) },
+		[IMX8MN_OCOTP_ASRC_DISABLE]	= { .fuse_addr = 20, .mask = BIT(31) },
+};
+
 static const struct ocotp_params imx8mn_params = {
 	.nregs = 256,
 	.bank_address_words = 0,
 	.set_timing = imx_ocotp_set_imx6_timing,
 	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
+	.num_disables = ARRAY_SIZE(imx8mn_disable_fuse),
+	.disables = imx8mn_disable_fuse,
 };
 
 static const struct ocotp_params imx8mp_params = {
@@ -589,6 +613,81 @@ static void imx_ocotp_fixup_dt_cell_info(struct nvmem_device *nvmem,
 	cell->read_post_process = imx_ocotp_cell_pp;
 }
 
+static int imx_ocotp_check_access(struct ocotp_priv *priv, u32 id)
+{
+	u32 addr, mask, ret, val;
+
+	if (id >= priv->params->num_disables) {
+		dev_err(priv->dev, "Index %d too large\n", id);
+		return -EACCES;
+	}
+
+	addr = priv->params->disables[id].fuse_addr;
+	mask = priv->params->disables[id].mask;
+
+	ret = imx_ocotp_read(priv, addr, &val, sizeof(val));
+	if (ret)
+		return ret;
+
+	dev_dbg(priv->dev, "id:%d addr:%#x mask:0x%08x\n", id, addr, mask);
+	/* true means disabled */
+	if (val & mask)
+		return -EACCES;
+
+	return 0;
+}
+
+static int imx_ocotp_grant_access(struct ocotp_priv *priv, struct device_node *parent)
+{
+	struct device *dev = priv->dev;
+
+	for_each_available_child_of_node_scoped(parent, child) {
+		struct of_phandle_args args;
+		u32 id, idx = 0;
+
+		while (!of_parse_phandle_with_args(child, "access-controllers",
+						   "#access-controller-cells",
+						   idx++, &args)) {
+			of_node_put(args.np);
+			if (args.np != dev->of_node)
+				continue;
+
+			/* Only support one cell */
+			if (args.args_count != 1) {
+				dev_err(dev, "wrong args count\n");
+				continue;
+			}
+
+			id = args.args[0];
+
+			dev_dbg(dev, "Checking node: %pOF disable ID: %d\n", child, id);
+
+			if (imx_ocotp_check_access(priv, id)) {
+				of_detach_node(child);
+				dev_info(dev, "%pOF: disabled by fuse, device driver will not be probed\n",
+					 child);
+			}
+		}
+
+		imx_ocotp_grant_access(priv, child);
+	}
+
+	return 0;
+}
+
+static int imx_ocotp_access_control(struct ocotp_priv *priv)
+{
+	struct device_node *root __free(device_node) = of_find_node_by_path("/");
+
+	if (!priv->params->disables)
+		return 0;
+
+	if (WARN_ON(!root))
+		return -EINVAL;
+
+	return imx_ocotp_grant_access(priv, root);
+}
+
 static int imx_ocotp_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -622,9 +721,13 @@ static int imx_ocotp_probe(struct platform_device *pdev)
 	imx_ocotp_clr_err_if_set(priv);
 	clk_disable_unprepare(priv->clk);
 
+	platform_set_drvdata(pdev, priv);
+
 	nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
+	if (IS_ERR(nvmem))
+		return PTR_ERR(nvmem);
 
-	return PTR_ERR_OR_ZERO(nvmem);
+	return imx_ocotp_access_control(priv);
 }
 
 static struct platform_driver imx_ocotp_driver = {
-- 
2.34.1

[PATCH 4/4] arm64: dts: imx8mn: Add access-controller references

[Alexander Stein]

Mark ocotp as a access-controller and add references on peripherals
which can be disabled (fused).

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 arch/arm64/boot/dts/freescale/imx8mn.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index a5f9cfb46e5dd..b023724679b80 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/nvmem/fsl,imx8mn-ocotp.h>
 #include <dt-bindings/thermal/thermal.h>
 
 #include "imx8mn-pinfunc.h"
@@ -431,6 +432,7 @@ easrc: easrc@300c0000 {
 					firmware-name = "imx/easrc/easrc-imx8mn.bin";
 					fsl,asrc-rate = <8000>;
 					fsl,asrc-format = <2>;
+					access-controllers = <&ocotp IMX8MN_OCOTP_ASRC_DISABLE>;
 					status = "disabled";
 				};
 			};
@@ -571,6 +573,7 @@ ocotp: efuse@30350000 {
 				clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
 				#address-cells = <1>;
 				#size-cells = <1>;
+				#access-controller-cells = <1>;
 
 				/*
 				 * The register address below maps to the MX8M
@@ -1053,6 +1056,7 @@ fec1: ethernet@30be0000 {
 				nvmem-cells = <&fec_mac_address>;
 				nvmem-cell-names = "mac-address";
 				fsl,stop-mode = <&gpr 0x10 3>;
+				access-controllers = <&ocotp IMX8MN_OCOTP_ENET_DISABLE>;
 				status = "disabled";
 			};
 
@@ -1091,6 +1095,7 @@ mipi_dsi: dsi@32e10000 {
 				clock-names = "bus_clk", "sclk_mipi";
 				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 				power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
+				access-controllers = <&ocotp IMX8MN_OCOTP_MIPI_DSI_DISABLE>;
 				status = "disabled";
 
 				ports {
@@ -1195,6 +1200,7 @@ mipi_csi: mipi-csi@32e30000 {
 					 <&clk IMX8MN_CLK_DISP_AXI_ROOT>;
 				clock-names = "pclk", "wrap", "phy", "axi";
 				power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>;
+				access-controllers = <&ocotp IMX8MN_OCOTP_MIPI_CSI_DISABLE>;
 				status = "disabled";
 
 				ports {
@@ -1225,6 +1231,7 @@ usbotg1: usb@32e40000 {
 				phys = <&usbphynop1>;
 				fsl,usbmisc = <&usbmisc1 0>;
 				power-domains = <&pgc_hsiomix>;
+				access-controllers = <&ocotp IMX8MN_OCOTP_USB_OTG1_DISABLE>;
 				status = "disabled";
 			};
 
@@ -1288,6 +1295,7 @@ gpu: gpu@38000000 {
 					       <400000000>,
 					       <1200000000>;
 			power-domains = <&pgc_gpumix>;
+			access-controllers = <&ocotp IMX8MN_OCOTP_GPU3D_DISABLE>;
 		};
 
 		gic: interrupt-controller@38800000 {
-- 
2.34.1

Re: [PATCH 1/4] dt-bindings: nvmem: imx-ocotp: Add i.MX8M Nano access controller definitions

[Frank Li]

On Thu, Jan 30, 2025 at 02:00:58PM +0100, Alexander Stein wrote:
> These are the definition for the bindings of imx-ocotp for disabling
> fuses.
>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>  create mode 100644 include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h
>
> diff --git a/include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h b/include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h
> new file mode 100644
> index 0000000000000..6e554edefd488
> --- /dev/null
> +++ b/include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
> +
> +#ifndef _DT_BINDINGS_NVMEM_IMX8MN_OCOTP_H
> +#define _DT_BINDINGS_NVMEM_IMX8MN_OCOTP_H
> +
> +#define IMX8MN_OCOTP_M7_DISABLE		0
> +#define IMX8MN_OCOTP_M7_MPU_DISABLE	1
> +#define IMX8MN_OCOTP_M7_FPU_DISABLE	2
> +#define IMX8MN_OCOTP_USB_OTG1_DISABLE	3
> +#define IMX8MN_OCOTP_GPU3D_DISABLE	4
> +#define IMX8MN_OCOTP_MIPI_DSI_DISABLE	5
> +#define IMX8MN_OCOTP_ENET_DISABLE	6
> +#define IMX8MN_OCOTP_MIPI_CSI_DISABLE	7
> +#define IMX8MN_OCOTP_ASRC_DISABLE	8
> +
> +#endif
> --
> 2.34.1
>

Re: [PATCH 2/4] nvmem: imx-ocotp: Sort header alphabetically

[Frank Li]

On Thu, Jan 30, 2025 at 02:00:59PM +0100, Alexander Stein wrote:
> Move linux/delay.h to the right position.
>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  drivers/nvmem/imx-ocotp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
> index 79dd4fda03295..c5086a16450ac 100644
> --- a/drivers/nvmem/imx-ocotp.c
> +++ b/drivers/nvmem/imx-ocotp.c
> @@ -15,6 +15,7 @@
>   */
>
>  #include <linux/clk.h>
> +#include <linux/delay.h>
>  #include <linux/device.h>
>  #include <linux/io.h>
>  #include <linux/module.h>
> @@ -22,7 +23,6 @@
>  #include <linux/of.h>
>  #include <linux/platform_device.h>
>  #include <linux/slab.h>
> -#include <linux/delay.h>
>
>  #define IMX_OCOTP_OFFSET_B0W0		0x400 /* Offset from base address of the
>  					       * OTP Bank0 Word0
> --
> 2.34.1
>

Re: [PATCH 3/4] nvmem: imx-ocotp: Support accessing controller for i.MX8M Nano

[Frank Li]

On Thu, Jan 30, 2025 at 02:01:00PM +0100, Alexander Stein wrote:
> i.MX8M OCOTP supports a specific peripheral or function being fused
> which means disabled, so
>  - Introduce disable_fuse for a list of possible fused peripherals.
>  - Iterate all nodes to check accessing permission. If not
>    allowed to be accessed, detach the node
>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
>  drivers/nvmem/Kconfig     |   3 ++
>  drivers/nvmem/imx-ocotp.c | 105 +++++++++++++++++++++++++++++++++++++-
>  2 files changed, 107 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
> index 8671b7c974b93..ba5c928cab520 100644
> --- a/drivers/nvmem/Kconfig
> +++ b/drivers/nvmem/Kconfig
> @@ -84,6 +84,9 @@ config NVMEM_IMX_OCOTP
>  	  This driver can also be built as a module. If so, the module
>  	  will be called nvmem-imx-ocotp.
>
> +	  If built as modules, any other driver relying on this working
> +	  as access controller also needs to be a module as well.
> +
>  config NVMEM_IMX_OCOTP_ELE
>  	tristate "i.MX On-Chip OTP Controller support"
>  	depends on ARCH_MXC || COMPILE_TEST
> diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
> index c5086a16450ac..e3ea026a37d0d 100644
> --- a/drivers/nvmem/imx-ocotp.c
> +++ b/drivers/nvmem/imx-ocotp.c
> @@ -23,6 +23,7 @@
>  #include <linux/of.h>
>  #include <linux/platform_device.h>
>  #include <linux/slab.h>
> +#include <dt-bindings/nvmem/fsl,imx8mn-ocotp.h>
>
>  #define IMX_OCOTP_OFFSET_B0W0		0x400 /* Offset from base address of the
>  					       * OTP Bank0 Word0
> @@ -91,11 +92,20 @@ struct ocotp_ctrl_reg {
>  	u32 bm_rel_shadows;
>  };
>
> +#define OCOTP_MAX_NUM_GATE_WORDS 4
> +
> +struct disable_fuse {
> +	u32 fuse_addr;
> +	u32 mask;
> +};
> +
>  struct ocotp_params {
>  	unsigned int nregs;
>  	unsigned int bank_address_words;
>  	void (*set_timing)(struct ocotp_priv *priv);
>  	struct ocotp_ctrl_reg ctrl;
> +	u32 num_disables;
> +	struct disable_fuse *disables;
>  };
>
>  static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags)
> @@ -552,11 +562,25 @@ static const struct ocotp_params imx8mm_params = {
>  	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
>  };
>
> +struct disable_fuse imx8mn_disable_fuse[] = {
> +		[IMX8MN_OCOTP_M7_DISABLE]	= { .fuse_addr = 20, .mask = BIT(8) },
> +		[IMX8MN_OCOTP_M7_MPU_DISABLE]	= { .fuse_addr = 20, .mask = BIT(9) },
> +		[IMX8MN_OCOTP_M7_FPU_DISABLE]	= { .fuse_addr = 20, .mask = BIT(10) },
> +		[IMX8MN_OCOTP_USB_OTG1_DISABLE]	= { .fuse_addr = 20, .mask = BIT(11) },
> +		[IMX8MN_OCOTP_GPU3D_DISABLE]	= { .fuse_addr = 20, .mask = BIT(24) },
> +		[IMX8MN_OCOTP_MIPI_DSI_DISABLE]	= { .fuse_addr = 20, .mask = BIT(28) },
> +		[IMX8MN_OCOTP_ENET_DISABLE]	= { .fuse_addr = 20, .mask = BIT(29) },
> +		[IMX8MN_OCOTP_MIPI_CSI_DISABLE]	= { .fuse_addr = 20, .mask = BIT(30) },
> +		[IMX8MN_OCOTP_ASRC_DISABLE]	= { .fuse_addr = 20, .mask = BIT(31) },
> +};

Can we direct define IMX8MN_OCOTP_M7_DISABLE as BIT(8), so avoid this
map data?

> +
>  static const struct ocotp_params imx8mn_params = {
>  	.nregs = 256,
>  	.bank_address_words = 0,
>  	.set_timing = imx_ocotp_set_imx6_timing,
>  	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
> +	.num_disables = ARRAY_SIZE(imx8mn_disable_fuse),
> +	.disables = imx8mn_disable_fuse,
>  };
>
>  static const struct ocotp_params imx8mp_params = {
> @@ -589,6 +613,81 @@ static void imx_ocotp_fixup_dt_cell_info(struct nvmem_device *nvmem,
>  	cell->read_post_process = imx_ocotp_cell_pp;
>  }
>
> +static int imx_ocotp_check_access(struct ocotp_priv *priv, u32 id)
> +{
> +	u32 addr, mask, ret, val;
> +
> +	if (id >= priv->params->num_disables) {
> +		dev_err(priv->dev, "Index %d too large\n", id);
> +		return -EACCES;
> +	}
> +
> +	addr = priv->params->disables[id].fuse_addr;
> +	mask = priv->params->disables[id].mask;
> +
> +	ret = imx_ocotp_read(priv, addr, &val, sizeof(val));
> +	if (ret)
> +		return ret;
> +
> +	dev_dbg(priv->dev, "id:%d addr:%#x mask:0x%08x\n", id, addr, mask);
> +	/* true means disabled */
> +	if (val & mask)
> +		return -EACCES;
> +
> +	return 0;
> +}
> +
> +static int imx_ocotp_grant_access(struct ocotp_priv *priv, struct device_node *parent)
> +{
> +	struct device *dev = priv->dev;
> +
> +	for_each_available_child_of_node_scoped(parent, child) {
> +		struct of_phandle_args args;
> +		u32 id, idx = 0;
> +
> +		while (!of_parse_phandle_with_args(child, "access-controllers",
> +						   "#access-controller-cells",
> +						   idx++, &args)) {
> +			of_node_put(args.np);
> +			if (args.np != dev->of_node)
> +				continue;
> +
> +			/* Only support one cell */
> +			if (args.args_count != 1) {
> +				dev_err(dev, "wrong args count\n");
> +				continue;
> +			}
> +
> +			id = args.args[0];
> +
> +			dev_dbg(dev, "Checking node: %pOF disable ID: %d\n", child, id);
> +
> +			if (imx_ocotp_check_access(priv, id)) {
> +				of_detach_node(child);
> +				dev_info(dev, "%pOF: disabled by fuse, device driver will not be probed\n",
> +					 child);
> +			}
> +		}
> +
> +		imx_ocotp_grant_access(priv, child);
> +	}
> +
> +	return 0;
> +}

Can we have one method to share above code logic to avoid copy-paste to
every ocotp driver? Anyway, we can improve that later.

Reviewed-by: Frank Li <Frank.Li@nxp.com>


> +
> +static int imx_ocotp_access_control(struct ocotp_priv *priv)
> +{
> +	struct device_node *root __free(device_node) = of_find_node_by_path("/");
> +
> +	if (!priv->params->disables)
> +		return 0;
> +
> +	if (WARN_ON(!root))
> +		return -EINVAL;
> +
> +	return imx_ocotp_grant_access(priv, root);
> +}
> +
>  static int imx_ocotp_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> @@ -622,9 +721,13 @@ static int imx_ocotp_probe(struct platform_device *pdev)
>  	imx_ocotp_clr_err_if_set(priv);
>  	clk_disable_unprepare(priv->clk);
>
> +	platform_set_drvdata(pdev, priv);
> +
>  	nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
> +	if (IS_ERR(nvmem))
> +		return PTR_ERR(nvmem);
>
> -	return PTR_ERR_OR_ZERO(nvmem);
> +	return imx_ocotp_access_control(priv);
>  }
>
>  static struct platform_driver imx_ocotp_driver = {
> --
> 2.34.1
>

Re: [PATCH 1/4] dt-bindings: nvmem: imx-ocotp: Add i.MX8M Nano access controller definitions

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 275 bytes --]

On Thu, Jan 30, 2025 at 02:00:58PM +0100, Alexander Stein wrote:
> These are the definition for the bindings of imx-ocotp for disabling
> fuses.
> 
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 0/4] Make i.MX8M Nano OCOTP work as accessing controller

[Rob Herring (Arm)]

On Thu, 30 Jan 2025 14:00:57 +0100, Alexander Stein wrote:
> Hi,
> 
> inspired by [1] this adds the accessing controller feature to i.MX8M Nano.
> The OCOTP eFuse has bits which can disable particular peripherals, such as
> GPU, MIPI-DSI oder USB.
> 
> In OCOTP driver, the nodes under "/" will be iterated, and checked
> if property "#access-controllers" exsits. If not allow access, detach
> the node.
> 
> I successfully used this on a i.MX8M Nano DualLite which has GPU disabled.
> Without this patchset the default DT completly freezes the SoC if GPU
> is accessed.
> Using this patchset the GPU is disabled without any DT modification from
> bootloader:
> > imx_ocotp 30350000.efuse: /soc@0/gpu@38000000: disabled by fuse, device driver will not be probed
> 
> Adding the other i.MX8M SoCs is straight forward.
> 
> Best regards,
> Alexander
> 
> [1] https://lore.kernel.org/all/20250121-imx-ocotp-v6-0-76dab40e13db@nxp.com/
> 
> Alexander Stein (4):
>   dt-bindings: nvmem: imx-ocotp: Add i.MX8M Nano access controller
>     definitions
>   nvmem: imx-ocotp: Sort header alphabetically
>   nvmem: imx-ocotp: Support accessing controller for i.MX8M Nano
>   arm64: dts: imx8mn: Add access-controller references
> 
>  arch/arm64/boot/dts/freescale/imx8mn.dtsi    |   8 ++
>  drivers/nvmem/Kconfig                        |   3 +
>  drivers/nvmem/imx-ocotp.c                    | 107 ++++++++++++++++++-
>  include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h |  16 +++
>  4 files changed, 132 insertions(+), 2 deletions(-)
>  create mode 100644 include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h
> 
> --
> 2.34.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/freescale/' for 20250130130101.1040824-1-alexander.stein@ew.tq-group.com:

arch/arm64/boot/dts/freescale/imx8mn-evk.dtb: easrc@300c0000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/sound/fsl,easrc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dtb: easrc@300c0000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/sound/fsl,easrc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dtb: easrc@300c0000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/sound/fsl,easrc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dtb: easrc@300c0000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/sound/fsl,easrc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dtb: easrc@300c0000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/sound/fsl,easrc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-dimonoff-gateway-evk.dtb: easrc@300c0000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/sound/fsl,easrc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dtb: easrc@300c0000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/sound/fsl,easrc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-evk.dtb: efuse@30350000: Unevaluated properties are not allowed ('#access-controller-cells' was unexpected)
	from schema $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dtb: efuse@30350000: Unevaluated properties are not allowed ('#access-controller-cells' was unexpected)
	from schema $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dtb: efuse@30350000: Unevaluated properties are not allowed ('#access-controller-cells' was unexpected)
	from schema $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dtb: efuse@30350000: Unevaluated properties are not allowed ('#access-controller-cells' was unexpected)
	from schema $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dtb: efuse@30350000: Unevaluated properties are not allowed ('#access-controller-cells' was unexpected)
	from schema $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dtb: efuse@30350000: Unevaluated properties are not allowed ('#access-controller-cells' was unexpected)
	from schema $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
arch/arm64/boot/dts/freescale/imx8mn-dimonoff-gateway-evk.dtb: efuse@30350000: Unevaluated properties are not allowed ('#access-controller-cells' was unexpected)
	from schema $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dtb: easrc@300c0000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/sound/fsl,easrc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-evk.dtb: ethernet@30be0000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/net/fsl,fec.yaml#
arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dtb: ethernet@30be0000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/net/fsl,fec.yaml#
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dtb: efuse@30350000: Unevaluated properties are not allowed ('#access-controller-cells' was unexpected)
	from schema $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dtb: ethernet@30be0000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/net/fsl,fec.yaml#
arch/arm64/boot/dts/freescale/imx8mn-evk.dtb: dsi@32e10000: access-controllers: [[20, 5]] is not of type 'object'
	from schema $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dtb: ethernet@30be0000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/net/fsl,fec.yaml#
arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dtb: dsi@32e10000: access-controllers: [[20, 5]] is not of type 'object'
	from schema $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dtb: dsi@32e10000: access-controllers: [[16, 5]] is not of type 'object'
	from schema $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dtb: ethernet@30be0000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/net/fsl,fec.yaml#
arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dtb: dsi@32e10000: access-controllers: [[16, 5]] is not of type 'object'
	from schema $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
arch/arm64/boot/dts/freescale/imx8mn-evk.dtb: mipi-csi@32e30000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dtb: mipi-csi@32e30000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
arch/arm64/boot/dts/freescale/imx8mn-evk.dtb: usb@32e40000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dtb: usb@32e40000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dtb: mipi-csi@32e30000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dtb: dsi@32e10000: access-controllers: [[19, 5]] is not of type 'object'
	from schema $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dtb: mipi-csi@32e30000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dtb: usb@32e40000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
arch/arm64/boot/dts/freescale/imx8mn-evk.dtb: gpu@38000000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dtb: usb@32e40000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dtb: gpu@38000000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dtb: ethernet@30be0000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/net/fsl,fec.yaml#
arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dtb: mipi-csi@32e30000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dtb: gpu@38000000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dtb: gpu@38000000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dtb: usb@32e40000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
arch/arm64/boot/dts/freescale/imx8mn-dimonoff-gateway-evk.dtb: ethernet@30be0000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/net/fsl,fec.yaml#
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dtb: dsi@32e10000: access-controllers: [[16, 5]] is not of type 'object'
	from schema $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dtb: gpu@38000000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-dimonoff-gateway-evk.dtb: dsi@32e10000: access-controllers: [[16, 5]] is not of type 'object'
	from schema $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dtb: mipi-csi@32e30000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dtb: usb@32e40000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
arch/arm64/boot/dts/freescale/imx8mn-dimonoff-gateway-evk.dtb: mipi-csi@32e30000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
arch/arm64/boot/dts/freescale/imx8mn-dimonoff-gateway-evk.dtb: usb@32e40000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dtb: gpu@38000000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-dimonoff-gateway-evk.dtb: gpu@38000000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dtb: ethernet@30be0000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/net/fsl,fec.yaml#
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dtb: dsi@32e10000: access-controllers: [[20, 5]] is not of type 'object'
	from schema $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dtb: mipi-csi@32e30000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dtb: usb@32e40000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dtb: easrc@300c0000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/sound/fsl,easrc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dtb: gpu@38000000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dtb: efuse@30350000: Unevaluated properties are not allowed ('#access-controller-cells' was unexpected)
	from schema $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dtb: ethernet@30be0000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/net/fsl,fec.yaml#
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dtb: dsi@32e10000: access-controllers: [[17, 5]] is not of type 'object'
	from schema $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dtb: mipi-csi@32e30000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dtb: usb@32e40000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dtb: easrc@300c0000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/sound/fsl,easrc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dtb: gpu@38000000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dtb: easrc@300c0000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/sound/fsl,easrc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dtb: efuse@30350000: Unevaluated properties are not allowed ('#access-controller-cells' was unexpected)
	from schema $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dtb: efuse@30350000: Unevaluated properties are not allowed ('#access-controller-cells' was unexpected)
	from schema $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dtb: ethernet@30be0000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/net/fsl,fec.yaml#
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dtb: ethernet@30be0000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/net/fsl,fec.yaml#
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dtb: dsi@32e10000: access-controllers: [[17, 5]] is not of type 'object'
	from schema $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dtb: dsi@32e10000: access-controllers: [[17, 5]] is not of type 'object'
	from schema $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dtb: mipi-csi@32e30000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dtb: usb@32e40000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dtb: mipi-csi@32e30000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dtb: gpu@38000000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dtb: usb@32e40000: Unevaluated properties are not allowed ('access-controllers' was unexpected)
	from schema $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dtb: gpu@38000000: 'access-controllers' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#

Re: [PATCH 3/4] nvmem: imx-ocotp: Support accessing controller for i.MX8M Nano

[Krzysztof Kozlowski]

On 30/01/2025 14:01, Alexander Stein wrote:
> +
> +static int imx_ocotp_grant_access(struct ocotp_priv *priv, struct device_node *parent)
> +{
> +	struct device *dev = priv->dev;
> +
> +	for_each_available_child_of_node_scoped(parent, child) {
> +		struct of_phandle_args args;
> +		u32 id, idx = 0;
> +
> +		while (!of_parse_phandle_with_args(child, "access-controllers",
> +						   "#access-controller-cells",
> +						   idx++, &args)) {
> +			of_node_put(args.np);
> +			if (args.np != dev->of_node)

You are using args.np after dropping the reference.

> +				continue;
> +
> +			/* Only support one cell */
> +			if (args.args_count != 1) {
> +				dev_err(dev, "wrong args count\n");
> +				continue;
> +			}
> +


Best regards,
Krzysztof

Re: [PATCH 3/4] nvmem: imx-ocotp: Support accessing controller for i.MX8M Nano

[Alexander Stein]

Hi,

Am Freitag, 31. Januar 2025, 08:20:40 CET schrieb Krzysztof Kozlowski:
> On 30/01/2025 14:01, Alexander Stein wrote:
> > +
> > +static int imx_ocotp_grant_access(struct ocotp_priv *priv, struct device_node *parent)
> > +{
> > +	struct device *dev = priv->dev;
> > +
> > +	for_each_available_child_of_node_scoped(parent, child) {
> > +		struct of_phandle_args args;
> > +		u32 id, idx = 0;
> > +
> > +		while (!of_parse_phandle_with_args(child, "access-controllers",
> > +						   "#access-controller-cells",
> > +						   idx++, &args)) {
> > +			of_node_put(args.np);
> > +			if (args.np != dev->of_node)
> 
> You are using args.np after dropping the reference.

Indeed, but is it really a problem? The args.np pointer is still the same.
So the comparison is unaffected.

Both branches need to drop the reference, no?
But the following looks awefull as well.
> if (args.np != dev->of_node) {
> 	of_node_put(args.np);
> 	continue;
> }
> of_node_put(args.np);

Best regards,
Alexander

> 
> > +				continue;
> > +
> > +			/* Only support one cell */
> > +			if (args.args_count != 1) {
> > +				dev_err(dev, "wrong args count\n");
> > +				continue;
> > +			}
> > +
> 
> 
> Best regards,
> Krzysztof
> 


-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/

Re: [PATCH 3/4] nvmem: imx-ocotp: Support accessing controller for i.MX8M Nano

[Alexander Stein]

Hi,

Am Donnerstag, 30. Januar 2025, 17:42:32 CET schrieb Frank Li:
> On Thu, Jan 30, 2025 at 02:01:00PM +0100, Alexander Stein wrote:
> > i.MX8M OCOTP supports a specific peripheral or function being fused
> > which means disabled, so
> >  - Introduce disable_fuse for a list of possible fused peripherals.
> >  - Iterate all nodes to check accessing permission. If not
> >    allowed to be accessed, detach the node
> >
> > Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > ---
> >  drivers/nvmem/Kconfig     |   3 ++
> >  drivers/nvmem/imx-ocotp.c | 105 +++++++++++++++++++++++++++++++++++++-
> >  2 files changed, 107 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
> > index 8671b7c974b93..ba5c928cab520 100644
> > --- a/drivers/nvmem/Kconfig
> > +++ b/drivers/nvmem/Kconfig
> > @@ -84,6 +84,9 @@ config NVMEM_IMX_OCOTP
> >  	  This driver can also be built as a module. If so, the module
> >  	  will be called nvmem-imx-ocotp.
> >
> > +	  If built as modules, any other driver relying on this working
> > +	  as access controller also needs to be a module as well.
> > +
> >  config NVMEM_IMX_OCOTP_ELE
> >  	tristate "i.MX On-Chip OTP Controller support"
> >  	depends on ARCH_MXC || COMPILE_TEST
> > diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
> > index c5086a16450ac..e3ea026a37d0d 100644
> > --- a/drivers/nvmem/imx-ocotp.c
> > +++ b/drivers/nvmem/imx-ocotp.c
> > @@ -23,6 +23,7 @@
> >  #include <linux/of.h>
> >  #include <linux/platform_device.h>
> >  #include <linux/slab.h>
> > +#include <dt-bindings/nvmem/fsl,imx8mn-ocotp.h>
> >
> >  #define IMX_OCOTP_OFFSET_B0W0		0x400 /* Offset from base address of the
> >  					       * OTP Bank0 Word0
> > @@ -91,11 +92,20 @@ struct ocotp_ctrl_reg {
> >  	u32 bm_rel_shadows;
> >  };
> >
> > +#define OCOTP_MAX_NUM_GATE_WORDS 4
> > +
> > +struct disable_fuse {
> > +	u32 fuse_addr;
> > +	u32 mask;
> > +};
> > +
> >  struct ocotp_params {
> >  	unsigned int nregs;
> >  	unsigned int bank_address_words;
> >  	void (*set_timing)(struct ocotp_priv *priv);
> >  	struct ocotp_ctrl_reg ctrl;
> > +	u32 num_disables;
> > +	struct disable_fuse *disables;
> >  };
> >
> >  static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags)
> > @@ -552,11 +562,25 @@ static const struct ocotp_params imx8mm_params = {
> >  	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
> >  };
> >
> > +struct disable_fuse imx8mn_disable_fuse[] = {
> > +		[IMX8MN_OCOTP_M7_DISABLE]	= { .fuse_addr = 20, .mask = BIT(8) },
> > +		[IMX8MN_OCOTP_M7_MPU_DISABLE]	= { .fuse_addr = 20, .mask = BIT(9) },
> > +		[IMX8MN_OCOTP_M7_FPU_DISABLE]	= { .fuse_addr = 20, .mask = BIT(10) },
> > +		[IMX8MN_OCOTP_USB_OTG1_DISABLE]	= { .fuse_addr = 20, .mask = BIT(11) },
> > +		[IMX8MN_OCOTP_GPU3D_DISABLE]	= { .fuse_addr = 20, .mask = BIT(24) },
> > +		[IMX8MN_OCOTP_MIPI_DSI_DISABLE]	= { .fuse_addr = 20, .mask = BIT(28) },
> > +		[IMX8MN_OCOTP_ENET_DISABLE]	= { .fuse_addr = 20, .mask = BIT(29) },
> > +		[IMX8MN_OCOTP_MIPI_CSI_DISABLE]	= { .fuse_addr = 20, .mask = BIT(30) },
> > +		[IMX8MN_OCOTP_ASRC_DISABLE]	= { .fuse_addr = 20, .mask = BIT(31) },
> > +};
> 
> Can we direct define IMX8MN_OCOTP_M7_DISABLE as BIT(8), so avoid this
> map data?

This would be possible for imx8mn, but not for imx8mp which uses
multiples fuses for disables. This is an excerpt from imx8mp WIP
> struct disable_fuse imx8mp_disable_fuse[] = {
> 	[IMX8MP_OCOTP_CAN_DISABLE]		= { .fuse_addr = 16, .mask = BIT(28) },
> 	[IMX8MP_OCOTP_CAN_FD_DISABLE]		= { .fuse_addr = 16, .mask = BIT(29) },
> 	[IMX8MP_OCOTP_VPU_VC8000E_DISABLE]	= { .fuse_addr = 16, .mask = BIT(30) },
> 	[IMX8MP_OCOTP_IMG_ISP1_DISABLE]		= { .fuse_addr = 20, .mask = BIT(0) },
> 	[IMX8MP_OCOTP_IMG_ISP2_DISABLE]		= { .fuse_addr = 20, .mask = BIT(1) },
> 	[IMX8MP_OCOTP_IMG_DEWARP_DISABLE]	= { .fuse_addr = 20, .mask = BIT(2) },
> };

Notice the fuse_addr of 16 and 20.

> > +
> >  static const struct ocotp_params imx8mn_params = {
> >  	.nregs = 256,
> >  	.bank_address_words = 0,
> >  	.set_timing = imx_ocotp_set_imx6_timing,
> >  	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
> > +	.num_disables = ARRAY_SIZE(imx8mn_disable_fuse),
> > +	.disables = imx8mn_disable_fuse,
> >  };
> >
> >  static const struct ocotp_params imx8mp_params = {
> > @@ -589,6 +613,81 @@ static void imx_ocotp_fixup_dt_cell_info(struct nvmem_device *nvmem,
> >  	cell->read_post_process = imx_ocotp_cell_pp;
> >  }
> >
> > +static int imx_ocotp_check_access(struct ocotp_priv *priv, u32 id)
> > +{
> > +	u32 addr, mask, ret, val;
> > +
> > +	if (id >= priv->params->num_disables) {
> > +		dev_err(priv->dev, "Index %d too large\n", id);
> > +		return -EACCES;
> > +	}
> > +
> > +	addr = priv->params->disables[id].fuse_addr;
> > +	mask = priv->params->disables[id].mask;
> > +
> > +	ret = imx_ocotp_read(priv, addr, &val, sizeof(val));
> > +	if (ret)
> > +		return ret;
> > +
> > +	dev_dbg(priv->dev, "id:%d addr:%#x mask:0x%08x\n", id, addr, mask);
> > +	/* true means disabled */
> > +	if (val & mask)
> > +		return -EACCES;
> > +
> > +	return 0;
> > +}
> > +
> > +static int imx_ocotp_grant_access(struct ocotp_priv *priv, struct device_node *parent)
> > +{
> > +	struct device *dev = priv->dev;
> > +
> > +	for_each_available_child_of_node_scoped(parent, child) {
> > +		struct of_phandle_args args;
> > +		u32 id, idx = 0;
> > +
> > +		while (!of_parse_phandle_with_args(child, "access-controllers",
> > +						   "#access-controller-cells",
> > +						   idx++, &args)) {
> > +			of_node_put(args.np);
> > +			if (args.np != dev->of_node)
> > +				continue;
> > +
> > +			/* Only support one cell */
> > +			if (args.args_count != 1) {
> > +				dev_err(dev, "wrong args count\n");
> > +				continue;
> > +			}
> > +
> > +			id = args.args[0];
> > +
> > +			dev_dbg(dev, "Checking node: %pOF disable ID: %d\n", child, id);
> > +
> > +			if (imx_ocotp_check_access(priv, id)) {
> > +				of_detach_node(child);
> > +				dev_info(dev, "%pOF: disabled by fuse, device driver will not be probed\n",
> > +					 child);
> > +			}
> > +		}
> > +
> > +		imx_ocotp_grant_access(priv, child);
> > +	}
> > +
> > +	return 0;
> > +}
> 
> Can we have one method to share above code logic to avoid copy-paste to
> every ocotp driver? Anyway, we can improve that later.

I need to check with STM32 implementation. The imx-ocotp-ele might use the
same function as here.

Best regards,
Alexander

> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> 
> 
> > +
> > +static int imx_ocotp_access_control(struct ocotp_priv *priv)
> > +{
> > +	struct device_node *root __free(device_node) = of_find_node_by_path("/");
> > +
> > +	if (!priv->params->disables)
> > +		return 0;
> > +
> > +	if (WARN_ON(!root))
> > +		return -EINVAL;
> > +
> > +	return imx_ocotp_grant_access(priv, root);
> > +}
> > +
> >  static int imx_ocotp_probe(struct platform_device *pdev)
> >  {
> >  	struct device *dev = &pdev->dev;
> > @@ -622,9 +721,13 @@ static int imx_ocotp_probe(struct platform_device *pdev)
> >  	imx_ocotp_clr_err_if_set(priv);
> >  	clk_disable_unprepare(priv->clk);
> >
> > +	platform_set_drvdata(pdev, priv);
> > +
> >  	nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
> > +	if (IS_ERR(nvmem))
> > +		return PTR_ERR(nvmem);
> >
> > -	return PTR_ERR_OR_ZERO(nvmem);
> > +	return imx_ocotp_access_control(priv);
> >  }
> >
> >  static struct platform_driver imx_ocotp_driver = {
> > --
> > 2.34.1
> >
> 


-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/

Re: [PATCH 3/4] nvmem: imx-ocotp: Support accessing controller for i.MX8M Nano

[Krzysztof Kozlowski]

On 31/01/2025 14:50, Alexander Stein wrote:
>>> +
>>> +		while (!of_parse_phandle_with_args(child, "access-controllers",
>>> +						   "#access-controller-cells",
>>> +						   idx++, &args)) {
>>> +			of_node_put(args.np);
>>> +			if (args.np != dev->of_node)
>>
>> You are using args.np after dropping the reference.
> 
> Indeed, but is it really a problem? The args.np pointer is still the same.
> So the comparison is unaffected.
> 
> Both branches need to drop the reference, no?

Ah, indeed, you do not use the reference except pointer comparison. It's
fine, maybe a bit less usual, but as you mentioned other alternative
also does not look good, so fine for me.

> But the following looks awefull as well.
>> if (args.np != dev->of_node) {
>> 	of_node_put(args.np);
>> 	continue;
>> }
>> of_node_put(args.np);
> 
Best regards,
Krzysztof

Re: [PATCH 3/4] nvmem: imx-ocotp: Support accessing controller for i.MX8M Nano

[Frank Li]

On Fri, Jan 31, 2025 at 02:54:06PM +0100, Alexander Stein wrote:
> Hi,
>
> Am Donnerstag, 30. Januar 2025, 17:42:32 CET schrieb Frank Li:
> > On Thu, Jan 30, 2025 at 02:01:00PM +0100, Alexander Stein wrote:
> > > i.MX8M OCOTP supports a specific peripheral or function being fused
> > > which means disabled, so
> > >  - Introduce disable_fuse for a list of possible fused peripherals.
> > >  - Iterate all nodes to check accessing permission. If not
> > >    allowed to be accessed, detach the node
> > >
> > > Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > > ---
> > >  drivers/nvmem/Kconfig     |   3 ++
> > >  drivers/nvmem/imx-ocotp.c | 105 +++++++++++++++++++++++++++++++++++++-
> > >  2 files changed, 107 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
> > > index 8671b7c974b93..ba5c928cab520 100644
> > > --- a/drivers/nvmem/Kconfig
> > > +++ b/drivers/nvmem/Kconfig
> > > @@ -84,6 +84,9 @@ config NVMEM_IMX_OCOTP
> > >  	  This driver can also be built as a module. If so, the module
> > >  	  will be called nvmem-imx-ocotp.
> > >
> > > +	  If built as modules, any other driver relying on this working
> > > +	  as access controller also needs to be a module as well.
> > > +
> > >  config NVMEM_IMX_OCOTP_ELE
> > >  	tristate "i.MX On-Chip OTP Controller support"
> > >  	depends on ARCH_MXC || COMPILE_TEST
> > > diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
> > > index c5086a16450ac..e3ea026a37d0d 100644
> > > --- a/drivers/nvmem/imx-ocotp.c
> > > +++ b/drivers/nvmem/imx-ocotp.c
> > > @@ -23,6 +23,7 @@
> > >  #include <linux/of.h>
> > >  #include <linux/platform_device.h>
> > >  #include <linux/slab.h>
> > > +#include <dt-bindings/nvmem/fsl,imx8mn-ocotp.h>
> > >
> > >  #define IMX_OCOTP_OFFSET_B0W0		0x400 /* Offset from base address of the
> > >  					       * OTP Bank0 Word0
> > > @@ -91,11 +92,20 @@ struct ocotp_ctrl_reg {
> > >  	u32 bm_rel_shadows;
> > >  };
> > >
> > > +#define OCOTP_MAX_NUM_GATE_WORDS 4
> > > +
> > > +struct disable_fuse {
> > > +	u32 fuse_addr;
> > > +	u32 mask;
> > > +};
> > > +
> > >  struct ocotp_params {
> > >  	unsigned int nregs;
> > >  	unsigned int bank_address_words;
> > >  	void (*set_timing)(struct ocotp_priv *priv);
> > >  	struct ocotp_ctrl_reg ctrl;
> > > +	u32 num_disables;
> > > +	struct disable_fuse *disables;
> > >  };
> > >
> > >  static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags)
> > > @@ -552,11 +562,25 @@ static const struct ocotp_params imx8mm_params = {
> > >  	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
> > >  };
> > >
> > > +struct disable_fuse imx8mn_disable_fuse[] = {
> > > +		[IMX8MN_OCOTP_M7_DISABLE]	= { .fuse_addr = 20, .mask = BIT(8) },
> > > +		[IMX8MN_OCOTP_M7_MPU_DISABLE]	= { .fuse_addr = 20, .mask = BIT(9) },
> > > +		[IMX8MN_OCOTP_M7_FPU_DISABLE]	= { .fuse_addr = 20, .mask = BIT(10) },
> > > +		[IMX8MN_OCOTP_USB_OTG1_DISABLE]	= { .fuse_addr = 20, .mask = BIT(11) },
> > > +		[IMX8MN_OCOTP_GPU3D_DISABLE]	= { .fuse_addr = 20, .mask = BIT(24) },
> > > +		[IMX8MN_OCOTP_MIPI_DSI_DISABLE]	= { .fuse_addr = 20, .mask = BIT(28) },
> > > +		[IMX8MN_OCOTP_ENET_DISABLE]	= { .fuse_addr = 20, .mask = BIT(29) },
> > > +		[IMX8MN_OCOTP_MIPI_CSI_DISABLE]	= { .fuse_addr = 20, .mask = BIT(30) },
> > > +		[IMX8MN_OCOTP_ASRC_DISABLE]	= { .fuse_addr = 20, .mask = BIT(31) },
> > > +};
> >
> > Can we direct define IMX8MN_OCOTP_M7_DISABLE as BIT(8), so avoid this
> > map data?
>
> This would be possible for imx8mn, but not for imx8mp which uses
> multiples fuses for disables. This is an excerpt from imx8mp WIP
> > struct disable_fuse imx8mp_disable_fuse[] = {
> > 	[IMX8MP_OCOTP_CAN_DISABLE]		= { .fuse_addr = 16, .mask = BIT(28) },
> > 	[IMX8MP_OCOTP_CAN_FD_DISABLE]		= { .fuse_addr = 16, .mask = BIT(29) },
> > 	[IMX8MP_OCOTP_VPU_VC8000E_DISABLE]	= { .fuse_addr = 16, .mask = BIT(30) },
> > 	[IMX8MP_OCOTP_IMG_ISP1_DISABLE]		= { .fuse_addr = 20, .mask = BIT(0) },
> > 	[IMX8MP_OCOTP_IMG_ISP2_DISABLE]		= { .fuse_addr = 20, .mask = BIT(1) },
> > 	[IMX8MP_OCOTP_IMG_DEWARP_DISABLE]	= { .fuse_addr = 20, .mask = BIT(2) },
> > };
>
> Notice the fuse_addr of 16 and 20.

Yes, I am not sure if it good idea to encode fuse_addr to IMX8MP_OCOTP_CAN_DISABLE

like

#define IMX8MP_OCOTP_CAN_DISABLE  16 << 16 | BIT(28)

So dt-bindings/nvmem/fsl,imx8mn-ocotp.h can be moved to dts directory.

Frank

>
> > > +
> > >  static const struct ocotp_params imx8mn_params = {
> > >  	.nregs = 256,
> > >  	.bank_address_words = 0,
> > >  	.set_timing = imx_ocotp_set_imx6_timing,
> > >  	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
> > > +	.num_disables = ARRAY_SIZE(imx8mn_disable_fuse),
> > > +	.disables = imx8mn_disable_fuse,
> > >  };
> > >
> > >  static const struct ocotp_params imx8mp_params = {
> > > @@ -589,6 +613,81 @@ static void imx_ocotp_fixup_dt_cell_info(struct nvmem_device *nvmem,
> > >  	cell->read_post_process = imx_ocotp_cell_pp;
> > >  }
> > >
> > > +static int imx_ocotp_check_access(struct ocotp_priv *priv, u32 id)
> > > +{
> > > +	u32 addr, mask, ret, val;
> > > +
> > > +	if (id >= priv->params->num_disables) {
> > > +		dev_err(priv->dev, "Index %d too large\n", id);
> > > +		return -EACCES;
> > > +	}
> > > +
> > > +	addr = priv->params->disables[id].fuse_addr;
> > > +	mask = priv->params->disables[id].mask;
> > > +
> > > +	ret = imx_ocotp_read(priv, addr, &val, sizeof(val));
> > > +	if (ret)
> > > +		return ret;
> > > +
> > > +	dev_dbg(priv->dev, "id:%d addr:%#x mask:0x%08x\n", id, addr, mask);
> > > +	/* true means disabled */
> > > +	if (val & mask)
> > > +		return -EACCES;
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +static int imx_ocotp_grant_access(struct ocotp_priv *priv, struct device_node *parent)
> > > +{
> > > +	struct device *dev = priv->dev;
> > > +
> > > +	for_each_available_child_of_node_scoped(parent, child) {
> > > +		struct of_phandle_args args;
> > > +		u32 id, idx = 0;
> > > +
> > > +		while (!of_parse_phandle_with_args(child, "access-controllers",
> > > +						   "#access-controller-cells",
> > > +						   idx++, &args)) {
> > > +			of_node_put(args.np);
> > > +			if (args.np != dev->of_node)
> > > +				continue;
> > > +
> > > +			/* Only support one cell */
> > > +			if (args.args_count != 1) {
> > > +				dev_err(dev, "wrong args count\n");
> > > +				continue;
> > > +			}
> > > +
> > > +			id = args.args[0];
> > > +
> > > +			dev_dbg(dev, "Checking node: %pOF disable ID: %d\n", child, id);
> > > +
> > > +			if (imx_ocotp_check_access(priv, id)) {
> > > +				of_detach_node(child);
> > > +				dev_info(dev, "%pOF: disabled by fuse, device driver will not be probed\n",
> > > +					 child);
> > > +			}
> > > +		}
> > > +
> > > +		imx_ocotp_grant_access(priv, child);
> > > +	}
> > > +
> > > +	return 0;
> > > +}
> >
> > Can we have one method to share above code logic to avoid copy-paste to
> > every ocotp driver? Anyway, we can improve that later.
>
> I need to check with STM32 implementation. The imx-ocotp-ele might use the
> same function as here.
>
> Best regards,
> Alexander
>
> > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> >
> >
> > > +
> > > +static int imx_ocotp_access_control(struct ocotp_priv *priv)
> > > +{
> > > +	struct device_node *root __free(device_node) = of_find_node_by_path("/");
> > > +
> > > +	if (!priv->params->disables)
> > > +		return 0;
> > > +
> > > +	if (WARN_ON(!root))
> > > +		return -EINVAL;
> > > +
> > > +	return imx_ocotp_grant_access(priv, root);
> > > +}
> > > +
> > >  static int imx_ocotp_probe(struct platform_device *pdev)
> > >  {
> > >  	struct device *dev = &pdev->dev;
> > > @@ -622,9 +721,13 @@ static int imx_ocotp_probe(struct platform_device *pdev)
> > >  	imx_ocotp_clr_err_if_set(priv);
> > >  	clk_disable_unprepare(priv->clk);
> > >
> > > +	platform_set_drvdata(pdev, priv);
> > > +
> > >  	nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
> > > +	if (IS_ERR(nvmem))
> > > +		return PTR_ERR(nvmem);
> > >
> > > -	return PTR_ERR_OR_ZERO(nvmem);
> > > +	return imx_ocotp_access_control(priv);
> > >  }
> > >
> > >  static struct platform_driver imx_ocotp_driver = {
> > > --
> > > 2.34.1
> > >
> >
>
>
> --
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> http://www.tq-group.com/
>
>

Re: [PATCH 3/4] nvmem: imx-ocotp: Support accessing controller for i.MX8M Nano

[Alexander Stein]

Am Freitag, 31. Januar 2025, 17:06:23 CET schrieb Frank Li:
> On Fri, Jan 31, 2025 at 02:54:06PM +0100, Alexander Stein wrote:
> > Hi,
> >
> > Am Donnerstag, 30. Januar 2025, 17:42:32 CET schrieb Frank Li:
> > > On Thu, Jan 30, 2025 at 02:01:00PM +0100, Alexander Stein wrote:
> > > > i.MX8M OCOTP supports a specific peripheral or function being fused
> > > > which means disabled, so
> > > >  - Introduce disable_fuse for a list of possible fused peripherals.
> > > >  - Iterate all nodes to check accessing permission. If not
> > > >    allowed to be accessed, detach the node
> > > >
> > > > Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > > > ---
> > > >  drivers/nvmem/Kconfig     |   3 ++
> > > >  drivers/nvmem/imx-ocotp.c | 105 +++++++++++++++++++++++++++++++++++++-
> > > >  2 files changed, 107 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
> > > > index 8671b7c974b93..ba5c928cab520 100644
> > > > --- a/drivers/nvmem/Kconfig
> > > > +++ b/drivers/nvmem/Kconfig
> > > > @@ -84,6 +84,9 @@ config NVMEM_IMX_OCOTP
> > > >  	  This driver can also be built as a module. If so, the module
> > > >  	  will be called nvmem-imx-ocotp.
> > > >
> > > > +	  If built as modules, any other driver relying on this working
> > > > +	  as access controller also needs to be a module as well.
> > > > +
> > > >  config NVMEM_IMX_OCOTP_ELE
> > > >  	tristate "i.MX On-Chip OTP Controller support"
> > > >  	depends on ARCH_MXC || COMPILE_TEST
> > > > diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
> > > > index c5086a16450ac..e3ea026a37d0d 100644
> > > > --- a/drivers/nvmem/imx-ocotp.c
> > > > +++ b/drivers/nvmem/imx-ocotp.c
> > > > @@ -23,6 +23,7 @@
> > > >  #include <linux/of.h>
> > > >  #include <linux/platform_device.h>
> > > >  #include <linux/slab.h>
> > > > +#include <dt-bindings/nvmem/fsl,imx8mn-ocotp.h>
> > > >
> > > >  #define IMX_OCOTP_OFFSET_B0W0		0x400 /* Offset from base address of the
> > > >  					       * OTP Bank0 Word0
> > > > @@ -91,11 +92,20 @@ struct ocotp_ctrl_reg {
> > > >  	u32 bm_rel_shadows;
> > > >  };
> > > >
> > > > +#define OCOTP_MAX_NUM_GATE_WORDS 4
> > > > +
> > > > +struct disable_fuse {
> > > > +	u32 fuse_addr;
> > > > +	u32 mask;
> > > > +};
> > > > +
> > > >  struct ocotp_params {
> > > >  	unsigned int nregs;
> > > >  	unsigned int bank_address_words;
> > > >  	void (*set_timing)(struct ocotp_priv *priv);
> > > >  	struct ocotp_ctrl_reg ctrl;
> > > > +	u32 num_disables;
> > > > +	struct disable_fuse *disables;
> > > >  };
> > > >
> > > >  static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags)
> > > > @@ -552,11 +562,25 @@ static const struct ocotp_params imx8mm_params = {
> > > >  	.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
> > > >  };
> > > >
> > > > +struct disable_fuse imx8mn_disable_fuse[] = {
> > > > +		[IMX8MN_OCOTP_M7_DISABLE]	= { .fuse_addr = 20, .mask = BIT(8) },
> > > > +		[IMX8MN_OCOTP_M7_MPU_DISABLE]	= { .fuse_addr = 20, .mask = BIT(9) },
> > > > +		[IMX8MN_OCOTP_M7_FPU_DISABLE]	= { .fuse_addr = 20, .mask = BIT(10) },
> > > > +		[IMX8MN_OCOTP_USB_OTG1_DISABLE]	= { .fuse_addr = 20, .mask = BIT(11) },
> > > > +		[IMX8MN_OCOTP_GPU3D_DISABLE]	= { .fuse_addr = 20, .mask = BIT(24) },
> > > > +		[IMX8MN_OCOTP_MIPI_DSI_DISABLE]	= { .fuse_addr = 20, .mask = BIT(28) },
> > > > +		[IMX8MN_OCOTP_ENET_DISABLE]	= { .fuse_addr = 20, .mask = BIT(29) },
> > > > +		[IMX8MN_OCOTP_MIPI_CSI_DISABLE]	= { .fuse_addr = 20, .mask = BIT(30) },
> > > > +		[IMX8MN_OCOTP_ASRC_DISABLE]	= { .fuse_addr = 20, .mask = BIT(31) },
> > > > +};
> > >
> > > Can we direct define IMX8MN_OCOTP_M7_DISABLE as BIT(8), so avoid this
> > > map data?
> >
> > This would be possible for imx8mn, but not for imx8mp which uses
> > multiples fuses for disables. This is an excerpt from imx8mp WIP
> > > struct disable_fuse imx8mp_disable_fuse[] = {
> > > 	[IMX8MP_OCOTP_CAN_DISABLE]		= { .fuse_addr = 16, .mask = BIT(28) },
> > > 	[IMX8MP_OCOTP_CAN_FD_DISABLE]		= { .fuse_addr = 16, .mask = BIT(29) },
> > > 	[IMX8MP_OCOTP_VPU_VC8000E_DISABLE]	= { .fuse_addr = 16, .mask = BIT(30) },
> > > 	[IMX8MP_OCOTP_IMG_ISP1_DISABLE]		= { .fuse_addr = 20, .mask = BIT(0) },
> > > 	[IMX8MP_OCOTP_IMG_ISP2_DISABLE]		= { .fuse_addr = 20, .mask = BIT(1) },
> > > 	[IMX8MP_OCOTP_IMG_DEWARP_DISABLE]	= { .fuse_addr = 20, .mask = BIT(2) },
> > > };
> >
> > Notice the fuse_addr of 16 and 20.
> 
> Yes, I am not sure if it good idea to encode fuse_addr to IMX8MP_OCOTP_CAN_DISABLE
> 
> like
> 
> #define IMX8MP_OCOTP_CAN_DISABLE  16 << 16 | BIT(28)
> 
> So dt-bindings/nvmem/fsl,imx8mn-ocotp.h can be moved to dts directory.

Mh, I personally don't like encoding offsets into bits. How about using
> '#access-controller-cells = <2>'
and using the defines like this
> #define IMX8MP_OCOTP_CAN_DISABLE  16 0x10000000

DT stays the same:
> access-controllers = <&ocotp IMX8MP_OCOTP_CAN_DISABLE>;

Note: It seems BIT(x) is not usable in DT.

Best regards,
Alexander
-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/

Re: [PATCH 3/4] nvmem: imx-ocotp: Support accessing controller for i.MX8M Nano

[Frank Li]

On Wed, Feb 05, 2025 at 07:51:23AM +0100, Alexander Stein wrote:
> Am Freitag, 31. Januar 2025, 17:06:23 CET schrieb Frank Li:
> > On Fri, Jan 31, 2025 at 02:54:06PM +0100, Alexander Stein wrote:
> > > Hi,
> > >
> > > Am Donnerstag, 30. Januar 2025, 17:42:32 CET schrieb Frank Li:
> > > > On Thu, Jan 30, 2025 at 02:01:00PM +0100, Alexander Stein wrote:
> > > > > i.MX8M OCOTP supports a specific peripheral or function being fused
> > > > > which means disabled, so
> > > > >  - Introduce disable_fuse for a list of possible fused peripherals.
> > > > >  - Iterate all nodes to check accessing permission. If not
> > > > >    allowed to be accessed, detach the node
> > > > >
> > > > > Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > > > > ---
> > > > >  drivers/nvmem/Kconfig     |   3 ++
> > > > >  drivers/nvmem/imx-ocotp.c | 105 +++++++++++++++++++++++++++++++++++++-
> > > > >  2 files changed, 107 insertions(+), 1 deletion(-)
> > > > >
...
> > > multiples fuses for disables. This is an excerpt from imx8mp WIP
> > > > struct disable_fuse imx8mp_disable_fuse[] = {
> > > > 	[IMX8MP_OCOTP_CAN_DISABLE]		= { .fuse_addr = 16, .mask = BIT(28) },
> > > > 	[IMX8MP_OCOTP_CAN_FD_DISABLE]		= { .fuse_addr = 16, .mask = BIT(29) },
> > > > 	[IMX8MP_OCOTP_VPU_VC8000E_DISABLE]	= { .fuse_addr = 16, .mask = BIT(30) },
> > > > 	[IMX8MP_OCOTP_IMG_ISP1_DISABLE]		= { .fuse_addr = 20, .mask = BIT(0) },
> > > > 	[IMX8MP_OCOTP_IMG_ISP2_DISABLE]		= { .fuse_addr = 20, .mask = BIT(1) },
> > > > 	[IMX8MP_OCOTP_IMG_DEWARP_DISABLE]	= { .fuse_addr = 20, .mask = BIT(2) },
> > > > };
> > >
> > > Notice the fuse_addr of 16 and 20.
> >
> > Yes, I am not sure if it good idea to encode fuse_addr to IMX8MP_OCOTP_CAN_DISABLE
> >
> > like
> >
> > #define IMX8MP_OCOTP_CAN_DISABLE  16 << 16 | BIT(28)
> >
> > So dt-bindings/nvmem/fsl,imx8mn-ocotp.h can be moved to dts directory.
>
> Mh, I personally don't like encoding offsets into bits. How about using
> > '#access-controller-cells = <2>'
> and using the defines like this
> > #define IMX8MP_OCOTP_CAN_DISABLE  16 0x10000000

I think it is good. better told peng fan to align this!

Frank

>
> DT stays the same:
> > access-controllers = <&ocotp IMX8MP_OCOTP_CAN_DISABLE>;
>
> Note: It seems BIT(x) is not usable in DT.
>
> Best regards,
> Alexander
> --
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> http://www.tq-group.com/
>
>

Re: [PATCH 3/4] nvmem: imx-ocotp: Support accessing controller for i.MX8M Nano

[Frank Li]

On Wed, Feb 05, 2025 at 11:43:22AM -0500, Frank Li wrote:
> On Wed, Feb 05, 2025 at 07:51:23AM +0100, Alexander Stein wrote:
> > Am Freitag, 31. Januar 2025, 17:06:23 CET schrieb Frank Li:
> > > On Fri, Jan 31, 2025 at 02:54:06PM +0100, Alexander Stein wrote:
> > > > Hi,
> > > >
> > > > Am Donnerstag, 30. Januar 2025, 17:42:32 CET schrieb Frank Li:
> > > > > On Thu, Jan 30, 2025 at 02:01:00PM +0100, Alexander Stein wrote:
> > > > > > i.MX8M OCOTP supports a specific peripheral or function being fused
> > > > > > which means disabled, so
> > > > > >  - Introduce disable_fuse for a list of possible fused peripherals.
> > > > > >  - Iterate all nodes to check accessing permission. If not
> > > > > >    allowed to be accessed, detach the node
> > > > > >
> > > > > > Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > > > > > ---
> > > > > >  drivers/nvmem/Kconfig     |   3 ++
> > > > > >  drivers/nvmem/imx-ocotp.c | 105 +++++++++++++++++++++++++++++++++++++-
> > > > > >  2 files changed, 107 insertions(+), 1 deletion(-)
> > > > > >
> ...
> > > > multiples fuses for disables. This is an excerpt from imx8mp WIP
> > > > > struct disable_fuse imx8mp_disable_fuse[] = {
> > > > > 	[IMX8MP_OCOTP_CAN_DISABLE]		= { .fuse_addr = 16, .mask = BIT(28) },
> > > > > 	[IMX8MP_OCOTP_CAN_FD_DISABLE]		= { .fuse_addr = 16, .mask = BIT(29) },
> > > > > 	[IMX8MP_OCOTP_VPU_VC8000E_DISABLE]	= { .fuse_addr = 16, .mask = BIT(30) },
> > > > > 	[IMX8MP_OCOTP_IMG_ISP1_DISABLE]		= { .fuse_addr = 20, .mask = BIT(0) },
> > > > > 	[IMX8MP_OCOTP_IMG_ISP2_DISABLE]		= { .fuse_addr = 20, .mask = BIT(1) },
> > > > > 	[IMX8MP_OCOTP_IMG_DEWARP_DISABLE]	= { .fuse_addr = 20, .mask = BIT(2) },
> > > > > };
> > > >
> > > > Notice the fuse_addr of 16 and 20.
> > >
> > > Yes, I am not sure if it good idea to encode fuse_addr to IMX8MP_OCOTP_CAN_DISABLE
> > >
> > > like
> > >
> > > #define IMX8MP_OCOTP_CAN_DISABLE  16 << 16 | BIT(28)
> > >
> > > So dt-bindings/nvmem/fsl,imx8mn-ocotp.h can be moved to dts directory.
> >
> > Mh, I personally don't like encoding offsets into bits. How about using
> > > '#access-controller-cells = <2>'
> > and using the defines like this
> > > #define IMX8MP_OCOTP_CAN_DISABLE  16 0x10000000
>
> I think it is good. better told peng fan to align this!

It'd better use bit offset directly. such as

#define IMX8MP_OCOTP_CAN_DISABLE  16 28

So binding doc easy to limit it to 0..31.

Frank

>
> Frank
>
> >
> > DT stays the same:
> > > access-controllers = <&ocotp IMX8MP_OCOTP_CAN_DISABLE>;
> >
> > Note: It seems BIT(x) is not usable in DT.
> >
> > Best regards,
> > Alexander
> > --
> > TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> > Amtsgericht München, HRB 105018
> > Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> > http://www.tq-group.com/
> >
> >