[PATCH v3 0/7] Add PCIe and USB device-tree support for J722S

[PATCH v3 0/7] Add PCIe and USB device-tree support for J722S

[Siddharth Vadapalli]

Hello,

This series adds device-tree support for PCIe and USB on J722S SoC.
This series is the v3 for the v2 USB series at:
https://lore.kernel.org/r/20240513114443.16350-1-r-gunasekaran@ti.com/
and is also the v1 series for enabling PCIe device-tree support for J722S.

Since the v2 USB series combined portions of the PCIe changes incorrectly,
I have updated this series to contain USB specific changes in the first 3
patches of this series while moving the PCIe specific changes to the
remaining 4 patches in this series.

Series is based on linux-next tagged next-20240524.

v2 for USB:
https://lore.kernel.org/r/20240513114443.16350-1-r-gunasekaran@ti.com/
Changes since v2 USB series:
- For patch 1:
  => Renamed serdes0_ln_ctrl to serdes_ln_ctrl to keep the format
  consistent across SoCs where a single node is sufficient to
  represent the Lane-Muxing for all instances of the Serdes.
- For patch 2:
  => No changes since v2.
- For patch 3:
  => Renamed serdes0_ln_ctrl to serdes_ln_ctrl corresponding to the change
  made in patch 1.
  => Dropped Serdes1 idle-states since it has not yet been added in the
  serdes_ln_ctrl node.
  => Dropped Serdes1 specific Lane-Muxing macros in "k3-serdes.h".
  => Added newline after /* J722S */ in "k3-serdes.h" following the file
  convention.

v1 for USB:
https://lore.kernel.org/r/20240429120932.11456-1-r-gunasekaran@ti.com/
Changes since v1 USB series:
- Introduced k3-j722s-main.dtsi newly to add the main domain
  peripherals that are present additionally in J722S as suggested by
  Andrew Davis.
- Used generic node names as suggested by Roger Quadros.
- Removed the aliases for usb as suggested by Rob Herring.

This series has no dependencies and has been tested on J722S-EVM.
Logs testing PCIe functionality with an NVMe SSD connected to the
J722S-EVM and testing USB functionality limited to "lsusb" output:
https://gist.github.com/Siddharth-Vadapalli-at-TI/6a9cdcec24add0114e63db736b3e23fb

Regards,
Siddharth.

Ravi Gunasekaran (3):
  arm64: dts: ti: k3-j722s-main: Add support for SERDES0
  arm64: dts: ti: k3-j722s-main: Redefine USB1 node description
  arm64: dts: ti: k3-j722s-evm: Update USB0 and USB1

Siddharth Vadapalli (4):
  arm64: dts: ti: k3-serdes: Add Serdes1 lane-muxing macros for J722S
  arm64: dts: ti: k3-j722s: Add lane mux for Serdes1
  arm64: dts: ti: k3-j722s-main: Add WIZ1 and Serdes1 nodes
  arm64: dts: ti: k3-j722s: Add support for PCIe0

 arch/arm64/boot/dts/ti/k3-j722s-evm.dts   |  72 +++++++++
 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 177 ++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j722s.dtsi      |   5 +
 arch/arm64/boot/dts/ti/k3-serdes.h        |   8 +
 4 files changed, 262 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi

-- 
2.40.1

[PATCH v3 1/7] arm64: dts: ti: k3-j722s-main: Add support for SERDES0

[Siddharth Vadapalli]

From: Ravi Gunasekaran <r-gunasekaran@ti.com>

AM62P's DT source files are reused for J722S inorder to
avoid duplication of nodes. But J722S has additional
peripherals that are not present in AM62P.

Introduce a -main.dtsi to define such additional main
domain peripherals and define the SERDES0 node.

Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v2:
https://lore.kernel.org/r/20240513114443.16350-2-r-gunasekaran@ti.com/
Changes since v2:
- Renamed serdes0_ln_ctrl to serdes_ln_ctrl to keep the format
  consistent across SoCs where a single node is sufficient to
  represent the Lane-Muxing for all instances of the Serdes.

v1:
https://lore.kernel.org/r/20240429120932.11456-2-r-gunasekaran@ti.com/
Changes since v1:
- Newly introduced k3-j722s-main.dtsi to add main domain peripherals
  that are additionally present in J722S.
- Used generic node names - renamed "clock-cmnrefclk" to "clk-0",
  "wiz@f000000" to "phy@f000000"

 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 64 +++++++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
new file mode 100644
index 000000000000..0dac8f1e1291
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree file for the J722S main domain peripherals
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+	serdes_refclk: clk-0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+};
+
+&cbass_main {
+	serdes_wiz0: phy@f000000 {
+		compatible = "ti,am64-wiz-10g";
+		ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
+		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+		num-lanes = <1>;
+		#reset-cells = <1>;
+		#clock-cells = <1>;
+
+		assigned-clocks = <&k3_clks 279 1>;
+		assigned-clock-parents = <&k3_clks 279 5>;
+
+		serdes0: serdes@f000000 {
+			compatible = "ti,j721e-serdes-10g";
+			reg = <0x0f000000 0x00010000>;
+			reg-names = "torrent_phy";
+			resets = <&serdes_wiz0 0>;
+			reset-names = "torrent_reset";
+			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+			clock-names = "refclk", "phy_en_refclk";
+			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+			assigned-clock-parents = <&k3_clks 279 1>,
+						 <&k3_clks 279 1>,
+						 <&k3_clks 279 1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#clock-cells = <1>;
+
+			status = "disabled"; /* Needs lane config */
+		};
+	};
+};
+
+&main_conf {
+	serdes_ln_ctrl: mux-controller@4080 {
+		compatible = "reg-mux";
+		reg = <0x4080 0x4>;
+		#mux-control-cells = <1>;
+		mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */
+	};
+};
-- 
2.40.1

[PATCH v3 2/7] arm64: dts: ti: k3-j722s-main: Redefine USB1 node description

[Siddharth Vadapalli]

From: Ravi Gunasekaran <r-gunasekaran@ti.com>

USB1 controller on J722S and AM62P are from different vendors.
Redefine the USB1 node description for J722S by deleting the
node inherited from AM62P dtsi.

Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v2:
https://lore.kernel.org/r/20240513114443.16350-3-r-gunasekaran@ti.com/
No changes since v2.

v1:
https://lore.kernel.org/r/20240429120932.11456-3-r-gunasekaran@ti.com/
Changes since v1:
- The entire node which was added in k3-j722s.dtsi in v1 in now moved to
  k3-j722s-main.dtsi as USB is a main domain peripheral.
- Used generic node names - renamed "cdns-usb@f920000" to "usb@f920000".

 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 39 +++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index 0dac8f1e1291..b069cecebfd9 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -6,6 +6,13 @@
 
 #include <dt-bindings/phy/phy-ti.h>
 
+/*
+ * USB1 controller on AM62P and J722S are of different IP.
+ * Delete AM62P's USBSS1 node definition and redefine it for J722S.
+ */
+
+/delete-node/ &usbss1;
+
 / {
 	serdes_refclk: clk-0 {
 		compatible = "fixed-clock";
@@ -52,6 +59,38 @@ serdes0: serdes@f000000 {
 			status = "disabled"; /* Needs lane config */
 		};
 	};
+
+	usbss1: usb@f920000 {
+		compatible = "ti,j721e-usb";
+		reg = <0x00 0x0f920000 0x00 0x100>;
+		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 278 3>, <&k3_clks 278 1>;
+		clock-names = "ref", "lpm";
+		assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
+		assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+
+		usb1: usb@31200000{
+			compatible = "cdns,usb3";
+			reg = <0x00 0x31200000 0x00 0x10000>,
+			      <0x00 0x31210000 0x00 0x10000>,
+			      <0x00 0x31220000 0x00 0x10000>;
+			reg-names = "otg",
+				    "xhci",
+				    "dev";
+			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
+			interrupt-names = "host",
+					  "peripheral",
+					  "otg";
+			maximum-speed = "super-speed";
+			dr_mode = "otg";
+		};
+	};
 };
 
 &main_conf {
-- 
2.40.1

[PATCH v3 3/7] arm64: dts: ti: k3-j722s-evm: Update USB0 and USB1

[Siddharth Vadapalli]

From: Ravi Gunasekaran <r-gunasekaran@ti.com>

The GPIO expander on the EVM allows the USB selection for Type-C
port to either USB0 or USB1 via USB hub. By default, let the Type-C
port select USB0 via the GPIO expander port P05.

Enable super-speed on USB1 by updating SerDes0 lane configuration.

Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v2:
https://lore.kernel.org/r/20240513114443.16350-4-r-gunasekaran@ti.com/
Changes since v2:
- Renamed serdes0_ln_ctrl to serdes_ln_ctrl corresponding to the change
  made in patch 1.
- Dropped Serdes1 idle-states since it has not yet been added in the
  serdes_ln_ctrl node.
- Dropped Serdes1 specific Lane-Muxing macros in "k3-serdes.h".
- Added newline after /* J722S */ in "k3-serdes.h" following the file
  convention.

v1:
https://lore.kernel.org/r/20240429120932.11456-4-r-gunasekaran@ti.com/
Changes since v1:
- Removed USB aliases, line-name property for p05 GPIO hog.
- Included k3-j722s-main.dtsi.

 arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 54 +++++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j722s.dtsi    |  5 +++
 arch/arm64/boot/dts/ti/k3-serdes.h      |  5 +++
 3 files changed, 64 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index bf3c246d13d1..a3bda39cc223 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -9,7 +9,9 @@
 /dts-v1/;
 
 #include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy.h>
 #include "k3-j722s.dtsi"
+#include "k3-serdes.h"
 
 / {
 	compatible = "ti,j722s-evm", "ti,j722s";
@@ -202,6 +204,12 @@ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */
 			J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
 		>;
 	};
+
+	main_usb1_pins_default: main-usb1-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
+		>;
+	};
 };
 
 &cpsw3g {
@@ -301,6 +309,13 @@ exp1: gpio@23 {
 				  "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
 				  "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
 				  "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
+
+		p05-hog {
+			/* P05 - USB2.0_MUX_SEL */
+			gpio-hog;
+			gpios = <5 GPIO_ACTIVE_LOW>;
+			output-high;
+		};
 	};
 };
 
@@ -384,3 +399,42 @@ &sdhci1 {
 	status = "okay";
 	bootph-all;
 };
+
+&serdes_ln_ctrl {
+	idle-states = <J722S_SERDES0_LANE0_USB>;
+};
+
+&serdes0 {
+	status = "okay";
+	serdes0_usb_link: phy@0 {
+		reg = <0>;
+		cdns,num-lanes = <1>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_USB3>;
+		resets = <&serdes_wiz0 1>;
+	};
+};
+
+&usbss0 {
+	ti,vbus-divider;
+	status = "okay";
+};
+
+&usb0 {
+	dr_mode = "otg";
+	usb-role-switch;
+};
+
+&usbss1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_usb1_pins_default>;
+	ti,vbus-divider;
+	status = "okay";
+};
+
+&usb1 {
+	dr_mode = "host";
+	maximum-speed = "super-speed";
+	phys = <&serdes0_usb_link>;
+	phy-names = "cdns3,usb3-phy";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
index c75744edb143..61b64fae1bf4 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
@@ -87,3 +87,8 @@ &oc_sram {
 	reg = <0x00 0x70000000 0x00 0x40000>;
 	ranges = <0x00 0x00 0x70000000 0x40000>;
 };
+
+/* Include bus peripherals that are additionally
+ * present in J722S
+ */
+ #include "k3-j722s-main.dtsi"
diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
index a011ad893b44..e6a036a4e70b 100644
--- a/arch/arm64/boot/dts/ti/k3-serdes.h
+++ b/arch/arm64/boot/dts/ti/k3-serdes.h
@@ -201,4 +201,9 @@
 #define J784S4_SERDES4_LANE3_USB		0x2
 #define J784S4_SERDES4_LANE3_IP4_UNUSED		0x3
 
+/* J722S */
+
+#define J722S_SERDES0_LANE0_USB			0x0
+#define J722S_SERDES0_LANE0_QSGMII_LANE2	0x1
+
 #endif /* DTS_ARM64_TI_K3_SERDES_H */
-- 
2.40.1

[PATCH v3 4/7] arm64: dts: ti: k3-serdes: Add Serdes1 lane-muxing macros for J722S

[Siddharth Vadapalli]

The Serdes1 instance of the Serdes on J722S SoC is a single lane Serdes
that is muxed across PCIe and CPSW. Define the lane-muxing macros to be
used as the idle state values.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Current patch is v1. No changelog.

 arch/arm64/boot/dts/ti/k3-serdes.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
index e6a036a4e70b..ef3606068140 100644
--- a/arch/arm64/boot/dts/ti/k3-serdes.h
+++ b/arch/arm64/boot/dts/ti/k3-serdes.h
@@ -206,4 +206,7 @@
 #define J722S_SERDES0_LANE0_USB			0x0
 #define J722S_SERDES0_LANE0_QSGMII_LANE2	0x1
 
+#define J722S_SERDES1_LANE0_PCIE0_LANE0		0x0
+#define J722S_SERDES1_LANE0_QSGMII_LANE1	0x1
+
 #endif /* DTS_ARM64_TI_K3_SERDES_H */
-- 
2.40.1

[PATCH v3 5/7] arm64: dts: ti: k3-j722s: Add lane mux for Serdes1

[Siddharth Vadapalli]

The Serdes1 instance of Serdes on J722S SoC can be muxed between PCIe0
and SGMII1. Update the "serdes_ln_ctrl" node adding support for the lane
mux of Serdes1. Additionally, set the default muxing for Serdes1 Lane0 to
PCIe0.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Current patch is v1. No changelog.

 arch/arm64/boot/dts/ti/k3-j722s-evm.dts   | 3 ++-
 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 5 +++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index a3bda39cc223..16c6ab8ee07e 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -401,7 +401,8 @@ &sdhci1 {
 };
 
 &serdes_ln_ctrl {
-	idle-states = <J722S_SERDES0_LANE0_USB>;
+	idle-states = <J722S_SERDES0_LANE0_USB>,
+		      <J722S_SERDES1_LANE0_PCIE0_LANE0>;
 };
 
 &serdes0 {
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index b069cecebfd9..48b77e476c77 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -96,8 +96,9 @@ usb1: usb@31200000{
 &main_conf {
 	serdes_ln_ctrl: mux-controller@4080 {
 		compatible = "reg-mux";
-		reg = <0x4080 0x4>;
+		reg = <0x4080 0x14>;
 		#mux-control-cells = <1>;
-		mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */
+		mux-reg-masks = <0x0 0x3>, /* SERDES0 lane0 select */
+				<0x10 0x3>; /* SERDES1 lane0 select */
 	};
 };
-- 
2.40.1

[PATCH v3 6/7] arm64: dts: ti: k3-j722s-main: Add WIZ1 and Serdes1 nodes

[Siddharth Vadapalli]

The Serdes1 instance of Serdes on TI's J722S SoC is a 1 Lane Serdes with
the WIZ1 instance of the WIZ wrapper used for configuring the Serdes.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Current patch is v1. No changelog.

 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 36 +++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index 48b77e476c77..19a7e8413ad2 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -60,6 +60,42 @@ serdes0: serdes@f000000 {
 		};
 	};
 
+	serdes_wiz1: phy@f010000 {
+		compatible = "ti,am64-wiz-10g";
+		ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
+		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+		num-lanes = <1>;
+		#reset-cells = <1>;
+		#clock-cells = <1>;
+
+		assigned-clocks = <&k3_clks 280 1>;
+		assigned-clock-parents = <&k3_clks 280 5>;
+
+		serdes1: serdes@f010000 {
+			compatible = "ti,j721e-serdes-10g";
+			reg = <0x0f010000 0x00010000>;
+			reg-names = "torrent_phy";
+			resets = <&serdes_wiz1 0>;
+			reset-names = "torrent_reset";
+			clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
+			clock-names = "refclk", "phy_en_refclk";
+			assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+					  <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
+					  <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
+			assigned-clock-parents = <&k3_clks 280 1>,
+						 <&k3_clks 280 1>,
+						 <&k3_clks 280 1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#clock-cells = <1>;
+		};
+	};
+
 	usbss1: usb@f920000 {
 		compatible = "ti,j721e-usb";
 		reg = <0x00 0x0f920000 0x00 0x100>;
-- 
2.40.1

[PATCH v3 7/7] arm64: dts: ti: k3-j722s: Add support for PCIe0

[Siddharth Vadapalli]

The PCIe0 instance of PCIe on TI's J722S SoC is a Gen3 single lane PCIe
controller. Add the device-tree nodes for it and enable it in Root Complex
mode of operation using Lane 0 of the Serdes1 instance of Serdes.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Current patch is v1. No changelog.

 arch/arm64/boot/dts/ti/k3-j722s-evm.dts   | 17 +++++++++++
 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 37 +++++++++++++++++++++++
 2 files changed, 54 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index 16c6ab8ee07e..d2d7de5cfe27 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -416,6 +416,16 @@ serdes0_usb_link: phy@0 {
 	};
 };
 
+&serdes1 {
+	serdes1_pcie_link: phy@0 {
+		reg = <0>;
+		cdns,num-lanes = <1>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_PCIE>;
+		resets = <&serdes_wiz1 1>;
+	};
+};
+
 &usbss0 {
 	ti,vbus-divider;
 	status = "okay";
@@ -439,3 +449,10 @@ &usb1 {
 	phys = <&serdes0_usb_link>;
 	phy-names = "cdns3,usb3-phy";
 };
+
+&pcie0_rc {
+	status = "okay";
+	reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>;
+	phys = <&serdes1_pcie_link>;
+	phy-names = "pcie-phy";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index 19a7e8413ad2..0b32893eb75e 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -4,6 +4,7 @@
  * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#include <dt-bindings/phy/phy-cadence.h>
 #include <dt-bindings/phy/phy-ti.h>
 
 /*
@@ -96,6 +97,35 @@ serdes1: serdes@f010000 {
 		};
 	};
 
+	pcie0_rc: pcie@f102000 {
+		compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
+		reg = <0x00 0x0f102000 0x00 0x1000>,
+		      <0x00 0x0f100000 0x00 0x400>,
+		      <0x00 0x0d000000 0x00 0x00800000>,
+		      <0x00 0x68000000 0x00 0x00001000>;
+		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+		ranges = <0x01000000 0x00 0x68001000  0x00 0x68001000  0x00 0x0010000>,
+			 <0x02000000 0x00 0x68011000  0x00 0x68011000  0x00 0x7fef000>;
+		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+		interrupt-names = "link_state";
+		interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
+		device_type = "pci";
+		max-link-speed = <3>;
+		num-lanes = <1>;
+		power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
+		clock-names = "fck", "pcie_refclk";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		bus-range = <0x0 0xff>;
+		vendor-id = <0x104c>;
+		device-id = <0xb010>;
+		cdns,no-bar-match-nbits = <64>;
+		ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+		msi-map = <0x0 &gic_its 0x0 0x10000>;
+		status = "disabled";
+	};
+
 	usbss1: usb@f920000 {
 		compatible = "ti,j721e-usb";
 		reg = <0x00 0x0f920000 0x00 0x100>;
@@ -138,3 +168,10 @@ serdes_ln_ctrl: mux-controller@4080 {
 				<0x10 0x3>; /* SERDES1 lane0 select */
 	};
 };
+
+&wkup_conf {
+	pcie0_ctrl: pcie0-ctrl@4070 {
+		compatible = "ti,j784s4-pcie-ctrl", "syscon";
+		reg = <0x4070 0x4>;
+	};
+};
-- 
2.40.1

Re: [PATCH v3 1/7] arm64: dts: ti: k3-j722s-main: Add support for SERDES0

[Roger Quadros]

On 24/05/2024 12:05, Siddharth Vadapalli wrote:
> From: Ravi Gunasekaran <r-gunasekaran@ti.com>
> 
> AM62P's DT source files are reused for J722S inorder to

inorder/in order

> avoid duplication of nodes. But J722S has additional
> peripherals that are not present in AM62P.
> 
> Introduce a -main.dtsi to define such additional main
> domain peripherals and define the SERDES0 node.
> 
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> v2:
> https://lore.kernel.org/r/20240513114443.16350-2-r-gunasekaran@ti.com/
> Changes since v2:
> - Renamed serdes0_ln_ctrl to serdes_ln_ctrl to keep the format
>   consistent across SoCs where a single node is sufficient to
>   represent the Lane-Muxing for all instances of the Serdes.
> 
> v1:
> https://lore.kernel.org/r/20240429120932.11456-2-r-gunasekaran@ti.com/
> Changes since v1:
> - Newly introduced k3-j722s-main.dtsi to add main domain peripherals
>   that are additionally present in J722S.
> - Used generic node names - renamed "clock-cmnrefclk" to "clk-0",
>   "wiz@f000000" to "phy@f000000"
> 
>  arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 64 +++++++++++++++++++++++
>  1 file changed, 64 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> new file mode 100644
> index 000000000000..0dac8f1e1291
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> @@ -0,0 +1,64 @@
> +// SPDX-License-Identifier: GPL-2.0-only OR MIT
> +/*
> + * Device Tree file for the J722S main domain peripherals
> + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#include <dt-bindings/phy/phy-ti.h>
> +
> +/ {
> +	serdes_refclk: clk-0 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <0>;
> +	};
> +};
> +
> +&cbass_main {
> +	serdes_wiz0: phy@f000000 {
> +		compatible = "ti,am64-wiz-10g";
> +		ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
> +		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
> +		num-lanes = <1>;
> +		#reset-cells = <1>;
> +		#clock-cells = <1>;
> +
> +		assigned-clocks = <&k3_clks 279 1>;
> +		assigned-clock-parents = <&k3_clks 279 5>;
> +
> +		serdes0: serdes@f000000 {
> +			compatible = "ti,j721e-serdes-10g";
> +			reg = <0x0f000000 0x00010000>;
> +			reg-names = "torrent_phy";
> +			resets = <&serdes_wiz0 0>;
> +			reset-names = "torrent_reset";
> +			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> +				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
> +			clock-names = "refclk", "phy_en_refclk";
> +			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> +					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
> +					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
> +			assigned-clock-parents = <&k3_clks 279 1>,
> +						 <&k3_clks 279 1>,
> +						 <&k3_clks 279 1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			#clock-cells = <1>;
> +
> +			status = "disabled"; /* Needs lane config */
> +		};
> +	};
> +};
> +
> +&main_conf {
> +	serdes_ln_ctrl: mux-controller@4080 {
> +		compatible = "reg-mux";
> +		reg = <0x4080 0x4>;
> +		#mux-control-cells = <1>;
> +		mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */
> +	};
> +};

-- 
cheers,
-roger

Re: [PATCH v3 2/7] arm64: dts: ti: k3-j722s-main: Redefine USB1 node description

[Roger Quadros]

On 24/05/2024 12:05, Siddharth Vadapalli wrote:
> From: Ravi Gunasekaran <r-gunasekaran@ti.com>
> 
> USB1 controller on J722S and AM62P are from different vendors.
> Redefine the USB1 node description for J722S by deleting the
> node inherited from AM62P dtsi.
> 
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> v2:
> https://lore.kernel.org/r/20240513114443.16350-3-r-gunasekaran@ti.com/
> No changes since v2.
> 
> v1:
> https://lore.kernel.org/r/20240429120932.11456-3-r-gunasekaran@ti.com/
> Changes since v1:
> - The entire node which was added in k3-j722s.dtsi in v1 in now moved to
>   k3-j722s-main.dtsi as USB is a main domain peripheral.
> - Used generic node names - renamed "cdns-usb@f920000" to "usb@f920000".
> 
>  arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 39 +++++++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> index 0dac8f1e1291..b069cecebfd9 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> @@ -6,6 +6,13 @@
>  
>  #include <dt-bindings/phy/phy-ti.h>
>  
> +/*
> + * USB1 controller on AM62P and J722S are of different IP.
> + * Delete AM62P's USBSS1 node definition and redefine it for J722S.
> + */
> +
> +/delete-node/ &usbss1;
> +

This is odd and indicates issues with current DT file inclusion.
We need to split out the non common IPs (e.g. USB) out of the common k3-am62p-main.dtsi file Maybe call it k3-am62-main-common.dtsi.
Only keep am62p specific stuff in k3-am62p-main.dtsi.

Include k3-am62-main-common.dtsi and k3-am62p-main.dtsi for AM62P
Include k3-am62-main-common.dtsi and k3-j722s-main.dtsi for J722S

This way you don't need to call /delete-node/

>  / {
>  	serdes_refclk: clk-0 {
>  		compatible = "fixed-clock";
> @@ -52,6 +59,38 @@ serdes0: serdes@f000000 {
>  			status = "disabled"; /* Needs lane config */
>  		};
>  	};
> +
> +	usbss1: usb@f920000 {
> +		compatible = "ti,j721e-usb";
> +		reg = <0x00 0x0f920000 0x00 0x100>;
> +		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&k3_clks 278 3>, <&k3_clks 278 1>;
> +		clock-names = "ref", "lpm";
> +		assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
> +		assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		status = "disabled";
> +
> +		usb1: usb@31200000{
> +			compatible = "cdns,usb3";
> +			reg = <0x00 0x31200000 0x00 0x10000>,
> +			      <0x00 0x31210000 0x00 0x10000>,
> +			      <0x00 0x31220000 0x00 0x10000>;
> +			reg-names = "otg",
> +				    "xhci",
> +				    "dev";
> +			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
> +				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
> +				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
> +			interrupt-names = "host",
> +					  "peripheral",
> +					  "otg";
> +			maximum-speed = "super-speed";
> +			dr_mode = "otg";
> +		};
> +	};
>  };
>  
>  &main_conf {

-- 
cheers,
-roger

Re: [PATCH v3 3/7] arm64: dts: ti: k3-j722s-evm: Update USB0 and USB1

[Roger Quadros]

On 24/05/2024 12:05, Siddharth Vadapalli wrote:
> From: Ravi Gunasekaran <r-gunasekaran@ti.com>
> 
> The GPIO expander on the EVM allows the USB selection for Type-C
> port to either USB0 or USB1 via USB hub. By default, let the Type-C
> port select USB0 via the GPIO expander port P05.
> 
> Enable super-speed on USB1 by updating SerDes0 lane configuration.
> 
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> v2:
> https://lore.kernel.org/r/20240513114443.16350-4-r-gunasekaran@ti.com/
> Changes since v2:
> - Renamed serdes0_ln_ctrl to serdes_ln_ctrl corresponding to the change
>   made in patch 1.
> - Dropped Serdes1 idle-states since it has not yet been added in the
>   serdes_ln_ctrl node.
> - Dropped Serdes1 specific Lane-Muxing macros in "k3-serdes.h".
> - Added newline after /* J722S */ in "k3-serdes.h" following the file
>   convention.
> 
> v1:
> https://lore.kernel.org/r/20240429120932.11456-4-r-gunasekaran@ti.com/
> Changes since v1:
> - Removed USB aliases, line-name property for p05 GPIO hog.
> - Included k3-j722s-main.dtsi.
> 
>  arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 54 +++++++++++++++++++++++++
>  arch/arm64/boot/dts/ti/k3-j722s.dtsi    |  5 +++
>  arch/arm64/boot/dts/ti/k3-serdes.h      |  5 +++
>  3 files changed, 64 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> index bf3c246d13d1..a3bda39cc223 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> @@ -9,7 +9,9 @@
>  /dts-v1/;
>  
>  #include <dt-bindings/net/ti-dp83867.h>
> +#include <dt-bindings/phy/phy.h>
>  #include "k3-j722s.dtsi"
> +#include "k3-serdes.h"
>  
>  / {
>  	compatible = "ti,j722s-evm", "ti,j722s";
> @@ -202,6 +204,12 @@ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */
>  			J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
>  		>;
>  	};
> +
> +	main_usb1_pins_default: main-usb1-default-pins {
> +		pinctrl-single,pins = <
> +			J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
> +		>;
> +	};
>  };
>  
>  &cpsw3g {
> @@ -301,6 +309,13 @@ exp1: gpio@23 {
>  				  "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
>  				  "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
>  				  "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
> +
> +		p05-hog {
> +			/* P05 - USB2.0_MUX_SEL */
> +			gpio-hog;
> +			gpios = <5 GPIO_ACTIVE_LOW>;
> +			output-high;
> +		};
>  	};
>  };
>  
> @@ -384,3 +399,42 @@ &sdhci1 {
>  	status = "okay";
>  	bootph-all;
>  };
> +
> +&serdes_ln_ctrl {
> +	idle-states = <J722S_SERDES0_LANE0_USB>;
> +};
> +
> +&serdes0 {
> +	status = "okay";
> +	serdes0_usb_link: phy@0 {
> +		reg = <0>;
> +		cdns,num-lanes = <1>;
> +		#phy-cells = <0>;
> +		cdns,phy-type = <PHY_TYPE_USB3>;
> +		resets = <&serdes_wiz0 1>;
> +	};
> +};
> +
> +&usbss0 {
> +	ti,vbus-divider;
> +	status = "okay";
> +};
> +
> +&usb0 {
> +	dr_mode = "otg";
> +	usb-role-switch;
> +};
> +
> +&usbss1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&main_usb1_pins_default>;
> +	ti,vbus-divider;
> +	status = "okay";
> +};
> +
> +&usb1 {
> +	dr_mode = "host";
> +	maximum-speed = "super-speed";
> +	phys = <&serdes0_usb_link>;
> +	phy-names = "cdns3,usb3-phy";
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> index c75744edb143..61b64fae1bf4 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> @@ -87,3 +87,8 @@ &oc_sram {
>  	reg = <0x00 0x70000000 0x00 0x40000>;
>  	ranges = <0x00 0x00 0x70000000 0x40000>;
>  };
> +
> +/* Include bus peripherals that are additionally
> + * present in J722S
> + */
> + #include "k3-j722s-main.dtsi"
> diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h

The k3-serdes.h changes should be in a separate independent patch.

> index a011ad893b44..e6a036a4e70b 100644
> --- a/arch/arm64/boot/dts/ti/k3-serdes.h
> +++ b/arch/arm64/boot/dts/ti/k3-serdes.h
> @@ -201,4 +201,9 @@
>  #define J784S4_SERDES4_LANE3_USB		0x2
>  #define J784S4_SERDES4_LANE3_IP4_UNUSED		0x3
>  
> +/* J722S */
> +
> +#define J722S_SERDES0_LANE0_USB			0x0
> +#define J722S_SERDES0_LANE0_QSGMII_LANE2	0x1
> +
>  #endif /* DTS_ARM64_TI_K3_SERDES_H */

-- 
cheers,
-roger

Re: [PATCH v3 4/7] arm64: dts: ti: k3-serdes: Add Serdes1 lane-muxing macros for J722S

[Roger Quadros]

On 24/05/2024 12:05, Siddharth Vadapalli wrote:
> The Serdes1 instance of the Serdes on J722S SoC is a single lane Serdes
> that is muxed across PCIe and CPSW. Define the lane-muxing macros to be
> used as the idle state values.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> Current patch is v1. No changelog.
> 
>  arch/arm64/boot/dts/ti/k3-serdes.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
> index e6a036a4e70b..ef3606068140 100644
> --- a/arch/arm64/boot/dts/ti/k3-serdes.h
> +++ b/arch/arm64/boot/dts/ti/k3-serdes.h
> @@ -206,4 +206,7 @@
>  #define J722S_SERDES0_LANE0_USB			0x0
>  #define J722S_SERDES0_LANE0_QSGMII_LANE2	0x1
>  
> +#define J722S_SERDES1_LANE0_PCIE0_LANE0		0x0
> +#define J722S_SERDES1_LANE0_QSGMII_LANE1	0x1
> +

Maybe this one patch can deal with both USB and PCIE0 additions to this file
and could be moved earlier in the series.

>  #endif /* DTS_ARM64_TI_K3_SERDES_H */

-- 
cheers,
-roger

Re: [PATCH v3 5/7] arm64: dts: ti: k3-j722s: Add lane mux for Serdes1

[Roger Quadros]

On 24/05/2024 12:05, Siddharth Vadapalli wrote:
> The Serdes1 instance of Serdes on J722S SoC can be muxed between PCIe0

Please use SERDES insted of Serdes or serdes as it is an abbreviation.

> and SGMII1. Update the "serdes_ln_ctrl" node adding support for the lane
> mux of Serdes1. Additionally, set the default muxing for Serdes1 Lane0 to
> PCIe0.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> Current patch is v1. No changelog.
> 
>  arch/arm64/boot/dts/ti/k3-j722s-evm.dts   | 3 ++-
>  arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 5 +++--
>  2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> index a3bda39cc223..16c6ab8ee07e 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> @@ -401,7 +401,8 @@ &sdhci1 {
>  };
>  
>  &serdes_ln_ctrl {
> -	idle-states = <J722S_SERDES0_LANE0_USB>;
> +	idle-states = <J722S_SERDES0_LANE0_USB>,
> +		      <J722S_SERDES1_LANE0_PCIE0_LANE0>;
>  };
>  
>  &serdes0 {
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> index b069cecebfd9..48b77e476c77 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> @@ -96,8 +96,9 @@ usb1: usb@31200000{
>  &main_conf {
>  	serdes_ln_ctrl: mux-controller@4080 {
>  		compatible = "reg-mux";
> -		reg = <0x4080 0x4>;
> +		reg = <0x4080 0x14>;
>  		#mux-control-cells = <1>;
> -		mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */
> +		mux-reg-masks = <0x0 0x3>, /* SERDES0 lane0 select */
> +				<0x10 0x3>; /* SERDES1 lane0 select */

Why not introduce this right in the patch where you add serdes_ln_ctrl mux node?

>  	};
>  };

-- 
cheers,
-roger

Re: [PATCH v3 6/7] arm64: dts: ti: k3-j722s-main: Add WIZ1 and Serdes1 nodes

[Roger Quadros]

On 24/05/2024 12:05, Siddharth Vadapalli wrote:
> The Serdes1 instance of Serdes on TI's J722S SoC is a 1 Lane Serdes with
> the WIZ1 instance of the WIZ wrapper used for configuring the Serdes.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> Current patch is v1. No changelog.
> 
>  arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 36 +++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> index 48b77e476c77..19a7e8413ad2 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> @@ -60,6 +60,42 @@ serdes0: serdes@f000000 {
>  		};
>  	};
>  
> +	serdes_wiz1: phy@f010000 {
> +		compatible = "ti,am64-wiz-10g";
> +		ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
> +		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
> +		num-lanes = <1>;
> +		#reset-cells = <1>;
> +		#clock-cells = <1>;
> +
> +		assigned-clocks = <&k3_clks 280 1>;
> +		assigned-clock-parents = <&k3_clks 280 5>;
> +
> +		serdes1: serdes@f010000 {
> +			compatible = "ti,j721e-serdes-10g";
> +			reg = <0x0f010000 0x00010000>;
> +			reg-names = "torrent_phy";
> +			resets = <&serdes_wiz1 0>;
> +			reset-names = "torrent_reset";
> +			clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
> +				 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
> +			clock-names = "refclk", "phy_en_refclk";
> +			assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
> +					  <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
> +					  <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
> +			assigned-clock-parents = <&k3_clks 280 1>,
> +						 <&k3_clks 280 1>,
> +						 <&k3_clks 280 1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			#clock-cells = <1>;
> +		};
> +	};
> +

Any particular reason to split addition of various nodes in the k3-j722s-main file?
I think all k3-j722s-main.dtsi additions can be in one patch.

>  	usbss1: usb@f920000 {
>  		compatible = "ti,j721e-usb";
>  		reg = <0x00 0x0f920000 0x00 0x100>;

-- 
cheers,
-roger

Re: [PATCH v3 7/7] arm64: dts: ti: k3-j722s: Add support for PCIe0

[Roger Quadros]

On 24/05/2024 12:05, Siddharth Vadapalli wrote:
> The PCIe0 instance of PCIe on TI's J722S SoC is a Gen3 single lane PCIe
> controller. Add the device-tree nodes for it and enable it in Root Complex
> mode of operation using Lane 0 of the Serdes1 instance of Serdes.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> Current patch is v1. No changelog.
> 
>  arch/arm64/boot/dts/ti/k3-j722s-evm.dts   | 17 +++++++++++
>  arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 37 +++++++++++++++++++++++
>  2 files changed, 54 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> index 16c6ab8ee07e..d2d7de5cfe27 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> @@ -416,6 +416,16 @@ serdes0_usb_link: phy@0 {
>  	};
>  };
>  
> +&serdes1 {
> +	serdes1_pcie_link: phy@0 {
> +		reg = <0>;
> +		cdns,num-lanes = <1>;
> +		#phy-cells = <0>;
> +		cdns,phy-type = <PHY_TYPE_PCIE>;
> +		resets = <&serdes_wiz1 1>;
> +	};
> +};
> +
>  &usbss0 {
>  	ti,vbus-divider;
>  	status = "okay";
> @@ -439,3 +449,10 @@ &usb1 {
>  	phys = <&serdes0_usb_link>;
>  	phy-names = "cdns3,usb3-phy";
>  };
> +
> +&pcie0_rc {
> +	status = "okay";
> +	reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>;
> +	phys = <&serdes1_pcie_link>;
> +	phy-names = "pcie-phy";
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> index 19a7e8413ad2..0b32893eb75e 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> @@ -4,6 +4,7 @@
>   * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
>   */
>  
> +#include <dt-bindings/phy/phy-cadence.h>
>  #include <dt-bindings/phy/phy-ti.h>
>  
>  /*
> @@ -96,6 +97,35 @@ serdes1: serdes@f010000 {
>  		};
>  	};
>  
> +	pcie0_rc: pcie@f102000 {

Please split PCIe node addition in  to separate patch. hopefully you can squash it with patches that
add USB, SERDES0 and SERDES1 to k3-j722s-main.dtsi.


> +		compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
> +		reg = <0x00 0x0f102000 0x00 0x1000>,
> +		      <0x00 0x0f100000 0x00 0x400>,
> +		      <0x00 0x0d000000 0x00 0x00800000>,
> +		      <0x00 0x68000000 0x00 0x00001000>;
> +		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
> +		ranges = <0x01000000 0x00 0x68001000  0x00 0x68001000  0x00 0x0010000>,
> +			 <0x02000000 0x00 0x68011000  0x00 0x68011000  0x00 0x7fef000>;
> +		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
> +		interrupt-names = "link_state";
> +		interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
> +		device_type = "pci";
> +		max-link-speed = <3>;
> +		num-lanes = <1>;
> +		power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
> +		clock-names = "fck", "pcie_refclk";
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		bus-range = <0x0 0xff>;
> +		vendor-id = <0x104c>;
> +		device-id = <0xb010>;
> +		cdns,no-bar-match-nbits = <64>;
> +		ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
> +		msi-map = <0x0 &gic_its 0x0 0x10000>;
> +		status = "disabled";
> +	};
> +
>  	usbss1: usb@f920000 {
>  		compatible = "ti,j721e-usb";
>  		reg = <0x00 0x0f920000 0x00 0x100>;
> @@ -138,3 +168,10 @@ serdes_ln_ctrl: mux-controller@4080 {
>  				<0x10 0x3>; /* SERDES1 lane0 select */
>  	};
>  };
> +
> +&wkup_conf {
> +	pcie0_ctrl: pcie0-ctrl@4070 {
> +		compatible = "ti,j784s4-pcie-ctrl", "syscon";
> +		reg = <0x4070 0x4>;
> +	};
> +};

-- 
cheers,
-roger

Re: [PATCH v3 1/7] arm64: dts: ti: k3-j722s-main: Add support for SERDES0

[Siddharth Vadapalli]

On Tue, May 28, 2024 at 03:09:41PM +0300, Roger Quadros wrote:
> 
> 
> On 24/05/2024 12:05, Siddharth Vadapalli wrote:
> > From: Ravi Gunasekaran <r-gunasekaran@ti.com>
> > 
> > AM62P's DT source files are reused for J722S inorder to
> 
> inorder/in order

Will fix in v4.

Regards,
Siddharth.

Re: [PATCH v3 2/7] arm64: dts: ti: k3-j722s-main: Redefine USB1 node description

[Siddharth Vadapalli]

On Tue, May 28, 2024 at 03:15:53PM +0300, Roger Quadros wrote:
> 
> 
> On 24/05/2024 12:05, Siddharth Vadapalli wrote:
> > From: Ravi Gunasekaran <r-gunasekaran@ti.com>
> > 
> > USB1 controller on J722S and AM62P are from different vendors.
> > Redefine the USB1 node description for J722S by deleting the
> > node inherited from AM62P dtsi.
> > 
> > Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > ---
> > v2:
> > https://lore.kernel.org/r/20240513114443.16350-3-r-gunasekaran@ti.com/
> > No changes since v2.
> > 
> > v1:
> > https://lore.kernel.org/r/20240429120932.11456-3-r-gunasekaran@ti.com/
> > Changes since v1:
> > - The entire node which was added in k3-j722s.dtsi in v1 in now moved to
> >   k3-j722s-main.dtsi as USB is a main domain peripheral.
> > - Used generic node names - renamed "cdns-usb@f920000" to "usb@f920000".
> > 
> >  arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 39 +++++++++++++++++++++++
> >  1 file changed, 39 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> > index 0dac8f1e1291..b069cecebfd9 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> > @@ -6,6 +6,13 @@
> >  
> >  #include <dt-bindings/phy/phy-ti.h>
> >  
> > +/*
> > + * USB1 controller on AM62P and J722S are of different IP.
> > + * Delete AM62P's USBSS1 node definition and redefine it for J722S.
> > + */
> > +
> > +/delete-node/ &usbss1;
> > +
> 
> This is odd and indicates issues with current DT file inclusion.
> We need to split out the non common IPs (e.g. USB) out of the common k3-am62p-main.dtsi file Maybe call it k3-am62-main-common.dtsi.
> Only keep am62p specific stuff in k3-am62p-main.dtsi.
> 
> Include k3-am62-main-common.dtsi and k3-am62p-main.dtsi for AM62P
> Include k3-am62-main-common.dtsi and k3-j722s-main.dtsi for J722S
> 
> This way you don't need to call /delete-node/

Ok. I will move the common nodes between k3-am62p-main.dtsi and
k3-j722s-main.dtsi to "k3-am62p-j722s-common.dtsi".

Regards,
Siddharth.

Re: [PATCH v3 3/7] arm64: dts: ti: k3-j722s-evm: Update USB0 and USB1

[Siddharth Vadapalli]

On Tue, May 28, 2024 at 03:18:25PM +0300, Roger Quadros wrote:

[...]

> > +	dr_mode = "host";
> > +	maximum-speed = "super-speed";
> > +	phys = <&serdes0_usb_link>;
> > +	phy-names = "cdns3,usb3-phy";
> > +};
> > diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> > index c75744edb143..61b64fae1bf4 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> > @@ -87,3 +87,8 @@ &oc_sram {
> >  	reg = <0x00 0x70000000 0x00 0x40000>;
> >  	ranges = <0x00 0x00 0x70000000 0x40000>;
> >  };
> > +
> > +/* Include bus peripherals that are additionally
> > + * present in J722S
> > + */
> > + #include "k3-j722s-main.dtsi"
> > diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
> 
> The k3-serdes.h changes should be in a separate independent patch.

Ok. Will create a new patch in v4 addressing your comments on patch 5 of
this series to combine Serdes1 changes as well into the same patch.

Regards,
Siddharth.

Re: [PATCH v3 4/7] arm64: dts: ti: k3-serdes: Add Serdes1 lane-muxing macros for J722S

[Siddharth Vadapalli]

On Tue, May 28, 2024 at 03:19:30PM +0300, Roger Quadros wrote:
> 
> 
> On 24/05/2024 12:05, Siddharth Vadapalli wrote:
> > The Serdes1 instance of the Serdes on J722S SoC is a single lane Serdes
> > that is muxed across PCIe and CPSW. Define the lane-muxing macros to be
> > used as the idle state values.
> > 
> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > ---
> > Current patch is v1. No changelog.
> > 
> >  arch/arm64/boot/dts/ti/k3-serdes.h | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
> > index e6a036a4e70b..ef3606068140 100644
> > --- a/arch/arm64/boot/dts/ti/k3-serdes.h
> > +++ b/arch/arm64/boot/dts/ti/k3-serdes.h
> > @@ -206,4 +206,7 @@
> >  #define J722S_SERDES0_LANE0_USB			0x0
> >  #define J722S_SERDES0_LANE0_QSGMII_LANE2	0x1
> >  
> > +#define J722S_SERDES1_LANE0_PCIE0_LANE0		0x0
> > +#define J722S_SERDES1_LANE0_QSGMII_LANE1	0x1
> > +
> 
> Maybe this one patch can deal with both USB and PCIE0 additions to this file
> and could be moved earlier in the series.

Yes. I will combine this with the SERDES0 changes in the v4 series.

Regards,
Siddharth.

Re: [PATCH v3 5/7] arm64: dts: ti: k3-j722s: Add lane mux for Serdes1

[Siddharth Vadapalli]

On Tue, May 28, 2024 at 03:23:32PM +0300, Roger Quadros wrote:
> 
> 
> On 24/05/2024 12:05, Siddharth Vadapalli wrote:
> > The Serdes1 instance of Serdes on J722S SoC can be muxed between PCIe0
> 
> Please use SERDES insted of Serdes or serdes as it is an abbreviation.

Ok.

> 
> > and SGMII1. Update the "serdes_ln_ctrl" node adding support for the lane
> > mux of Serdes1. Additionally, set the default muxing for Serdes1 Lane0 to
> > PCIe0.
> > 
> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > ---
> > Current patch is v1. No changelog.
> > 

[...]

> > @@ -96,8 +96,9 @@ usb1: usb@31200000{
> >  &main_conf {
> >  	serdes_ln_ctrl: mux-controller@4080 {
> >  		compatible = "reg-mux";
> > -		reg = <0x4080 0x4>;
> > +		reg = <0x4080 0x14>;
> >  		#mux-control-cells = <1>;
> > -		mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */
> > +		mux-reg-masks = <0x0 0x3>, /* SERDES0 lane0 select */
> > +				<0x10 0x3>; /* SERDES1 lane0 select */
> 
> Why not introduce this right in the patch where you add serdes_ln_ctrl mux node?

I was preserving patch authorship from the v2 series. I will combine
this in the v4 with a Co-developed-by tag.

Regards,
Siddharth.

Re: [PATCH v3 6/7] arm64: dts: ti: k3-j722s-main: Add WIZ1 and Serdes1 nodes

[Siddharth Vadapalli]

On Tue, May 28, 2024 at 03:24:44PM +0300, Roger Quadros wrote:

[...]

> > +			#size-cells = <0>;
> > +			#clock-cells = <1>;
> > +		};
> > +	};
> > +
> 
> Any particular reason to split addition of various nodes in the k3-j722s-main file?
> I think all k3-j722s-main.dtsi additions can be in one patch.

The intent was to preserve patch ownership from v2. I will combine them
in the v4.

Regards,
Siddharth.

Re: [PATCH v3 7/7] arm64: dts: ti: k3-j722s: Add support for PCIe0

[Siddharth Vadapalli]

On Tue, May 28, 2024 at 03:26:11PM +0300, Roger Quadros wrote:

[...]

> >  
> > +#include <dt-bindings/phy/phy-cadence.h>
> >  #include <dt-bindings/phy/phy-ti.h>
> >  
> >  /*
> > @@ -96,6 +97,35 @@ serdes1: serdes@f010000 {
> >  		};
> >  	};
> >  
> > +	pcie0_rc: pcie@f102000 {
> 
> Please split PCIe node addition in  to separate patch. hopefully you can squash it with patches that
> add USB, SERDES0 and SERDES1 to k3-j722s-main.dtsi.

I will do so in the v4 series. Thank you for reviewing and sharing your
feedback on this series.

Regards,
Siddharth.