* [PATCH 0/2] Use R8A77980 CPG core clock and SYSC power domain macros
@ 2018-04-26 10:40 Sergei Shtylyov
2018-04-26 10:43 ` [PATCH 1/2] arm64: dts: renesas: r8a77980: use CPG core clock macros Sergei Shtylyov
2018-04-26 10:45 ` [PATCH 2/2] arm64: dts: renesas: r8a77980: use SYSC power domain macros Sergei Shtylyov
0 siblings, 2 replies; 5+ messages in thread
From: Sergei Shtylyov @ 2018-04-26 10:40 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Mark Rutland, Catalin Marinas, Magnus Damm, Will Deacon,
linux-arm-kernel@lists.infradead.org
Hello!
Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20180425-v4.17-rc2' tag. Now that the R8A77980 CPG core clock
and SYSC power domain #define's have hit Linus' tree, we can replace the bare
numbers (we had to use to avoid a cross tree dependencies) with these #define's,
at last...
[1/2] arm64: dts: renesas: r8a77980: use CPG core clock macros
[2/2] arm64: dts: renesas: r8a77978: use SYSC power domain macros
WBR, Sergei
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] arm64: dts: renesas: r8a77980: use CPG core clock macros
2018-04-26 10:40 [PATCH 0/2] Use R8A77980 CPG core clock and SYSC power domain macros Sergei Shtylyov
@ 2018-04-26 10:43 ` Sergei Shtylyov
2018-05-02 7:03 ` Simon Horman
2018-04-26 10:45 ` [PATCH 2/2] arm64: dts: renesas: r8a77980: use SYSC power domain macros Sergei Shtylyov
1 sibling, 1 reply; 5+ messages in thread
From: Sergei Shtylyov @ 2018-04-26 10:43 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Mark Rutland, Catalin Marinas, Magnus Damm, Will Deacon,
linux-arm-kernel@lists.infradead.org
Now that the commit 35b3c462dae1 ("dt-bindings: clock: add R8A77980 CPG
core clock definitions") has hit Linus' tree, we can replace the bare
numbers (we had to use to avoid a cross tree dependency) with these macro
definitions...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -6,9 +6,9 @@
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
+#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
/ {
compatible = "renesas,r8a77980";
@@ -23,7 +23,7 @@
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0>;
- clocks = <&cpg CPG_CORE 0>;
+ clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
power-domains = <&sysc 5>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
@@ -104,7 +104,7 @@
reg = <0 0xe6540000 0 0x60>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 520>,
- <&cpg CPG_CORE 19>,
+ <&cpg CPG_CORE R8A77980_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
@@ -122,7 +122,7 @@
reg = <0 0xe6550000 0 0x60>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 519>,
- <&cpg CPG_CORE 19>,
+ <&cpg CPG_CORE R8A77980_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x33>, <&dmac1 0x32>,
@@ -140,7 +140,7 @@
reg = <0 0xe6560000 0 0x60>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 518>,
- <&cpg CPG_CORE 19>,
+ <&cpg CPG_CORE R8A77980_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x35>, <&dmac1 0x34>,
@@ -158,7 +158,7 @@
reg = <0 0xe66a0000 0 0x60>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE 19>,
+ <&cpg CPG_CORE R8A77980_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x37>, <&dmac1 0x36>,
@@ -220,7 +220,7 @@
reg = <0 0xe6e60000 0 0x40>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 207>,
- <&cpg CPG_CORE 19>,
+ <&cpg CPG_CORE R8A77980_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
@@ -238,7 +238,7 @@
reg = <0 0xe6e68000 0 0x40>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 206>,
- <&cpg CPG_CORE 19>,
+ <&cpg CPG_CORE R8A77980_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
@@ -256,7 +256,7 @@
reg = <0 0xe6c50000 0 0x40>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 204>,
- <&cpg CPG_CORE 19>,
+ <&cpg CPG_CORE R8A77980_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x57>, <&dmac1 0x56>,
@@ -274,7 +274,7 @@
reg = <0 0xe6c40000 0 0x40>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 203>,
- <&cpg CPG_CORE 19>,
+ <&cpg CPG_CORE R8A77980_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x59>, <&dmac1 0x58>,
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] arm64: dts: renesas: r8a77980: use SYSC power domain macros
2018-04-26 10:40 [PATCH 0/2] Use R8A77980 CPG core clock and SYSC power domain macros Sergei Shtylyov
2018-04-26 10:43 ` [PATCH 1/2] arm64: dts: renesas: r8a77980: use CPG core clock macros Sergei Shtylyov
@ 2018-04-26 10:45 ` Sergei Shtylyov
2018-05-02 7:03 ` Simon Horman
1 sibling, 1 reply; 5+ messages in thread
From: Sergei Shtylyov @ 2018-04-26 10:45 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Mark Rutland, Catalin Marinas, Magnus Damm, Will Deacon,
linux-arm-kernel@lists.infradead.org
Now that the commit 7755b40d07a8 ("dt-bindings: power: add R8A77980 SYSC
power domain definitions") has hit Linus' tree, we can replace the bare
numbers (we had to use to avoid a cross tree dependency) with these macro
definitions...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 31 +++++++++++++++---------------
1 file changed, 16 insertions(+), 15 deletions(-)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a77980-sysc.h>
/ {
compatible = "renesas,r8a77980";
@@ -24,14 +25,14 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0>;
clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
- power-domains = <&sysc 5>;
+ power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
};
L2_CA53: cache-controller {
compatible = "cache";
- power-domains = <&sysc 21>;
+ power-domains = <&sysc R8A77980_PD_CA53_SCU>;
cache-unified;
cache-level = <2>;
};
@@ -110,7 +111,7 @@
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
<&dmac2 0x31>, <&dmac2 0x30>;
dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 520>;
status = "disabled";
};
@@ -128,7 +129,7 @@
dmas = <&dmac1 0x33>, <&dmac1 0x32>,
<&dmac2 0x33>, <&dmac2 0x32>;
dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 519>;
status = "disabled";
};
@@ -146,7 +147,7 @@
dmas = <&dmac1 0x35>, <&dmac1 0x34>,
<&dmac2 0x35>, <&dmac2 0x34>;
dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 518>;
status = "disabled";
};
@@ -164,7 +165,7 @@
dmas = <&dmac1 0x37>, <&dmac1 0x36>,
<&dmac2 0x37>, <&dmac2 0x36>;
dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 517>;
status = "disabled";
};
@@ -206,7 +207,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
#address-cells = <1>;
@@ -226,7 +227,7 @@
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
<&dmac2 0x51>, <&dmac2 0x50>;
dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 207>;
status = "disabled";
};
@@ -244,7 +245,7 @@
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
<&dmac2 0x53>, <&dmac2 0x52>;
dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 206>;
status = "disabled";
};
@@ -262,7 +263,7 @@
dmas = <&dmac1 0x57>, <&dmac1 0x56>,
<&dmac2 0x57>, <&dmac2 0x56>;
dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 204>;
status = "disabled";
};
@@ -280,7 +281,7 @@
dmas = <&dmac1 0x59>, <&dmac1 0x58>,
<&dmac2 0x59>, <&dmac2 0x58>;
dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 203>;
status = "disabled";
};
@@ -313,7 +314,7 @@
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <16>;
@@ -347,7 +348,7 @@
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 217>;
clock-names = "fck";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 217>;
#dma-cells = <1>;
dma-channels = <16>;
@@ -359,7 +360,7 @@
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 314>;
max-frequency = <200000000>;
status = "disabled";
@@ -378,7 +379,7 @@
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r8a77980: use CPG core clock macros
2018-04-26 10:43 ` [PATCH 1/2] arm64: dts: renesas: r8a77980: use CPG core clock macros Sergei Shtylyov
@ 2018-05-02 7:03 ` Simon Horman
0 siblings, 0 replies; 5+ messages in thread
From: Simon Horman @ 2018-05-02 7:03 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Magnus Damm, Will Deacon,
linux-renesas-soc, Rob Herring, Catalin Marinas,
linux-arm-kernel@lists.infradead.org
On Thu, Apr 26, 2018 at 01:43:56PM +0300, Sergei Shtylyov wrote:
> Now that the commit 35b3c462dae1 ("dt-bindings: clock: add R8A77980 CPG
> core clock definitions") has hit Linus' tree, we can replace the bare
> numbers (we had to use to avoid a cross tree dependency) with these macro
> definitions...
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks, applied.
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] arm64: dts: renesas: r8a77980: use SYSC power domain macros
2018-04-26 10:45 ` [PATCH 2/2] arm64: dts: renesas: r8a77980: use SYSC power domain macros Sergei Shtylyov
@ 2018-05-02 7:03 ` Simon Horman
0 siblings, 0 replies; 5+ messages in thread
From: Simon Horman @ 2018-05-02 7:03 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Magnus Damm, Will Deacon,
linux-renesas-soc, Rob Herring, Catalin Marinas,
linux-arm-kernel@lists.infradead.org
On Thu, Apr 26, 2018 at 01:45:21PM +0300, Sergei Shtylyov wrote:
> Now that the commit 7755b40d07a8 ("dt-bindings: power: add R8A77980 SYSC
> power domain definitions") has hit Linus' tree, we can replace the bare
> numbers (we had to use to avoid a cross tree dependency) with these macro
> definitions...
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks, applied.
^ permalink raw reply [flat|nested] 5+ messages in thread
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2018-04-26 10:40 [PATCH 0/2] Use R8A77980 CPG core clock and SYSC power domain macros Sergei Shtylyov
2018-04-26 10:43 ` [PATCH 1/2] arm64: dts: renesas: r8a77980: use CPG core clock macros Sergei Shtylyov
2018-05-02 7:03 ` Simon Horman
2018-04-26 10:45 ` [PATCH 2/2] arm64: dts: renesas: r8a77980: use SYSC power domain macros Sergei Shtylyov
2018-05-02 7:03 ` Simon Horman
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