[PATCH 0/4] arm64: add R8A78000 support

[PATCH 0/4] arm64: add R8A78000 support

[Kuninori Morimoto]

Hi Geert

This patch-set adds R8A78000 and Ironhide board support.
It is based on SDK v4.28.0 or later. It will be released at end of Oct.

Duy Nguyen (1):
  soc: renesas: Identify R-Car X5H

Hai Pham (2):
  arm64: dts: renesas: Add R8A78000 X5H DTs
  arm64: renesas: Add R8A78000 Ironhide board code

Kuninori Morimoto (1):
  dt-bindings: soc: renesas: Document R-Car X5H Ironhide

 .../bindings/soc/renesas/renesas.yaml         |   6 +
 arch/arm64/boot/dts/renesas/Makefile          |   2 +
 .../boot/dts/renesas/r8a78000-ironhide.dts    |  87 ++
 arch/arm64/boot/dts/renesas/r8a78000.dtsi     | 936 ++++++++++++++++++
 drivers/soc/renesas/Kconfig                   |  12 +
 drivers/soc/renesas/renesas-soc.c             |  12 +
 6 files changed, 1055 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r8a78000.dtsi

-- 
2.43.0

[PATCH 1/4] dt-bindings: soc: renesas: Document R-Car X5H Ironhide

[Kuninori Morimoto]

Document the compatible values for the Renesas R-Car X5H (R8A78000) SoC,
as used on the Renesas Ironhide board.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
 Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index 5f9d541d177a..f4947ac65460 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -473,6 +473,12 @@ properties:
           - const: renesas,r8a779mb
           - const: renesas,r8a7795
 
+      - description: R-Car X5H (R8A78000)
+        items:
+          - enum:
+              - renesas,ironhide    # Ironhide (RTP8A78000ASKB0F10S)
+          - const: renesas,r8a78000
+
       - description: RZ/N1D (R9A06G032)
         items:
           - enum:
-- 
2.43.0

[PATCH 2/4] soc: renesas: Identify R-Car X5H

[Kuninori Morimoto]

From: Duy Nguyen <duy.nguyen.rh@renesas.com>

Add support for identifying the R-Car X5H SoC.

[Kuninori: tidyup for upstreaming]

Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/soc/renesas/Kconfig       | 12 ++++++++++++
 drivers/soc/renesas/renesas-soc.c | 12 ++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 719b7f4f376f..7229f4afb3fa 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -39,6 +39,10 @@ config ARCH_RCAR_GEN4
 	bool
 	select ARCH_RCAR_GEN3
 
+config ARCH_RCAR_GEN5
+	bool
+	select ARCH_RCAR_GEN4
+
 config ARCH_RMOBILE
 	bool
 	select PM
@@ -348,6 +352,14 @@ config ARCH_R8A779H0
 	help
 	  This enables support for the Renesas R-Car V4M SoC.
 
+config ARCH_R8A78000
+	bool "ARM64 Platform support for R8A78000 (R-Car X5H)"
+	default y if ARCH_RENESAS
+	default ARCH_RENESAS
+	select ARCH_RCAR_GEN5
+	help
+	  This enables support for the Renesas R-Car X5H SoC.
+
 config ARCH_R9A07G043
 	bool "ARM64 Platform support for R9A07G043U (RZ/G2UL)"
 	default y if ARCH_RENESAS
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index df2b38417b80..1eb52356b996 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -36,6 +36,10 @@ static const struct renesas_family fam_rcar_gen4 __initconst __maybe_unused = {
 	.name	= "R-Car Gen4",
 };
 
+static const struct renesas_family fam_rcar_gen5 __initconst __maybe_unused = {
+	.name   = "R-Car Gen5",
+};
+
 static const struct renesas_family fam_rmobile __initconst __maybe_unused = {
 	.name	= "R-Mobile",
 	.reg	= 0xe600101c,		/* CCCR (Common Chip Code Register) */
@@ -266,6 +270,11 @@ static const struct renesas_soc soc_rcar_v4m __initconst __maybe_unused = {
 	.id     = 0x5d,
 };
 
+static const struct renesas_soc soc_rcar_x5h __initconst __maybe_unused = {
+	.family = &fam_rcar_gen5,
+	.id     = 0x60,
+};
+
 static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = {
 	.family	= &fam_shmobile,
 	.id	= 0x37,
@@ -378,6 +387,9 @@ static const struct of_device_id renesas_socs[] __initconst __maybe_unused = {
 #ifdef CONFIG_ARCH_R8A779H0
 	{ .compatible = "renesas,r8a779h0",	.data = &soc_rcar_v4m },
 #endif
+#ifdef CONFIG_ARCH_R8A78000
+	{ .compatible = "renesas,r8a78000",	.data = &soc_rcar_x5h },
+#endif
 #ifdef CONFIG_ARCH_R9A07G043
 #ifdef CONFIG_RISCV
 	{ .compatible = "renesas,r9a07g043",	.data = &soc_rz_five },
-- 
2.43.0

[PATCH 3/4] arm64: dts: renesas: Add R8A78000 X5H DTs

[Kuninori Morimoto]

From: Hai Pham <hai.pham.ud@renesas.com>

Add initial DT support for R8A78000 (R-Car X5H) SoC.

[Kuninori: tidyup for upstreaming]

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com>
Signed-off-by: Minh Le <minh.le.aj@renesas.com>
Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a78000.dtsi | 936 ++++++++++++++++++++++
 1 file changed, 936 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a78000.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
new file mode 100644
index 000000000000..c81b3ce75222
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -0,0 +1,936 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car X5H (R8A78000) SoC
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r8a78000";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&a720_0>;
+				};
+				core1 {
+					cpu = <&a720_1>;
+				};
+				core2 {
+					cpu = <&a720_2>;
+				};
+				core3 {
+					cpu = <&a720_3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&a720_4>;
+				};
+				core1 {
+					cpu = <&a720_5>;
+				};
+				core2 {
+					cpu = <&a720_6>;
+				};
+				core3 {
+					cpu = <&a720_7>;
+				};
+			};
+
+			cluster2 {
+				core0 {
+					cpu = <&a720_8>;
+				};
+				core1 {
+					cpu = <&a720_9>;
+				};
+				core2 {
+					cpu = <&a720_10>;
+				};
+				core3 {
+					cpu = <&a720_11>;
+				};
+			};
+
+			cluster3 {
+				core0 {
+					cpu = <&a720_12>;
+				};
+				core1 {
+					cpu = <&a720_13>;
+				};
+				core2 {
+					cpu = <&a720_14>;
+				};
+				core3 {
+					cpu = <&a720_15>;
+				};
+			};
+
+			cluster4 {
+				core0 {
+					cpu = <&a720_16>;
+				};
+				core1 {
+					cpu = <&a720_17>;
+				};
+				core2 {
+					cpu = <&a720_18>;
+				};
+				core3 {
+					cpu = <&a720_19>;
+				};
+			};
+
+			cluster5 {
+				core0 {
+					cpu = <&a720_20>;
+				};
+				core1 {
+					cpu = <&a720_21>;
+				};
+				core2 {
+					cpu = <&a720_22>;
+				};
+				core3 {
+					cpu = <&a720_23>;
+				};
+			};
+
+			cluster6 {
+				core0 {
+					cpu = <&a720_24>;
+				};
+				core1 {
+					cpu = <&a720_25>;
+				};
+				core2 {
+					cpu = <&a720_26>;
+				};
+				core3 {
+					cpu = <&a720_27>;
+				};
+			};
+
+			cluster7 {
+				core0 {
+					cpu = <&a720_28>;
+				};
+				core1 {
+					cpu = <&a720_29>;
+				};
+				core2 {
+					cpu = <&a720_30>;
+				};
+				core3 {
+					cpu = <&a720_31>;
+				};
+			};
+		};
+
+		a720_0: cpu@0 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x0>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_0>;
+			enable-method = "psci";
+
+			L1_CA720_0: l1-cache-controller-0 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_0>;
+			};
+
+			L2_CA720_0: l2-cache-controller-0 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_0>;
+			};
+		};
+
+		a720_1: cpu@100 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x100>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_1>;
+			enable-method = "psci";
+
+			L1_CA720_1: l1-cache-controller-1 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_1>;
+			};
+
+			L2_CA720_1: l2-cache-controller-1 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_0>;
+			};
+		};
+
+		a720_2: cpu@200 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x200>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_2>;
+			enable-method = "psci";
+
+			L1_CA720_2: l1-cache-controller-2 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_2>;
+			};
+
+			L2_CA720_2: l2-cache-controller-2 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_0>;
+			};
+		};
+
+		a720_3: cpu@300 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x300>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_3>;
+			enable-method = "psci";
+
+			L1_CA720_3: l1-cache-controller-3 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_3>;
+			};
+
+			L2_CA720_3: l2-cache-controller-3 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_0>;
+			};
+		};
+
+		a720_4: cpu@10000 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x10000>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_4>;
+			enable-method = "psci";
+
+			L1_CA720_4: l1-cache-controller-4 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_4>;
+			};
+
+			L2_CA720_4: l2-cache-controller-4 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_1>;
+			};
+		};
+
+		a720_5: cpu@10100 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x10100>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_5>;
+			enable-method = "psci";
+
+			L1_CA720_5: l1-cache-controller-5 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_5>;
+			};
+
+			L2_CA720_5: l2-cache-controller-5 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_1>;
+			};
+		};
+
+		a720_6: cpu@10200 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x10200>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_6>;
+			enable-method = "psci";
+
+			L1_CA720_6: l1-cache-controller-6 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_6>;
+			};
+
+			L2_CA720_6: l2-cache-controller-6 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_1>;
+			};
+		};
+
+		a720_7: cpu@10300 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x10300>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_7>;
+			enable-method = "psci";
+
+			L1_CA720_7: l1-cache-controller-7 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_7>;
+			};
+
+			L2_CA720_7: l2-cache-controller-7 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_1>;
+			};
+		};
+
+		a720_8: cpu@20000 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x20000>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_8>;
+			enable-method = "psci";
+
+			L1_CA720_8: l1-cache-controller-8 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_8>;
+			};
+
+			L2_CA720_8: l2-cache-controller-8 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_2>;
+			};
+		};
+
+		a720_9: cpu@20100 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x20100>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_9>;
+			enable-method = "psci";
+
+			L1_CA720_9: l1-cache-controller-9 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_9>;
+			};
+
+			L2_CA720_9: l2-cache-controller-9 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_2>;
+			};
+		};
+
+		a720_10: cpu@20200 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x20200>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_10>;
+			enable-method = "psci";
+
+			L1_CA720_10: l1-cache-controller-10 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_10>;
+			};
+
+			L2_CA720_10: l2-cache-controller-10 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_2>;
+			};
+		};
+
+		a720_11: cpu@20300 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x20300>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_11>;
+			enable-method = "psci";
+
+			L1_CA720_11: l1-cache-controller-11 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_11>;
+			};
+
+			L2_CA720_11: l2-cache-controller-11 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_2>;
+			};
+		};
+
+		a720_12: cpu@30000 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x30000>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_12>;
+			enable-method = "psci";
+
+			L1_CA720_12: l1-cache-controller-12 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_12>;
+			};
+
+			L2_CA720_12: l2-cache-controller-12 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_3>;
+			};
+		};
+
+		a720_13: cpu@30100 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x30100>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_13>;
+			enable-method = "psci";
+
+			L1_CA720_13: l1-cache-controller-13 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_13>;
+			};
+
+			L2_CA720_13: l2-cache-controller-13 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_3>;
+			};
+		};
+
+		a720_14: cpu@30200 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x30200>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_14>;
+			enable-method = "psci";
+
+			L1_CA720_14: l1-cache-controller-14 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_14>;
+			};
+
+			L2_CA720_14: l2-cache-controller-14 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_3>;
+			};
+		};
+
+		a720_15: cpu@30300 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x30300>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_15>;
+			enable-method = "psci";
+
+			L1_CA720_15: l1-cache-controller-15 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_15>;
+			};
+
+			L2_CA720_15: l2-cache-controller-15 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_3>;
+			};
+		};
+
+		a720_16: cpu@40000 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x40000>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_16>;
+			enable-method = "psci";
+
+			L1_CA720_16: l1-cache-controller-16 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_16>;
+			};
+
+			L2_CA720_16: l2-cache-controller-16 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_4>;
+			};
+		};
+
+		a720_17: cpu@40100 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x40100>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_17>;
+			enable-method = "psci";
+
+			L1_CA720_17: l1-cache-controller-17 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_17>;
+			};
+
+			L2_CA720_17: l2-cache-controller-17 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_4>;
+			};
+		};
+
+		a720_18: cpu@40200 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x40200>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_18>;
+			enable-method = "psci";
+
+			L1_CA720_18: l1-cache-controller-18 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_18>;
+			};
+
+			L2_CA720_18: l2-cache-controller-18 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_4>;
+			};
+		};
+
+		a720_19: cpu@40300 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x40300>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_19>;
+			enable-method = "psci";
+
+			L1_CA720_19: l1-cache-controller-19 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_19>;
+			};
+
+			L2_CA720_19: l2-cache-controller-19 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_4>;
+			};
+		};
+
+		a720_20: cpu@50000 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x50000>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_20>;
+			enable-method = "psci";
+
+			L1_CA720_20: l1-cache-controller-20 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_20>;
+			};
+
+			L2_CA720_20: l2-cache-controller-20 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_5>;
+			};
+		};
+
+		a720_21: cpu@50100 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x50100>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_21>;
+			enable-method = "psci";
+
+			L1_CA720_21: l1-cache-controller-21 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_21>;
+			};
+
+			L2_CA720_21: l2-cache-controller-21 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_5>;
+			};
+		};
+
+		a720_22: cpu@50200 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x50200>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_22>;
+			enable-method = "psci";
+
+			L1_CA720_22: l1-cache-controller-22 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_22>;
+			};
+
+			L2_CA720_22: l2-cache-controller-22 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_5>;
+			};
+		};
+
+		a720_23: cpu@50300 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x50300>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_23>;
+			enable-method = "psci";
+
+			L1_CA720_23: l1-cache-controller-23 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_23>;
+			};
+
+			L2_CA720_23: l2-cache-controller-23 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_5>;
+			};
+		};
+
+		a720_24: cpu@60000 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x60000>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_24>;
+			enable-method = "psci";
+
+			L1_CA720_24: l1-cache-controller-24 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_24>;
+			};
+
+			L2_CA720_24: l2-cache-controller-24 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_6>;
+			};
+		};
+
+		a720_25: cpu@60100 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x60100>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_25>;
+			enable-method = "psci";
+
+			L1_CA720_25: l1-cache-controller-25 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_25>;
+			};
+
+			L2_CA720_25: l2-cache-controller-25 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_6>;
+			};
+		};
+
+		a720_26: cpu@60200 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x60200>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_26>;
+			enable-method = "psci";
+
+			L1_CA720_26: l1-cache-controller-26 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_26>;
+			};
+
+			L2_CA720_26: l2-cache-controller-26 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_6>;
+			};
+		};
+
+		a720_27: cpu@60300 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x60300>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_27>;
+			enable-method = "psci";
+
+			L1_CA720_27: l1-cache-controller-27 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_27>;
+			};
+
+			L2_CA720_27: l2-cache-controller-27 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_6>;
+			};
+		};
+
+		a720_28: cpu@70000 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x70000>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_28>;
+			enable-method = "psci";
+
+			L1_CA720_28: l1-cache-controller-28 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_28>;
+			};
+
+			L2_CA720_28: l2-cache-controller-28 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_7>;
+			};
+		};
+
+		a720_29: cpu@70100 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x70100>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_29>;
+			enable-method = "psci";
+
+			L1_CA720_29: l1-cache-controller-29 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_29>;
+			};
+
+			L2_CA720_29: l2-cache-controller-29 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_7>;
+			};
+		};
+
+		a720_30: cpu@70200 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x70200>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_30>;
+			enable-method = "psci";
+
+			L1_CA720_30: l1-cache-controller-30 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_30>;
+			};
+
+			L2_CA720_30: l2-cache-controller-30 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_7>;
+			};
+		};
+
+		a720_31: cpu@70300 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x70300>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_31>;
+			enable-method = "psci";
+
+			L1_CA720_31: l1-cache-controller-31 {
+				compatible = "cache";
+				next-level-cache = <&L2_CA720_31>;
+			};
+
+			L2_CA720_31: l2-cache-controller-31 {
+				compatible = "cache";
+				next-level-cache = <&L3_CA720_7>;
+			};
+		};
+
+		L3_CA720_0: cache-controller-0 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA720_1: cache-controller-1 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA720_2: cache-controller-2 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA720_3: cache-controller-3 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA720_4: cache-controller-4 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA720_5: cache-controller-5 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA720_6: cache-controller-6 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA720_7: cache-controller-7 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <3>;
+		};
+	};
+
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	extalr_clk: extalr {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	/* In the early phase, there is no clock control support,
+	 * so assume that the clocks are enabled by default.
+	 * Therefore, dummy clocks are used.
+	 */
+	dummy_clk_sgasyncd4: dummy_clk_sgasyncd4 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <266660000>;
+	};
+
+	/* External SCIF clock - to be overridden by boards that provide it */
+	scif_clk: scif {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		prr: chipid@189e0044 {
+			compatible = "renesas,prr";
+			reg = <0 0x189e0044 0 4>;
+		};
+
+		/* The Arm GIC-700AE - View 1 */
+		gic: interrupt-controller@39000000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			redistributor-stride = <0x0 0x40000>;
+			#redistributor-regions = <32>;
+			reg = <0x0 0x39000000 0x0 0x20000>, // GICD
+			      <0x0 0x39080000 0x0 0x40000>, // GICR Core0
+			      <0x0 0x390C0000 0x0 0x40000>, // GICR Core1
+			      <0x0 0x39100000 0x0 0x40000>, // GICR Core2
+			      <0x0 0x39140000 0x0 0x40000>, // GICR Core3
+			      <0x0 0x39180000 0x0 0x40000>, // GICR Core4
+			      <0x0 0x391C0000 0x0 0x40000>, // GICR Core5
+			      <0x0 0x39200000 0x0 0x40000>, // GICR Core6
+			      <0x0 0x39240000 0x0 0x40000>, // GICR Core7
+			      <0x0 0x39280000 0x0 0x40000>, // GICR Core8
+			      <0x0 0x392C0000 0x0 0x40000>, // GICR Core9
+			      <0x0 0x39300000 0x0 0x40000>, // GICR Core10
+			      <0x0 0x39340000 0x0 0x40000>, // GICR Core11
+			      <0x0 0x39380000 0x0 0x40000>, // GICR Core12
+			      <0x0 0x393C0000 0x0 0x40000>, // GICR Core13
+			      <0x0 0x39400000 0x0 0x40000>, // GICR Core14
+			      <0x0 0x39440000 0x0 0x40000>, // GICR Core15
+			      <0x0 0x39480000 0x0 0x40000>, // GICR Core16
+			      <0x0 0x394C0000 0x0 0x40000>, // GICR Core17
+			      <0x0 0x39500000 0x0 0x40000>, // GICR Core18
+			      <0x0 0x39540000 0x0 0x40000>, // GICR Core19
+			      <0x0 0x39580000 0x0 0x40000>, // GICR Core20
+			      <0x0 0x395C0000 0x0 0x40000>, // GICR Core21
+			      <0x0 0x39600000 0x0 0x40000>, // GICR Core22
+			      <0x0 0x39640000 0x0 0x40000>, // GICR Core23
+			      <0x0 0x39680000 0x0 0x40000>, // GICR Core24
+			      <0x0 0x396C0000 0x0 0x40000>, // GICR Core25
+			      <0x0 0x39700000 0x0 0x40000>, // GICR Core26
+			      <0x0 0x39740000 0x0 0x40000>, // GICR Core27
+			      <0x0 0x39780000 0x0 0x40000>, // GICR Core28
+			      <0x0 0x397C0000 0x0 0x40000>, // GICR Core29
+			      <0x0 0x39800000 0x0 0x40000>, // GICR Core30
+			      <0x0 0x39840000 0x0 0x40000>; // GICR Core31
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		scif0: serial@c0700000 {
+			compatible = "renesas,rcar-gen5-scif", "renesas,scif";
+			reg = <0 0xc0700000 0 0x40>;
+			interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			status = "disabled";
+		};
+
+		scif1: serial@c0704000 {
+			compatible = "renesas,rcar-gen5-scif", "renesas,scif";
+			reg = <0 0xc0704000 0 0x40>;
+			interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			status = "disabled";
+		};
+
+		scif3: serial@c0708000 {
+			compatible = "renesas,rcar-gen5-scif", "renesas,scif";
+			reg = <0 0xc0708000 0 0x40>;
+			interrupts = <GIC_SPI 4076 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			status = "disabled";
+		};
+
+		scif4: serial@c070c000 {
+			compatible = "renesas,rcar-gen5-scif", "renesas,scif";
+			reg = <0 0xc070c000 0 0x40>;
+			interrupts = <GIC_SPI 4077 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			status = "disabled";
+		};
+
+		hscif0: serial@c0710000 {
+			compatible = "renesas,rcar-gen5-hscif", "renesas,hscif";
+			reg = <0 0xc0710000 0 0x60>;
+			interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			status = "disabled";
+		};
+
+		hscif1: serial@c0714000 {
+			compatible = "renesas,rcar-gen5-hscif", "renesas,hscif";
+			reg = <0 0xc0714000 0 0x60>;
+			interrupts = <GIC_SPI 4079 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			status = "disabled";
+		};
+
+		hscif2: serial@c0718000 {
+			compatible = "renesas,rcar-gen5-hscif", "renesas,hscif";
+			reg = <0 0xc0718000 0 0x60>;
+			interrupts = <GIC_SPI 4080 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			status = "disabled";
+		};
+
+		hscif3: serial@c071c000 {
+			compatible = "renesas,rcar-gen5-hscif", "renesas,hscif";
+			reg = <0 0xc071c000 0 0x60>;
+			interrupts = <GIC_SPI 4081 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			status = "disabled";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
+				  "hyp-virt";
+	};
+};
-- 
2.43.0

[PATCH 4/4] arm64: renesas: Add R8A78000 Ironhide board code

[Kuninori Morimoto]

From: Hai Pham <hai.pham.ud@renesas.com>

Add the initial support for Renesas R8A7800 board code.

[Kuninori: tidyup for upstreaming]

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile          |  2 +
 .../boot/dts/renesas/r8a78000-ironhide.dts    | 87 +++++++++++++++++++
 2 files changed, 89 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 6093d5f6e548..8b31cc70880d 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -182,3 +182,5 @@ dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb
 
 dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo
 dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo
+
+dtb-$(CONFIG_ARCH_R8A78000) += r8a78000-ironhide.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
new file mode 100644
index 000000000000..16b515c40acd
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the Ironhide board
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a78000.dtsi"
+
+/ {
+	model = "Renesas Ironhide board based on r8a78000";
+	compatible = "renesas,ironhide", "renesas,r8a78000";
+
+	aliases {
+		serial0 = &hscif0;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel rw maxcpus=1";
+		stdout-path = "serial0:1843200n8";
+	};
+
+	memory@60600000 {
+		device_type = "memory";
+		/* first 518MB is reserved for other purposes. */
+		reg = <0x0 0x60600000 0x0 0x5fa00000>;
+	};
+
+	memory@1080000000 {
+		device_type = "memory";
+		reg = <0x10 0x80000000 0x0 0x80000000>;
+	};
+
+	memory@1200000000 {
+		device_type = "memory";
+		reg = <0x12 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1400000000 {
+		device_type = "memory";
+		reg = <0x14 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1600000000 {
+		device_type = "memory";
+		reg = <0x16 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1800000000 {
+		device_type = "memory";
+		reg = <0x18 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1a00000000 {
+		device_type = "memory";
+		reg = <0x1a 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1c00000000 {
+		device_type = "memory";
+		reg = <0x1c 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1e00000000 {
+		device_type = "memory";
+		reg = <0x1e 0x00000000 0x1 0x00000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+	clock-frequency = <32768>;
+};
+
+&hscif0 {
+	uart-has-rtscts;
+	/* Please use exclusively to the scif0 node */
+	status = "okay";
+};
+
+&scif_clk {
+	clock-frequency = <26000000>;
+};
-- 
2.43.0

Re: [PATCH 3/4] arm64: dts: renesas: Add R8A78000 X5H DTs

[Krzysztof Kozlowski]

On Tue, Sep 09, 2025 at 01:45:09AM +0000, Kuninori Morimoto wrote:
> +
> +		a720_0: cpu@0 {
> +			compatible = "arm,cortex-a720";
> +			reg = <0x0 0x0>;
> +			device_type = "cpu";
> +			next-level-cache = <&L1_CA720_0>;
> +			enable-method = "psci";
> +
> +			L1_CA720_0: l1-cache-controller-0 {


cache-controller-0

> +				compatible = "cache";

Missing several properties. I have doubts this passes checks.

> +				next-level-cache = <&L2_CA720_0>;
> +			};
> +
> +			L2_CA720_0: l2-cache-controller-0 {

cache-controller-1

> +				compatible = "cache";
> +				next-level-cache = <&L3_CA720_0>;
> +			};
> +		};
> +
> +		a720_1: cpu@100 {
> +			compatible = "arm,cortex-a720";
> +			reg = <0x0 0x100>;
> +			device_type = "cpu";
> +			next-level-cache = <&L1_CA720_1>;
> +			enable-method = "psci";
> +
> +			L1_CA720_1: l1-cache-controller-1 {


cache-controller-0

> +				compatible = "cache";
> +				next-level-cache = <&L2_CA720_1>;
> +			};
> +
> +			L2_CA720_1: l2-cache-controller-1 {


cache-controller-1

> +				compatible = "cache";
> +				next-level-cache = <&L3_CA720_0>;
> +			};
> +		};
> +
> +		a720_2: cpu@200 {
> +			compatible = "arm,cortex-a720";
> +			reg = <0x0 0x200>;
> +			device_type = "cpu";
> +			next-level-cache = <&L1_CA720_2>;
> +			enable-method = "psci";
> +
> +			L1_CA720_2: l1-cache-controller-2 {

Numbering does not start from 2

cache-controller-0

and so on. All of these nodes are incomplete.

> +				compatible = "cache";
> +				next-level-cache = <&L2_CA720_2>;
> +			};
> +
> +			L2_CA720_2: l2-cache-controller-2 {
> +				compatible = "cache";
> +				next-level-cache = <&L3_CA720_0>;
> +			};
> +		};

...

> +
> +		L3_CA720_2: cache-controller-2 {
> +			compatible = "cache";
> +			cache-unified;
> +			cache-level = <3>;
> +		};
> +
> +		L3_CA720_3: cache-controller-3 {
> +			compatible = "cache";
> +			cache-unified;
> +			cache-level = <3>;
> +		};
> +
> +		L3_CA720_4: cache-controller-4 {
> +			compatible = "cache";
> +			cache-unified;
> +			cache-level = <3>;
> +		};
> +
> +		L3_CA720_5: cache-controller-5 {
> +			compatible = "cache";
> +			cache-unified;
> +			cache-level = <3>;
> +		};
> +
> +		L3_CA720_6: cache-controller-6 {
> +			compatible = "cache";
> +			cache-unified;
> +			cache-level = <3>;
> +		};
> +
> +		L3_CA720_7: cache-controller-7 {
> +			compatible = "cache";
> +			cache-unified;
> +			cache-level = <3>;
> +		};
> +	};
> +
> +	extal_clk: extal {

Use some sane prefix.

https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml

> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		/* This value must be overridden by the board */
> +		clock-frequency = <0>;

Drop instead

> +	};
> +
> +	extalr_clk: extalr {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		/* This value must be overridden by the board */
> +		clock-frequency = <0>;

Drop instead

> +	};
> +
> +	/* In the early phase, there is no clock control support,

Don't use netdev style here.

/*
 *


> +	 * so assume that the clocks are enabled by default.
> +	 * Therefore, dummy clocks are used.
> +	 */
> +	dummy_clk_sgasyncd4: dummy_clk_sgasyncd4 {

See dts coding style. No underscores.

> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <266660000>;
> +	};
> +
> +	/* External SCIF clock - to be overridden by boards that provide it */
> +	scif_clk: scif {

Also name without prefix (or suffix, or anything)

> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <0>;

Drop


> +	};
> +
> +	soc: soc {
> +		compatible = "simple-bus";
> +		interrupt-parent = <&gic>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		prr: chipid@189e0044 {
> +			compatible = "renesas,prr";
> +			reg = <0 0x189e0044 0 4>;
> +		};
> +
> +		/* The Arm GIC-700AE - View 1 */
> +		gic: interrupt-controller@39000000 {
> +			compatible = "arm,gic-v3";
> +			#interrupt-cells = <3>;
> +			#address-cells = <0>;
> +			interrupt-controller;
> +			redistributor-stride = <0x0 0x40000>;
> +			#redistributor-regions = <32>;
> +			reg = <0x0 0x39000000 0x0 0x20000>, // GICD

Please use DTS coding style order of properties.

> +			      <0x0 0x39080000 0x0 0x40000>, // GICR Core0
> +			      <0x0 0x390C0000 0x0 0x40000>, // GICR Core1
> +			      <0x0 0x39100000 0x0 0x40000>, // GICR Core2
> +			      <0x0 0x39140000 0x0 0x40000>, // GICR Core3
> +			      <0x0 0x39180000 0x0 0x40000>, // GICR Core4
> +			      <0x0 0x391C0000 0x0 0x40000>, // GICR Core5
> +			      <0x0 0x39200000 0x0 0x40000>, // GICR Core6
> +			      <0x0 0x39240000 0x0 0x40000>, // GICR Core7
> +			      <0x0 0x39280000 0x0 0x40000>, // GICR Core8
> +			      <0x0 0x392C0000 0x0 0x40000>, // GICR Core9
> +			      <0x0 0x39300000 0x0 0x40000>, // GICR Core10
> +			      <0x0 0x39340000 0x0 0x40000>, // GICR Core11
> +			      <0x0 0x39380000 0x0 0x40000>, // GICR Core12
> +			      <0x0 0x393C0000 0x0 0x40000>, // GICR Core13
> +			      <0x0 0x39400000 0x0 0x40000>, // GICR Core14
> +			      <0x0 0x39440000 0x0 0x40000>, // GICR Core15
> +			      <0x0 0x39480000 0x0 0x40000>, // GICR Core16
> +			      <0x0 0x394C0000 0x0 0x40000>, // GICR Core17
> +			      <0x0 0x39500000 0x0 0x40000>, // GICR Core18
> +			      <0x0 0x39540000 0x0 0x40000>, // GICR Core19
> +			      <0x0 0x39580000 0x0 0x40000>, // GICR Core20
> +			      <0x0 0x395C0000 0x0 0x40000>, // GICR Core21
> +			      <0x0 0x39600000 0x0 0x40000>, // GICR Core22
> +			      <0x0 0x39640000 0x0 0x40000>, // GICR Core23
> +			      <0x0 0x39680000 0x0 0x40000>, // GICR Core24
> +			      <0x0 0x396C0000 0x0 0x40000>, // GICR Core25
> +			      <0x0 0x39700000 0x0 0x40000>, // GICR Core26
> +			      <0x0 0x39740000 0x0 0x40000>, // GICR Core27
> +			      <0x0 0x39780000 0x0 0x40000>, // GICR Core28
> +			      <0x0 0x397C0000 0x0 0x40000>, // GICR Core29
> +			      <0x0 0x39800000 0x0 0x40000>, // GICR Core30
> +			      <0x0 0x39840000 0x0 0x40000>; // GICR Core31

Here 0x0...

> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		scif0: serial@c0700000 {
> +			compatible = "renesas,rcar-gen5-scif", "renesas,scif";
> +			reg = <0 0xc0700000 0 0x40>;

but here just '0' decimal. Just keep your code consistent, whichever you
choose.

Re: [PATCH 4/4] arm64: renesas: Add R8A78000 Ironhide board code

[Krzysztof Kozlowski]

On Tue, Sep 09, 2025 at 01:45:15AM +0000, Kuninori Morimoto wrote:
> From: Hai Pham <hai.pham.ud@renesas.com>
> 
> Add the initial support for Renesas R8A7800 board code.
> 
> [Kuninori: tidyup for upstreaming]
> 
> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
> Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
> Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/Makefile          |  2 +
>  .../boot/dts/renesas/r8a78000-ironhide.dts    | 87 +++++++++++++++++++
>  2 files changed, 89 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
> 
> diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
> index 6093d5f6e548..8b31cc70880d 100644
> --- a/arch/arm64/boot/dts/renesas/Makefile
> +++ b/arch/arm64/boot/dts/renesas/Makefile
> @@ -182,3 +182,5 @@ dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb
>  
>  dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo
>  dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo
> +
> +dtb-$(CONFIG_ARCH_R8A78000) += r8a78000-ironhide.dtb
> diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
> new file mode 100644
> index 000000000000..16b515c40acd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
> @@ -0,0 +1,87 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the Ironhide board
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +#include "r8a78000.dtsi"
> +
> +/ {
> +	model = "Renesas Ironhide board based on r8a78000";
> +	compatible = "renesas,ironhide", "renesas,r8a78000";
> +
> +	aliases {
> +		serial0 = &hscif0;
> +	};
> +
> +	chosen {
> +		bootargs = "ignore_loglevel rw maxcpus=1";

Drop bootargs. Not suitable for mainline. I really do not understand why
all users in mainline and other projects (not your development) must be
limited to cpus=1.

ignore_loglevel is also not suitable for mainline

rw is just incomplete and irrelevant.


Best regards,
Krzysztof

Re: [PATCH 1/4] dt-bindings: soc: renesas: Document R-Car X5H Ironhide

[Krzysztof Kozlowski]

On Tue, Sep 09, 2025 at 01:44:53AM +0000, Kuninori Morimoto wrote:
> Document the compatible values for the Renesas R-Car X5H (R8A78000) SoC,
> as used on the Renesas Ironhide board.
> 
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> ---
>  Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 3/4] arm64: dts: renesas: Add R8A78000 X5H DTs

[Geert Uytterhoeven]

Hi Krzysztof,

Thanks for your quick review!

On Tue, 9 Sept 2025 at 09:46, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On Tue, Sep 09, 2025 at 01:45:09AM +0000, Kuninori Morimoto wrote:

> > +     extal_clk: extal {
>
> Use some sane prefix.
>
> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml
>
> > +             compatible = "fixed-clock";
> > +             #clock-cells = <0>;
> > +             /* This value must be overridden by the board */
> > +             clock-frequency = <0>;
>
> Drop instead

clock-frequency is a required property?

>
> > +     };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/4] arm64: dts: renesas: Add R8A78000 X5H DTs

[Krzysztof Kozlowski]

On 09/09/2025 09:51, Geert Uytterhoeven wrote:
> Hi Krzysztof,
> 
> Thanks for your quick review!
> 
> On Tue, 9 Sept 2025 at 09:46, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>> On Tue, Sep 09, 2025 at 01:45:09AM +0000, Kuninori Morimoto wrote:
> 
>>> +     extal_clk: extal {
>>
>> Use some sane prefix.
>>
>> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml
>>
>>> +             compatible = "fixed-clock";
>>> +             #clock-cells = <0>;
>>> +             /* This value must be overridden by the board */
>>> +             clock-frequency = <0>;
>>
>> Drop instead
> 
> clock-frequency is a required property?

And it should be provided by the board or fail the DTS. I think now it
hides the dtbs_check warnings for no real gain/reason.


Best regards,
Krzysztof

Re: [PATCH 3/4] arm64: dts: renesas: Add R8A78000 X5H DTs

[Geert Uytterhoeven]

Hi Krzysztof,

On Tue, 9 Sept 2025 at 10:38, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On 09/09/2025 09:51, Geert Uytterhoeven wrote:
> > On Tue, 9 Sept 2025 at 09:46, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >> On Tue, Sep 09, 2025 at 01:45:09AM +0000, Kuninori Morimoto wrote:
> >
> >>> +     extal_clk: extal {
> >>
> >> Use some sane prefix.
> >>
> >> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml
> >>
> >>> +             compatible = "fixed-clock";
> >>> +             #clock-cells = <0>;
> >>> +             /* This value must be overridden by the board */
> >>> +             clock-frequency = <0>;
> >>
> >> Drop instead
> >
> > clock-frequency is a required property?
>
> And it should be provided by the board or fail the DTS. I think now it
> hides the dtbs_check warnings for no real gain/reason.

In this particular case, the clock-frequency could indeed be omitted
n the .dtsi, as the extal clock is mandatory, thus must always be
augmented in board .dts.
In case of optional clocks (e.g. serial, PCIe, or CAN external clock
oscillators may not be populated on all boards), it is different.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/4] arm64: dts: renesas: Add R8A78000 X5H DTs

[Krzysztof Kozlowski]

On 09/09/2025 10:50, Geert Uytterhoeven wrote:
> Hi Krzysztof,
> 
> On Tue, 9 Sept 2025 at 10:38, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>> On 09/09/2025 09:51, Geert Uytterhoeven wrote:
>>> On Tue, 9 Sept 2025 at 09:46, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>> On Tue, Sep 09, 2025 at 01:45:09AM +0000, Kuninori Morimoto wrote:
>>>
>>>>> +     extal_clk: extal {
>>>>
>>>> Use some sane prefix.
>>>>
>>>> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml
>>>>
>>>>> +             compatible = "fixed-clock";
>>>>> +             #clock-cells = <0>;
>>>>> +             /* This value must be overridden by the board */
>>>>> +             clock-frequency = <0>;
>>>>
>>>> Drop instead
>>>
>>> clock-frequency is a required property?
>>
>> And it should be provided by the board or fail the DTS. I think now it
>> hides the dtbs_check warnings for no real gain/reason.
> 
> In this particular case, the clock-frequency could indeed be omitted
> n the .dtsi, as the extal clock is mandatory, thus must always be
> augmented in board .dts.
> In case of optional clocks (e.g. serial, PCIe, or CAN external clock
> oscillators may not be populated on all boards), it is different.

1. That is not such clock.
2. So putting invalid value is correct? No, devices which do not exist
should not be in DTSI or should be disabled. Having wrong values is
never correct.

Best regards,
Krzysztof

Re: [PATCH 4/4] arm64: renesas: Add R8A78000 Ironhide board code

[Kuninori Morimoto]

Hi Krzysztof

> > +	chosen {
> > +		bootargs = "ignore_loglevel rw maxcpus=1";
> 
> Drop bootargs. Not suitable for mainline. I really do not understand why
> all users in mainline and other projects (not your development) must be
> limited to cpus=1.

This is initial patch, and only 1 CPU is available for now.
The limitaion will be removed in the future, but not yet for now.

Thank you for your help !!

Best regards
---
Kuninori Morimoto

Re: [PATCH 4/4] arm64: renesas: Add R8A78000 Ironhide board code

[Krzysztof Kozlowski]

On 10/09/2025 01:39, Kuninori Morimoto wrote:
> 
> Hi Krzysztof
> 
>>> +	chosen {
>>> +		bootargs = "ignore_loglevel rw maxcpus=1";
>>
>> Drop bootargs. Not suitable for mainline. I really do not understand why
>> all users in mainline and other projects (not your development) must be
>> limited to cpus=1.
> 
> This is initial patch, and only 1 CPU is available for now.
> The limitaion will be removed in the future, but not yet for now.


You do not understand the problem - DTS describes the hardware, not your
current stage of Linux support. These bootargs are wrong, I have been
commenting on this since years.

Best regards,
Krzysztof

Re: [PATCH 4/4] arm64: renesas: Add R8A78000 Ironhide board code

[Geert Uytterhoeven]

On Wed, 10 Sept 2025 at 09:11, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On 10/09/2025 01:39, Kuninori Morimoto wrote:
> >>> +   chosen {
> >>> +           bootargs = "ignore_loglevel rw maxcpus=1";
> >>
> >> Drop bootargs. Not suitable for mainline. I really do not understand why
> >> all users in mainline and other projects (not your development) must be
> >> limited to cpus=1.
> >
> > This is initial patch, and only 1 CPU is available for now.
> > The limitaion will be removed in the future, but not yet for now.
>
> You do not understand the problem - DTS describes the hardware, not your
> current stage of Linux support. These bootargs are wrong, I have been
> commenting on this since years.

Well, we can't post the full DTS describing the full hardware yet, as
that hasn't been written yet.  E.g. lots of DT bindings for new or
changed components are still missing.  So we have to fall back to the
customary incremental DTS writing...

If currently only one CPU can/must be used, the right way to handle
that is to drop all but the first CPU node from the .dtsi, and only
add the other CPU nodes later.  This is what we've been doing for
other SoCs before, too.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/4] arm64: renesas: Add R8A78000 Ironhide board code

[Krzysztof Kozlowski]

On 10/09/2025 14:45, Geert Uytterhoeven wrote:
> On Wed, 10 Sept 2025 at 09:11, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>> On 10/09/2025 01:39, Kuninori Morimoto wrote:
>>>>> +   chosen {
>>>>> +           bootargs = "ignore_loglevel rw maxcpus=1";
>>>>
>>>> Drop bootargs. Not suitable for mainline. I really do not understand why
>>>> all users in mainline and other projects (not your development) must be
>>>> limited to cpus=1.
>>>
>>> This is initial patch, and only 1 CPU is available for now.
>>> The limitaion will be removed in the future, but not yet for now.
>>
>> You do not understand the problem - DTS describes the hardware, not your
>> current stage of Linux support. These bootargs are wrong, I have been
>> commenting on this since years.
> 
> Well, we can't post the full DTS describing the full hardware yet, as
> that hasn't been written yet.  E.g. lots of DT bindings for new or

No one suggests that, but you tied DTS to your particular setup without
any explanation. Nothing in commit msg, nothing in comment explains why
you need "rw". Nothing explains why maxcpus=1.

I am sorry, but we talk about complete basics here. All odd and weird
code - and maxcpus=1 is the weirdest - MUST HAVE explanation.

> changed components are still missing.  So we have to fall back to the
> customary incremental DTS writing...
> 
> If currently only one CPU can/must be used, the right way to handle
> that is to drop all but the first CPU node from the .dtsi, and only
> add the other CPU nodes later.  This is what we've been doing for
> other SoCs before, too.

No, because on my imaginary system, these bootargs are not helping and
remaining CPUs work fine.

What's more, it breaks my imaginary system root, because I am running it
from readonly NFS root.


Best regards,
Krzysztof

Re: [PATCH 4/4] arm64: renesas: Add R8A78000 Ironhide board code

[Geert Uytterhoeven]

Hi Krzysztof,

On Thu, 11 Sept 2025 at 09:16, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> What's more, it breaks my imaginary system root, because I am running it
> from readonly NFS root.

Real mean run NFS root over SLIP on the serial console
(which is so far the only I/O device described in the DTB ;-).

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/4] arm64: renesas: Add R8A78000 Ironhide board code

[Krzysztof Kozlowski]

On 11/09/2025 09:24, Geert Uytterhoeven wrote:
> Hi Krzysztof,
> 
> On Thu, 11 Sept 2025 at 09:16, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>> What's more, it breaks my imaginary system root, because I am running it
>> from readonly NFS root.
> 
> Real mean run NFS root over SLIP on the serial console
> (which is so far the only I/O device described in the DTB ;-).

My imaginary system is very imaginary :).

Best regards,
Krzysztof