* [PATCH v3 1/5] arm64: dts: ti: k3-am62: disable "cpsw3g" in SoC file and enable in board file
2025-10-14 12:53 [PATCH v3 0/5] TI-K3-DTS: Cleanup CPSW DT Nodes Siddharth Vadapalli
@ 2025-10-14 12:53 ` Siddharth Vadapalli
2025-10-14 12:53 ` [PATCH v3 2/5] arm64: dts: ti: k3-am65: disable "mcu_cpsw" " Siddharth Vadapalli
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Siddharth Vadapalli @ 2025-10-14 12:53 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
Following the existing convention of disabling nodes in the SoC file and
enabling only the required ones in the board file, disable "cpsw3g" node
in the SoC file "k3-am62-main.dtsi" and enable it in the board (or board
include) files:
a) k3-am62-lp-sk.dts
b) k3-am625-beagleplay.dts
c) k3-am625-sk-common.dtsi
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v2 of this patch is at:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250611114336.2392320-2-s-vadapalli@ti.com/
Changes since v2:
- Rebased patch on next-20251010
- Moved changes made in 'k3-am625-sk.dts' into 'k3-am625-sk-common.dtsi'
- Reordered 'status' property within the node to follow the ordering
specified by:
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
Regards,
Siddharth.
arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 4 ++++
arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 1 +
arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi | 1 +
4 files changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts
index ecfba05fe5c2..89be21783e27 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts
@@ -181,6 +181,10 @@ &sdhci1 {
vqmmc-supply = <&vddshv_sdio>;
};
+&cpsw3g {
+ status = "okay";
+};
+
&cpsw_port2 {
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index 40fb3c9e674c..0fd23ee996a1 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
@@ -723,6 +723,8 @@ cpsw3g: ethernet@8000000 {
dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
"tx7", "rx";
+ status = "disabled";
+
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts
index 7028d9835c4a..774178b9aa88 100644
--- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts
+++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts
@@ -590,6 +590,7 @@ &cpsw3g {
<&gbe_pmx_obsclk>;
assigned-clocks = <&k3_clks 157 70>, <&k3_clks 157 20>;
assigned-clock-parents = <&k3_clks 157 72>, <&k3_clks 157 22>;
+ status = "okay";
};
&cpsw_port1 {
diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi
index fe0b98e1d105..73a8882a650a 100644
--- a/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi
@@ -212,6 +212,7 @@ &sdhci1 {
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
+ status = "okay";
};
&cpsw_port2 {
--
2.51.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v3 2/5] arm64: dts: ti: k3-am65: disable "mcu_cpsw" in SoC file and enable in board file
2025-10-14 12:53 [PATCH v3 0/5] TI-K3-DTS: Cleanup CPSW DT Nodes Siddharth Vadapalli
2025-10-14 12:53 ` [PATCH v3 1/5] arm64: dts: ti: k3-am62: disable "cpsw3g" in SoC file and enable in board file Siddharth Vadapalli
@ 2025-10-14 12:53 ` Siddharth Vadapalli
2025-10-14 12:53 ` [PATCH v3 3/5] arm64: dts: ti: k3-j7200: " Siddharth Vadapalli
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Siddharth Vadapalli @ 2025-10-14 12:53 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
Following the existing convention of disabling nodes in the SoC file and
enabling only the required ones in the board file, disable "mcu_cpsw" node
in the SoC file "k3-am65-mcu.dtsi" and enable it in the board file
"k3-am654-base-board.dts". Also, now that "mcu_cpsw" is disabled in the
SoC file, disabling it in "k3-am65-iot2050-common.dtsi" is no longer
required. Hence, remove the section corresponding to this change.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v2 of this patch is at:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250611114336.2392320-3-s-vadapalli@ti.com/
Changes since v2:
- Rebased patch on next-20251010
- Reordered 'status' property within the node to follow the ordering
specified by:
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
Regards,
Siddharth.
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 4 ----
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 +
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
index 42ba3dab2fc1..a9a4e7401a49 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
@@ -457,10 +457,6 @@ &main_i2c3 {
#size-cells = <0>;
};
-&mcu_cpsw {
- status = "disabled";
-};
-
&sdhci1 {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
index f6d9a5779918..74439e0c16a5 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -354,6 +354,8 @@ mcu_cpsw: ethernet@46000000 {
"tx4", "tx5", "tx6", "tx7",
"rx";
+ status = "disabled";
+
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 0c42c486d83a..8c3f150f6a84 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -571,6 +571,7 @@ partition@3fe0000 {
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default>;
+ status = "okay";
};
&davinci_mdio {
--
2.51.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v3 3/5] arm64: dts: ti: k3-j7200: disable "mcu_cpsw" in SoC file and enable in board file
2025-10-14 12:53 [PATCH v3 0/5] TI-K3-DTS: Cleanup CPSW DT Nodes Siddharth Vadapalli
2025-10-14 12:53 ` [PATCH v3 1/5] arm64: dts: ti: k3-am62: disable "cpsw3g" in SoC file and enable in board file Siddharth Vadapalli
2025-10-14 12:53 ` [PATCH v3 2/5] arm64: dts: ti: k3-am65: disable "mcu_cpsw" " Siddharth Vadapalli
@ 2025-10-14 12:53 ` Siddharth Vadapalli
2025-10-14 12:53 ` [PATCH v3 4/5] arm64: dts: ti: k3-j721e: disable "mcu_cpsw" in SoC file and enable it " Siddharth Vadapalli
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Siddharth Vadapalli @ 2025-10-14 12:53 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
Following the existing convention of disabling nodes in the SoC file and
enabling only the required ones in the board file, disable "mcu_cpsw" node
in the SoC file "k3-j7200-mcu-wakeup.dtsi" and enable it in the board file
"k3-j7200-common-proc-board.dts".
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v2 of this patch is at:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250611114336.2392320-4-s-vadapalli@ti.com/
Changes since v2:
- Rebased patch on next-20251010
- Reordered 'status' property within the node to follow the ordering
specified by:
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
Regards,
Siddharth.
arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 1 +
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index f684ce6ad9ad..f03a15edf954 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -323,6 +323,7 @@ &wkup_gpio0 {
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
+ status = "okay";
};
&davinci_mdio {
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index 692c4745040e..fec1db8b133d 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -432,6 +432,8 @@ mcu_cpsw: ethernet@46000000 {
"tx4", "tx5", "tx6", "tx7",
"rx";
+ status = "disabled";
+
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
--
2.51.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v3 4/5] arm64: dts: ti: k3-j721e: disable "mcu_cpsw" in SoC file and enable it in board file
2025-10-14 12:53 [PATCH v3 0/5] TI-K3-DTS: Cleanup CPSW DT Nodes Siddharth Vadapalli
` (2 preceding siblings ...)
2025-10-14 12:53 ` [PATCH v3 3/5] arm64: dts: ti: k3-j7200: " Siddharth Vadapalli
@ 2025-10-14 12:53 ` Siddharth Vadapalli
2025-10-14 12:53 ` [PATCH v3 5/5] arm64: dts: ti: k3-j721s2: disable "mcu_cpsw" in SoC file and enable in board files Siddharth Vadapalli
2025-10-14 17:07 ` [PATCH v3 0/5] TI-K3-DTS: Cleanup CPSW DT Nodes Dominik Haller
5 siblings, 0 replies; 9+ messages in thread
From: Siddharth Vadapalli @ 2025-10-14 12:53 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
Following the existing convention of disabling nodes in the SoC file and
enabling only the required ones in the board file, disable "mcu_cpsw" node
in the SoC file "k3-j721e-mcu-wakeup.dtsi" and enable it in the board file
"k3-j721e-common-proc-board.dts".
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v2 of this patch is at:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250611114336.2392320-5-s-vadapalli@ti.com/
Changes since v2:
- Rebased patch on next-20251010
- Reordered 'status' property within the node to follow the ordering
specified by:
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
Regards,
Siddharth.
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 1 +
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 45311438315f..5906dfa97205 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -769,6 +769,7 @@ exp5: gpio@20 {
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
+ status = "okay";
};
&davinci_mdio {
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index 42a21398e389..d5e5e89be5e9 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -551,6 +551,8 @@ mcu_cpsw: ethernet@46000000 {
"tx4", "tx5", "tx6", "tx7",
"rx";
+ status = "disabled";
+
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
--
2.51.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v3 5/5] arm64: dts: ti: k3-j721s2: disable "mcu_cpsw" in SoC file and enable in board files
2025-10-14 12:53 [PATCH v3 0/5] TI-K3-DTS: Cleanup CPSW DT Nodes Siddharth Vadapalli
` (3 preceding siblings ...)
2025-10-14 12:53 ` [PATCH v3 4/5] arm64: dts: ti: k3-j721e: disable "mcu_cpsw" in SoC file and enable it " Siddharth Vadapalli
@ 2025-10-14 12:53 ` Siddharth Vadapalli
2025-10-14 17:07 ` [PATCH v3 0/5] TI-K3-DTS: Cleanup CPSW DT Nodes Dominik Haller
5 siblings, 0 replies; 9+ messages in thread
From: Siddharth Vadapalli @ 2025-10-14 12:53 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
Following the existing convention of disabling nodes in the SoC file and
enabling only the required ones in the board file, disable "mcu_cpsw" node
in the SoC file "k3-j721s2-mcu-wakeup.dtsi" and enable it in the board
files:
a) k3-am68-sk-base-board.dts
b) k3-j721s2-common-proc-board.dts
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v2 of this patch is at:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250611114336.2392320-6-s-vadapalli@ti.com/
Changes since v2:
- Rebased patch on next-20251010
- Reordered 'status' property within the node to follow the ordering
specified by:
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
Regards,
Siddharth.
arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 1 +
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 1 +
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 ++
3 files changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
index 75a107456ce1..e44542b1584c 100644
--- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
@@ -692,6 +692,7 @@ &main_sdhci1 {
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
+ status = "okay";
};
&davinci_mdio {
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 9e43dcff8ef2..3740596576c0 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -457,6 +457,7 @@ &main_sdhci1 {
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
+ status = "okay";
};
&davinci_mdio {
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 837097751c18..2a7f9c519735 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -552,6 +552,8 @@ mcu_cpsw: ethernet@46000000 {
"tx4", "tx5", "tx6", "tx7",
"rx";
+ status = "disabled";
+
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
--
2.51.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v3 0/5] TI-K3-DTS: Cleanup CPSW DT Nodes
2025-10-14 12:53 [PATCH v3 0/5] TI-K3-DTS: Cleanup CPSW DT Nodes Siddharth Vadapalli
` (4 preceding siblings ...)
2025-10-14 12:53 ` [PATCH v3 5/5] arm64: dts: ti: k3-j721s2: disable "mcu_cpsw" in SoC file and enable in board files Siddharth Vadapalli
@ 2025-10-14 17:07 ` Dominik Haller
2025-10-15 4:58 ` Siddharth Vadapalli
5 siblings, 1 reply; 9+ messages in thread
From: Dominik Haller @ 2025-10-14 17:07 UTC (permalink / raw)
To: nm@ti.com, s-vadapalli@ti.com, vigneshr@ti.com, kristo@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, robh@kernel.org
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, srk@ti.com
On Di, 2025-10-14 at 18:23 +0530, Siddharth Vadapalli wrote:
> Hello,
>
> This series cleans up the CPSW Device-tree nodes by updating the SoC
> and
> board files to keep CPSW disabled in the SoC files and enable it only
> in
> the board files.
>
> The following is a summary of the SoCs, CPSW instance and the Boards
> that
> this series affects:
Hello Siddharth,
please also enable cpsw3g in our k3-am62-phycore-som.dtsi and mcu_cpsw
in our k3-am68-phyboard-izar.dts.
Unless I'm missing some other patches you're turning off ethernet on
those two both platforms too.
Thanks
Dominik
>
> ----- ------- ---------------- -------------------------------
> -------------
> S.No. SoC CPSW Instance Board(s)
> ----- ------- ---------------- -------------------------------
> -------------
> 1. AM62 CPSW3G AM625-Beagleplay, AM62-LP-
> SK, AM625-SK
> 2. AM65 MCU CPSW2G AM654-Base-Board, IOT-2050
> Based Boards
> 3. J7200 MCU CPSW2G J7200-Common-Processor-
> Board
> 4. J721E MCU CPSW2G J721E-Common-Processor-
> Board
> 5. J721S2 MCU CPSW2G AM68-SK-Base-Board, J721S2-
> Common-Processor-Board
>
> Series is based on linux-next tagged next-20251010.
>
> v2 of this series is at:
> https://patchwork.kernel.org/project/linux-arm-kernel/cover/20250611114336.2392320-1-s-vadapalli@ti.com/
> Changes since v2:
> - Rebased series on next-20251010.
> - In the first patch, the changes that were made within
> 'k3-am625-sk.dts' in the previous version, have been
> moved into 'k3-am625-sk-common.dtsi'
> - The 'status' property within 'nodes' has been ordered to follow:
>
> https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
>
> Test Logs:
> 1. AM654-Base-Board:
> https://gist.github.com/Siddharth-Vadapalli-at-TI/3af178c71cd2da436f60b87928dcb1eb
> 2. AM68-SK-Base-Board:
> https://gist.github.com/Siddharth-Vadapalli-at-TI/b027a6849f3c17e11fad8324a905aa68
> 3. J7200-Common-Processor-Board:
> https://gist.github.com/Siddharth-Vadapalli-at-TI/70d0d96fab92b894253c1884499d6fc1
> 4. J721E-Common-Processor-Board:
> https://gist.github.com/Siddharth-Vadapalli-at-TI/2c88aadf36923b1d27672b64489cb2dc
> 5. J721S2-Common-Processor-Board:
> https://gist.github.com/Siddharth-Vadapalli-at-TI/0abbae2ef99f82871aa520e1ab973c85
>
> Regards,
> Siddharth.
>
> Siddharth Vadapalli (5):
> arm64: dts: ti: k3-am62: disable "cpsw3g" in SoC file and enable in
> board file
> arm64: dts: ti: k3-am65: disable "mcu_cpsw" in SoC file and enable
> in
> board file
> arm64: dts: ti: k3-j7200: disable "mcu_cpsw" in SoC file and enable
> in
> board file
> arm64: dts: ti: k3-j721e: disable "mcu_cpsw" in SoC file and enable
> it
> in board file
> arm64: dts: ti: k3-j721s2: disable "mcu_cpsw" in SoC file and
> enable
> in board files
>
> arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 4 ++++
> arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 2 ++
> arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 1 +
> arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 4 ----
> arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 ++
> arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 +
> arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 1 +
> arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 1 +
> arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++
> arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 1 +
> arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 ++
> arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 1 +
> arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 ++
> 14 files changed, 21 insertions(+), 4 deletions(-)
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v3 0/5] TI-K3-DTS: Cleanup CPSW DT Nodes
2025-10-14 17:07 ` [PATCH v3 0/5] TI-K3-DTS: Cleanup CPSW DT Nodes Dominik Haller
@ 2025-10-15 4:58 ` Siddharth Vadapalli
2025-10-15 11:16 ` Siddharth Vadapalli
0 siblings, 1 reply; 9+ messages in thread
From: Siddharth Vadapalli @ 2025-10-15 4:58 UTC (permalink / raw)
To: Dominik Haller
Cc: nm@ti.com, vigneshr@ti.com, kristo@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, robh@kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, srk@ti.com, s-vadapalli@ti.com
On Tue, 2025-10-14 at 17:07 +0000, Dominik Haller wrote:
> On Di, 2025-10-14 at 18:23 +0530, Siddharth Vadapalli wrote:
> > Hello,
> >
> > This series cleans up the CPSW Device-tree nodes by updating the SoC
> > and
> > board files to keep CPSW disabled in the SoC files and enable it only
> > in
> > the board files.
> >
> > The following is a summary of the SoCs, CPSW instance and the Boards
> > that
> > this series affects:
> Hello Siddharth,
>
> please also enable cpsw3g in our k3-am62-phycore-som.dtsi and mcu_cpsw
> in our k3-am68-phyboard-izar.dts.
> Unless I'm missing some other patches you're turning off ethernet on
> those two both platforms too.
Thank you for pointing it out. I will include them and post the v4 series.
Regards,
Siddharth.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 0/5] TI-K3-DTS: Cleanup CPSW DT Nodes
2025-10-15 4:58 ` Siddharth Vadapalli
@ 2025-10-15 11:16 ` Siddharth Vadapalli
0 siblings, 0 replies; 9+ messages in thread
From: Siddharth Vadapalli @ 2025-10-15 11:16 UTC (permalink / raw)
To: Dominik Haller
Cc: nm@ti.com, vigneshr@ti.com, kristo@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, robh@kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, srk@ti.com, s-vadapalli@ti.com
On Wed, 2025-10-15 at 10:28 +0530, Siddharth Vadapalli wrote:
> On Tue, 2025-10-14 at 17:07 +0000, Dominik Haller wrote:
> > On Di, 2025-10-14 at 18:23 +0530, Siddharth Vadapalli wrote:
> > > Hello,
> > >
> > > This series cleans up the CPSW Device-tree nodes by updating the SoC
> > > and
> > > board files to keep CPSW disabled in the SoC files and enable it only
> > > in
> > > the board files.
> > >
> > > The following is a summary of the SoCs, CPSW instance and the Boards
> > > that
> > > this series affects:
> > Hello Siddharth,
> >
> > please also enable cpsw3g in our k3-am62-phycore-som.dtsi and mcu_cpsw
> > in our k3-am68-phyboard-izar.dts.
> > Unless I'm missing some other patches you're turning off ethernet on
> > those two both platforms too.
>
> Thank you for pointing it out. I will include them and post the v4 series.
I have implemented the feedback and have posted the v4 series at:
https://lore.kernel.org/r/20251015111344.3639415-1-s-vadapalli@ti.com/
Regards,
Siddharth.
^ permalink raw reply [flat|nested] 9+ messages in thread