From: Krzysztof Kozlowski <krzk@kernel.org>
To: Sherry Sun <sherry.sun@nxp.com>,
robh+dt@kernel.org, krzk+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-imx@nxp.com,
Dinh Nguyen <dinguyen@kernel.org>
Subject: Re: [PATCH] arm64: dts: imx8mp: add ddr controller node to support EDAC on imx8mp
Date: Fri, 18 Mar 2022 12:56:01 +0100 [thread overview]
Message-ID: <df985bc1-bb99-9623-ad78-b77329b8eba7@kernel.org> (raw)
In-Reply-To: <20220318113526.15986-1-sherry.sun@nxp.com>
On 18/03/2022 12:35, Sherry Sun wrote:
> i.MX8MP use synopsys V3.70a ddr controller IP, so add edac support
> for i.MX8MP based on "snps,ddrc-3.80a" synopsys edac driver.
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 794d75173cf5..a6124a11d6ee 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -902,6 +902,12 @@
> interrupt-parent = <&gic>;
> };
>
> + edacmc: memory-controller@3d400000 {
> + compatible = "snps,ddrc-3.80a";
> + reg = <0x3d400000 0x400000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
This is not correct according to the bindings. Dinh's commit adding the
compatible might not be correct, so please first fix bindings.
While fixing bindings, order the compatibles by name (s goes before x).
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-03-18 11:56 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-18 11:35 [PATCH] arm64: dts: imx8mp: add ddr controller node to support EDAC on imx8mp Sherry Sun
2022-03-18 11:56 ` Krzysztof Kozlowski [this message]
2022-03-21 6:18 ` Sherry Sun
2022-03-18 12:14 ` Krzysztof Kozlowski
2022-03-19 9:53 ` Sherry Sun
2022-03-19 14:37 ` Krzysztof Kozlowski
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