Re: [PATCH v8 5/8] dt-bindings: arm: add an interrupt property for Coresight CTCU

[Jie Gan <jie.gan@oss.qualcomm.com>]

On 12/11/2025 9:37 PM, Rob Herring wrote:
> On Thu, Dec 11, 2025 at 02:10:44PM +0800, Jie Gan wrote:
>> Add an interrupt property to CTCU device. The interrupt will be triggered
>> when the data size in the ETR buffer exceeds the threshold of the
>> BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register
>> of CTCU device will enable the interrupt.
>>
>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Reviewed-by: Mike Leach <mike.leach@linaro.org>
>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> ---
>>   .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml    | 17 +++++++++++++++++
>>   1 file changed, 17 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>> index c969c16c21ef..90f88cc6cd3e 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>> @@ -39,6 +39,16 @@ properties:
>>       items:
>>         - const: apb
>>   
>> +  interrupts:
>> +    items:
>> +      - description: Byte cntr interrupt for the first etr device
>> +      - description: Byte cntr interrupt for the second etr device
>> +
>> +  interrupt-names:
>> +    items:
>> +      - const: etrirq0
>> +      - const: etrirq1
> 
> Names are kind of pointless when it is just foo<index>.

Hi Rob,

I was naming them as etr0/etr1. Are these names acceptable?
The interrupts are assigned exclusively to a specific ETR device.

But Suzuki is concerned that this might cause confusion because the ETR 
device is named randomly in the driver. Suzuki suggested using ‘port-0’ 
and ‘port-1’ and would also like to hear your feedback on these names.

Usually, the probe sequence follows the order of the addresses. In our 
specification, ‘ETR0’ is always probed before ‘ETR1’ because its address 
is lower.

I would greatly appreciate your suggestion for the interrupt name, if 
possible.

Thanks,
Jie

> 
>> +
>>     label:
>>       description:
>>         Description of a coresight device.
>> @@ -60,6 +70,8 @@ additionalProperties: false
>>   
>>   examples:
>>     - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>>       ctcu@1001000 {
>>           compatible = "qcom,sa8775p-ctcu";
>>           reg = <0x1001000 0x1000>;
>> @@ -67,6 +79,11 @@ examples:
>>           clocks = <&aoss_qmp>;
>>           clock-names = "apb";
>>   
>> +        interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
>> +                     <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
>> +        interrupt-names = "etrirq0",
>> +                          "etrirq1;
>> +
>>           in-ports {
>>               #address-cells = <1>;
>>               #size-cells = <0>;
>>
>> -- 
>> 2.34.1
>>